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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/proc-sa1100.S | |
3 | * | |
4 | * Copyright (C) 1997-2002 Russell King | |
d090ddda | 5 | * hacked for non-paged-MM by Hyok S. Choi, 2003. |
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6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * MMU functions for SA110 | |
12 | * | |
13 | * These are the low level assembler for performing cache and TLB | |
14 | * functions on the StrongARM-1100 and StrongARM-1110. | |
15 | * | |
16 | * Note that SA1100 and SA1110 share everything but their name and CPU ID. | |
17 | * | |
18 | * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl): | |
19 | * Flush the read buffer at context switches | |
20 | */ | |
21 | #include <linux/linkage.h> | |
22 | #include <linux/init.h> | |
23 | #include <asm/assembler.h> | |
e6ae744d | 24 | #include <asm/asm-offsets.h> |
5ec9407d | 25 | #include <asm/hwcap.h> |
a09e64fb | 26 | #include <mach/hardware.h> |
74945c86 | 27 | #include <asm/pgtable-hwdef.h> |
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28 | #include <asm/pgtable.h> |
29 | ||
bb8d5a55 TG |
30 | #include "proc-macros.S" |
31 | ||
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32 | /* |
33 | * the cache line size of the I and D cache | |
34 | */ | |
35 | #define DCACHELINESIZE 32 | |
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36 | |
37 | __INIT | |
38 | ||
39 | /* | |
40 | * cpu_sa1100_proc_init() | |
41 | */ | |
42 | ENTRY(cpu_sa1100_proc_init) | |
43 | mov r0, #0 | |
44 | mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching | |
45 | mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland | |
46 | mov pc, lr | |
47 | ||
4260415f | 48 | .section .text |
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49 | |
50 | /* | |
51 | * cpu_sa1100_proc_fin() | |
52 | * | |
53 | * Prepare the CPU for reset: | |
54 | * - Disable interrupts | |
55 | * - Clean and turn off caches. | |
56 | */ | |
57 | ENTRY(cpu_sa1100_proc_fin) | |
95f3df6b | 58 | mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching |
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59 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
60 | bic r0, r0, #0x1000 @ ...i............ | |
61 | bic r0, r0, #0x000e @ ............wca. | |
62 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
9ca03a21 | 63 | mov pc, lr |
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64 | |
65 | /* | |
66 | * cpu_sa1100_reset(loc) | |
67 | * | |
68 | * Perform a soft reset of the system. Put the CPU into the | |
69 | * same state as it would be if it had been reset, and branch | |
70 | * to what would be the reset vector. | |
71 | * | |
72 | * loc: location to jump to for soft reset | |
73 | */ | |
74 | .align 5 | |
75 | ENTRY(cpu_sa1100_reset) | |
76 | mov ip, #0 | |
77 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | |
78 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
d090ddda | 79 | #ifdef CONFIG_MMU |
1da177e4 | 80 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
d090ddda | 81 | #endif |
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82 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register |
83 | bic ip, ip, #0x000f @ ............wcam | |
84 | bic ip, ip, #0x1100 @ ...i...s........ | |
85 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | |
86 | mov pc, r0 | |
87 | ||
88 | /* | |
89 | * cpu_sa1100_do_idle(type) | |
90 | * | |
91 | * Cause the processor to idle | |
92 | * | |
93 | * type: call type: | |
94 | * 0 = slow idle | |
95 | * 1 = fast idle | |
96 | * 2 = switch to slow processor clock | |
97 | * 3 = switch to fast processor clock | |
98 | */ | |
99 | .align 5 | |
100 | ENTRY(cpu_sa1100_do_idle) | |
101 | mov r0, r0 @ 4 nop padding | |
102 | mov r0, r0 | |
103 | mov r0, r0 | |
104 | mov r0, r0 @ 4 nop padding | |
105 | mov r0, r0 | |
106 | mov r0, r0 | |
107 | mov r0, #0 | |
108 | ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address | |
109 | @ --- aligned to a cache line | |
110 | mcr p15, 0, r0, c15, c2, 2 @ disable clock switching | |
111 | ldr r1, [r1, #0] @ force switch to MCLK | |
112 | mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt | |
113 | mov r0, r0 @ safety | |
114 | mcr p15, 0, r0, c15, c1, 2 @ enable clock switching | |
115 | mov pc, lr | |
116 | ||
117 | /* ================================= CACHE ================================ */ | |
118 | ||
119 | /* | |
120 | * cpu_sa1100_dcache_clean_area(addr,sz) | |
121 | * | |
122 | * Clean the specified entry of any caches such that the MMU | |
123 | * translation fetches will obtain correct data. | |
124 | * | |
125 | * addr: cache-unaligned virtual address | |
126 | */ | |
127 | .align 5 | |
128 | ENTRY(cpu_sa1100_dcache_clean_area) | |
129 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
130 | add r0, r0, #DCACHELINESIZE | |
131 | subs r1, r1, #DCACHELINESIZE | |
132 | bhi 1b | |
133 | mov pc, lr | |
134 | ||
135 | /* =============================== PageTable ============================== */ | |
136 | ||
137 | /* | |
138 | * cpu_sa1100_switch_mm(pgd) | |
139 | * | |
140 | * Set the translation base pointer to be as described by pgd. | |
141 | * | |
142 | * pgd: new page tables | |
143 | */ | |
144 | .align 5 | |
145 | ENTRY(cpu_sa1100_switch_mm) | |
d090ddda | 146 | #ifdef CONFIG_MMU |
95f3df6b RK |
147 | str lr, [sp, #-4]! |
148 | bl v4wb_flush_kern_cache_all @ clears IP | |
1da177e4 | 149 | mcr p15, 0, ip, c9, c0, 0 @ invalidate RB |
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150 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer |
151 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | |
95f3df6b | 152 | ldr pc, [sp], #4 |
d090ddda HC |
153 | #else |
154 | mov pc, lr | |
155 | #endif | |
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156 | |
157 | /* | |
ad1ae2fe | 158 | * cpu_sa1100_set_pte_ext(ptep, pte, ext) |
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159 | * |
160 | * Set a PTE and flush it out | |
161 | */ | |
162 | .align 5 | |
ad1ae2fe | 163 | ENTRY(cpu_sa1100_set_pte_ext) |
d090ddda | 164 | #ifdef CONFIG_MMU |
da091653 | 165 | armv3_set_pte_ext wc_disable=0 |
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166 | mov r0, r0 |
167 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
168 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
d090ddda | 169 | #endif |
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170 | mov pc, lr |
171 | ||
f6b0fa02 RK |
172 | .globl cpu_sa1100_suspend_size |
173 | .equ cpu_sa1100_suspend_size, 4*4 | |
29ea23ff | 174 | #ifdef CONFIG_PM_SLEEP |
f6b0fa02 RK |
175 | ENTRY(cpu_sa1100_do_suspend) |
176 | stmfd sp!, {r4 - r7, lr} | |
177 | mrc p15, 0, r4, c3, c0, 0 @ domain ID | |
178 | mrc p15, 0, r5, c2, c0, 0 @ translation table base addr | |
179 | mrc p15, 0, r6, c13, c0, 0 @ PID | |
180 | mrc p15, 0, r7, c1, c0, 0 @ control reg | |
181 | stmia r0, {r4 - r7} @ store cp regs | |
182 | ldmfd sp!, {r4 - r7, pc} | |
183 | ENDPROC(cpu_sa1100_do_suspend) | |
184 | ||
185 | ENTRY(cpu_sa1100_do_resume) | |
186 | ldmia r0, {r4 - r7} @ load cp regs | |
187 | mov r1, #0 | |
188 | mcr p15, 0, r1, c8, c7, 0 @ flush I+D TLBs | |
189 | mcr p15, 0, r1, c7, c7, 0 @ flush I&D cache | |
190 | mcr p15, 0, r1, c9, c0, 0 @ invalidate RB | |
191 | mcr p15, 0, r1, c9, c0, 5 @ allow user space to use RB | |
192 | ||
193 | mcr p15, 0, r4, c3, c0, 0 @ domain ID | |
194 | mcr p15, 0, r5, c2, c0, 0 @ translation table base addr | |
195 | mcr p15, 0, r6, c13, c0, 0 @ PID | |
196 | mov r0, r7 @ control register | |
197 | mov r2, r5, lsr #14 @ get TTB0 base | |
198 | mov r2, r2, lsl #14 | |
199 | ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ | |
200 | PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE | |
201 | b cpu_resume_mmu | |
202 | ENDPROC(cpu_sa1100_do_resume) | |
203 | #else | |
204 | #define cpu_sa1100_do_suspend 0 | |
205 | #define cpu_sa1100_do_resume 0 | |
206 | #endif | |
207 | ||
5085f3ff | 208 | __CPUINIT |
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209 | |
210 | .type __sa1100_setup, #function | |
211 | __sa1100_setup: | |
212 | mov r0, #0 | |
213 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 | |
214 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 | |
d090ddda | 215 | #ifdef CONFIG_MMU |
1da177e4 | 216 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 |
d090ddda | 217 | #endif |
22b19086 RK |
218 | adr r5, sa1100_crval |
219 | ldmia r5, {r5, r6} | |
1da177e4 | 220 | mrc p15, 0, r0, c1, c0 @ get control register v4 |
1da177e4 | 221 | bic r0, r0, r5 |
22b19086 | 222 | orr r0, r0, r6 |
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223 | mov pc, lr |
224 | .size __sa1100_setup, . - __sa1100_setup | |
225 | ||
226 | /* | |
227 | * R | |
228 | * .RVI ZFRS BLDP WCAM | |
229 | * ..11 0001 ..11 1101 | |
230 | * | |
231 | */ | |
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232 | .type sa1100_crval, #object |
233 | sa1100_crval: | |
234 | crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130 | |
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235 | |
236 | __INITDATA | |
237 | ||
238 | /* | |
239 | * Purpose : Function pointers used to access above functions - all calls | |
240 | * come through these | |
241 | */ | |
242 | ||
243 | /* | |
244 | * SA1100 and SA1110 share the same function calls | |
245 | */ | |
246 | .type sa1100_processor_functions, #object | |
247 | ENTRY(sa1100_processor_functions) | |
248 | .word v4_early_abort | |
4fb28474 | 249 | .word legacy_pabort |
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250 | .word cpu_sa1100_proc_init |
251 | .word cpu_sa1100_proc_fin | |
252 | .word cpu_sa1100_reset | |
253 | .word cpu_sa1100_do_idle | |
254 | .word cpu_sa1100_dcache_clean_area | |
255 | .word cpu_sa1100_switch_mm | |
ad1ae2fe | 256 | .word cpu_sa1100_set_pte_ext |
f6b0fa02 RK |
257 | .word cpu_sa1100_suspend_size |
258 | .word cpu_sa1100_do_suspend | |
259 | .word cpu_sa1100_do_resume | |
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260 | .size sa1100_processor_functions, . - sa1100_processor_functions |
261 | ||
262 | .section ".rodata" | |
263 | ||
264 | .type cpu_arch_name, #object | |
265 | cpu_arch_name: | |
266 | .asciz "armv4" | |
267 | .size cpu_arch_name, . - cpu_arch_name | |
268 | ||
269 | .type cpu_elf_name, #object | |
270 | cpu_elf_name: | |
271 | .asciz "v4" | |
272 | .size cpu_elf_name, . - cpu_elf_name | |
273 | ||
274 | .type cpu_sa1100_name, #object | |
275 | cpu_sa1100_name: | |
276 | .asciz "StrongARM-1100" | |
277 | .size cpu_sa1100_name, . - cpu_sa1100_name | |
278 | ||
279 | .type cpu_sa1110_name, #object | |
280 | cpu_sa1110_name: | |
281 | .asciz "StrongARM-1110" | |
282 | .size cpu_sa1110_name, . - cpu_sa1110_name | |
283 | ||
284 | .align | |
285 | ||
02b7dd12 | 286 | .section ".proc.info.init", #alloc, #execinstr |
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287 | |
288 | .type __sa1100_proc_info,#object | |
289 | __sa1100_proc_info: | |
290 | .long 0x4401a110 | |
291 | .long 0xfffffff0 | |
292 | .long PMD_TYPE_SECT | \ | |
293 | PMD_SECT_BUFFERABLE | \ | |
294 | PMD_SECT_CACHEABLE | \ | |
295 | PMD_SECT_AP_WRITE | \ | |
296 | PMD_SECT_AP_READ | |
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297 | .long PMD_TYPE_SECT | \ |
298 | PMD_SECT_AP_WRITE | \ | |
299 | PMD_SECT_AP_READ | |
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300 | b __sa1100_setup |
301 | .long cpu_arch_name | |
302 | .long cpu_elf_name | |
303 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT | |
304 | .long cpu_sa1100_name | |
305 | .long sa1100_processor_functions | |
306 | .long v4wb_tlb_fns | |
307 | .long v4_mc_user_fns | |
308 | .long v4wb_cache_fns | |
309 | .size __sa1100_proc_info, . - __sa1100_proc_info | |
310 | ||
311 | .type __sa1110_proc_info,#object | |
312 | __sa1110_proc_info: | |
313 | .long 0x6901b110 | |
314 | .long 0xfffffff0 | |
315 | .long PMD_TYPE_SECT | \ | |
316 | PMD_SECT_BUFFERABLE | \ | |
317 | PMD_SECT_CACHEABLE | \ | |
318 | PMD_SECT_AP_WRITE | \ | |
319 | PMD_SECT_AP_READ | |
8799ee9f RK |
320 | .long PMD_TYPE_SECT | \ |
321 | PMD_SECT_AP_WRITE | \ | |
322 | PMD_SECT_AP_READ | |
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323 | b __sa1100_setup |
324 | .long cpu_arch_name | |
325 | .long cpu_elf_name | |
326 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT | |
327 | .long cpu_sa1110_name | |
328 | .long sa1100_processor_functions | |
329 | .long v4wb_tlb_fns | |
330 | .long v4_mc_user_fns | |
331 | .long v4wb_cache_fns | |
332 | .size __sa1110_proc_info, . - __sa1110_proc_info |