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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/proc-sa1100.S | |
3 | * | |
4 | * Copyright (C) 1997-2002 Russell King | |
d090ddda | 5 | * hacked for non-paged-MM by Hyok S. Choi, 2003. |
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6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * MMU functions for SA110 | |
12 | * | |
13 | * These are the low level assembler for performing cache and TLB | |
14 | * functions on the StrongARM-1100 and StrongARM-1110. | |
15 | * | |
16 | * Note that SA1100 and SA1110 share everything but their name and CPU ID. | |
17 | * | |
18 | * 12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl): | |
19 | * Flush the read buffer at context switches | |
20 | */ | |
21 | #include <linux/linkage.h> | |
22 | #include <linux/init.h> | |
23 | #include <asm/assembler.h> | |
e6ae744d | 24 | #include <asm/asm-offsets.h> |
ee90dabc | 25 | #include <asm/elf.h> |
1da177e4 | 26 | #include <asm/hardware.h> |
74945c86 | 27 | #include <asm/pgtable-hwdef.h> |
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28 | #include <asm/pgtable.h> |
29 | ||
bb8d5a55 TG |
30 | #include "proc-macros.S" |
31 | ||
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32 | /* |
33 | * the cache line size of the I and D cache | |
34 | */ | |
35 | #define DCACHELINESIZE 32 | |
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36 | |
37 | __INIT | |
38 | ||
39 | /* | |
40 | * cpu_sa1100_proc_init() | |
41 | */ | |
42 | ENTRY(cpu_sa1100_proc_init) | |
43 | mov r0, #0 | |
44 | mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching | |
45 | mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland | |
46 | mov pc, lr | |
47 | ||
48 | .previous | |
49 | ||
50 | /* | |
51 | * cpu_sa1100_proc_fin() | |
52 | * | |
53 | * Prepare the CPU for reset: | |
54 | * - Disable interrupts | |
55 | * - Clean and turn off caches. | |
56 | */ | |
57 | ENTRY(cpu_sa1100_proc_fin) | |
58 | stmfd sp!, {lr} | |
59 | mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE | |
60 | msr cpsr_c, ip | |
95f3df6b RK |
61 | bl v4wb_flush_kern_cache_all |
62 | mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching | |
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63 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
64 | bic r0, r0, #0x1000 @ ...i............ | |
65 | bic r0, r0, #0x000e @ ............wca. | |
66 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
67 | ldmfd sp!, {pc} | |
68 | ||
69 | /* | |
70 | * cpu_sa1100_reset(loc) | |
71 | * | |
72 | * Perform a soft reset of the system. Put the CPU into the | |
73 | * same state as it would be if it had been reset, and branch | |
74 | * to what would be the reset vector. | |
75 | * | |
76 | * loc: location to jump to for soft reset | |
77 | */ | |
78 | .align 5 | |
79 | ENTRY(cpu_sa1100_reset) | |
80 | mov ip, #0 | |
81 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | |
82 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
d090ddda | 83 | #ifdef CONFIG_MMU |
1da177e4 | 84 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
d090ddda | 85 | #endif |
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86 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register |
87 | bic ip, ip, #0x000f @ ............wcam | |
88 | bic ip, ip, #0x1100 @ ...i...s........ | |
89 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | |
90 | mov pc, r0 | |
91 | ||
92 | /* | |
93 | * cpu_sa1100_do_idle(type) | |
94 | * | |
95 | * Cause the processor to idle | |
96 | * | |
97 | * type: call type: | |
98 | * 0 = slow idle | |
99 | * 1 = fast idle | |
100 | * 2 = switch to slow processor clock | |
101 | * 3 = switch to fast processor clock | |
102 | */ | |
103 | .align 5 | |
104 | ENTRY(cpu_sa1100_do_idle) | |
105 | mov r0, r0 @ 4 nop padding | |
106 | mov r0, r0 | |
107 | mov r0, r0 | |
108 | mov r0, r0 @ 4 nop padding | |
109 | mov r0, r0 | |
110 | mov r0, r0 | |
111 | mov r0, #0 | |
112 | ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address | |
113 | @ --- aligned to a cache line | |
114 | mcr p15, 0, r0, c15, c2, 2 @ disable clock switching | |
115 | ldr r1, [r1, #0] @ force switch to MCLK | |
116 | mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt | |
117 | mov r0, r0 @ safety | |
118 | mcr p15, 0, r0, c15, c1, 2 @ enable clock switching | |
119 | mov pc, lr | |
120 | ||
121 | /* ================================= CACHE ================================ */ | |
122 | ||
123 | /* | |
124 | * cpu_sa1100_dcache_clean_area(addr,sz) | |
125 | * | |
126 | * Clean the specified entry of any caches such that the MMU | |
127 | * translation fetches will obtain correct data. | |
128 | * | |
129 | * addr: cache-unaligned virtual address | |
130 | */ | |
131 | .align 5 | |
132 | ENTRY(cpu_sa1100_dcache_clean_area) | |
133 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
134 | add r0, r0, #DCACHELINESIZE | |
135 | subs r1, r1, #DCACHELINESIZE | |
136 | bhi 1b | |
137 | mov pc, lr | |
138 | ||
139 | /* =============================== PageTable ============================== */ | |
140 | ||
141 | /* | |
142 | * cpu_sa1100_switch_mm(pgd) | |
143 | * | |
144 | * Set the translation base pointer to be as described by pgd. | |
145 | * | |
146 | * pgd: new page tables | |
147 | */ | |
148 | .align 5 | |
149 | ENTRY(cpu_sa1100_switch_mm) | |
d090ddda | 150 | #ifdef CONFIG_MMU |
95f3df6b RK |
151 | str lr, [sp, #-4]! |
152 | bl v4wb_flush_kern_cache_all @ clears IP | |
1da177e4 | 153 | mcr p15, 0, ip, c9, c0, 0 @ invalidate RB |
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154 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer |
155 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | |
95f3df6b | 156 | ldr pc, [sp], #4 |
d090ddda HC |
157 | #else |
158 | mov pc, lr | |
159 | #endif | |
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160 | |
161 | /* | |
ad1ae2fe | 162 | * cpu_sa1100_set_pte_ext(ptep, pte, ext) |
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163 | * |
164 | * Set a PTE and flush it out | |
165 | */ | |
166 | .align 5 | |
ad1ae2fe | 167 | ENTRY(cpu_sa1100_set_pte_ext) |
d090ddda | 168 | #ifdef CONFIG_MMU |
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169 | str r1, [r0], #-2048 @ linux version |
170 | ||
171 | eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY | |
172 | ||
173 | bic r2, r1, #PTE_SMALL_AP_MASK | |
174 | bic r2, r2, #PTE_TYPE_MASK | |
175 | orr r2, r2, #PTE_TYPE_SMALL | |
176 | ||
177 | tst r1, #L_PTE_USER @ User? | |
178 | orrne r2, r2, #PTE_SMALL_AP_URO_SRW | |
179 | ||
180 | tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? | |
181 | orreq r2, r2, #PTE_SMALL_AP_UNO_SRW | |
182 | ||
183 | tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? | |
184 | movne r2, #0 | |
185 | ||
186 | str r2, [r0] @ hardware version | |
187 | mov r0, r0 | |
188 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
189 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
d090ddda | 190 | #endif |
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191 | mov pc, lr |
192 | ||
193 | __INIT | |
194 | ||
195 | .type __sa1100_setup, #function | |
196 | __sa1100_setup: | |
197 | mov r0, #0 | |
198 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 | |
199 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 | |
d090ddda | 200 | #ifdef CONFIG_MMU |
1da177e4 | 201 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 |
d090ddda | 202 | #endif |
22b19086 RK |
203 | adr r5, sa1100_crval |
204 | ldmia r5, {r5, r6} | |
1da177e4 | 205 | mrc p15, 0, r0, c1, c0 @ get control register v4 |
1da177e4 | 206 | bic r0, r0, r5 |
22b19086 | 207 | orr r0, r0, r6 |
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208 | mov pc, lr |
209 | .size __sa1100_setup, . - __sa1100_setup | |
210 | ||
211 | /* | |
212 | * R | |
213 | * .RVI ZFRS BLDP WCAM | |
214 | * ..11 0001 ..11 1101 | |
215 | * | |
216 | */ | |
22b19086 RK |
217 | .type sa1100_crval, #object |
218 | sa1100_crval: | |
219 | crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130 | |
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220 | |
221 | __INITDATA | |
222 | ||
223 | /* | |
224 | * Purpose : Function pointers used to access above functions - all calls | |
225 | * come through these | |
226 | */ | |
227 | ||
228 | /* | |
229 | * SA1100 and SA1110 share the same function calls | |
230 | */ | |
231 | .type sa1100_processor_functions, #object | |
232 | ENTRY(sa1100_processor_functions) | |
233 | .word v4_early_abort | |
234 | .word cpu_sa1100_proc_init | |
235 | .word cpu_sa1100_proc_fin | |
236 | .word cpu_sa1100_reset | |
237 | .word cpu_sa1100_do_idle | |
238 | .word cpu_sa1100_dcache_clean_area | |
239 | .word cpu_sa1100_switch_mm | |
ad1ae2fe | 240 | .word cpu_sa1100_set_pte_ext |
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241 | .size sa1100_processor_functions, . - sa1100_processor_functions |
242 | ||
243 | .section ".rodata" | |
244 | ||
245 | .type cpu_arch_name, #object | |
246 | cpu_arch_name: | |
247 | .asciz "armv4" | |
248 | .size cpu_arch_name, . - cpu_arch_name | |
249 | ||
250 | .type cpu_elf_name, #object | |
251 | cpu_elf_name: | |
252 | .asciz "v4" | |
253 | .size cpu_elf_name, . - cpu_elf_name | |
254 | ||
255 | .type cpu_sa1100_name, #object | |
256 | cpu_sa1100_name: | |
257 | .asciz "StrongARM-1100" | |
258 | .size cpu_sa1100_name, . - cpu_sa1100_name | |
259 | ||
260 | .type cpu_sa1110_name, #object | |
261 | cpu_sa1110_name: | |
262 | .asciz "StrongARM-1110" | |
263 | .size cpu_sa1110_name, . - cpu_sa1110_name | |
264 | ||
265 | .align | |
266 | ||
02b7dd12 | 267 | .section ".proc.info.init", #alloc, #execinstr |
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268 | |
269 | .type __sa1100_proc_info,#object | |
270 | __sa1100_proc_info: | |
271 | .long 0x4401a110 | |
272 | .long 0xfffffff0 | |
273 | .long PMD_TYPE_SECT | \ | |
274 | PMD_SECT_BUFFERABLE | \ | |
275 | PMD_SECT_CACHEABLE | \ | |
276 | PMD_SECT_AP_WRITE | \ | |
277 | PMD_SECT_AP_READ | |
8799ee9f RK |
278 | .long PMD_TYPE_SECT | \ |
279 | PMD_SECT_AP_WRITE | \ | |
280 | PMD_SECT_AP_READ | |
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281 | b __sa1100_setup |
282 | .long cpu_arch_name | |
283 | .long cpu_elf_name | |
284 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT | |
285 | .long cpu_sa1100_name | |
286 | .long sa1100_processor_functions | |
287 | .long v4wb_tlb_fns | |
288 | .long v4_mc_user_fns | |
289 | .long v4wb_cache_fns | |
290 | .size __sa1100_proc_info, . - __sa1100_proc_info | |
291 | ||
292 | .type __sa1110_proc_info,#object | |
293 | __sa1110_proc_info: | |
294 | .long 0x6901b110 | |
295 | .long 0xfffffff0 | |
296 | .long PMD_TYPE_SECT | \ | |
297 | PMD_SECT_BUFFERABLE | \ | |
298 | PMD_SECT_CACHEABLE | \ | |
299 | PMD_SECT_AP_WRITE | \ | |
300 | PMD_SECT_AP_READ | |
8799ee9f RK |
301 | .long PMD_TYPE_SECT | \ |
302 | PMD_SECT_AP_WRITE | \ | |
303 | PMD_SECT_AP_READ | |
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304 | b __sa1100_setup |
305 | .long cpu_arch_name | |
306 | .long cpu_elf_name | |
307 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT | |
308 | .long cpu_sa1110_name | |
309 | .long sa1100_processor_functions | |
310 | .long v4wb_tlb_fns | |
311 | .long v4_mc_user_fns | |
312 | .long v4wb_cache_fns | |
313 | .size __sa1110_proc_info, . - __sa1110_proc_info |