[linux-2.6-block.git] / arch / arm / mm / proc-fa526.S

/*
 *  linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
 *
 *  Written by : Luke Lee
 *  Copyright (C) 2005 Faraday Corp.
 *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the fa526.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>

#include "proc-macros.S"

#define CACHE_DLINESIZE	16

	.text
/*
 * cpu_fa526_proc_init()
 */
ENTRY(cpu_fa526_proc_init)
	ret	lr

/*
 * cpu_fa526_proc_fin()
 */
ENTRY(cpu_fa526_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	nop
	nop
	ret	lr

/*
 * cpu_fa526_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	4
	.pushsection	.idmap.text, "ax"
ENTRY(cpu_fa526_reset)
/* TODO: Use CP8 if possible... */
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	bic	ip, ip, #0x0800			@ BTB off
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	nop
	nop
	ret	r0
ENDPROC(cpu_fa526_reset)
	.popsection

/*
 * cpu_fa526_do_idle()
 */
	.align	4
ENTRY(cpu_fa526_do_idle)
	ret	lr


ENTRY(cpu_fa526_dcache_clean_area)
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/* =============================== PageTable ============================== */

/*
 * cpu_fa526_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	4
ENTRY(cpu_fa526_switch_mm)
#ifdef CONFIG_MMU
	mov	ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
	mcr	p15, 0, ip, c7, c14, 0		@ clean and invalidate whole D cache
#endif
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c5, 6		@ invalidate BTB since mm changed
	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate UTLB
#endif
	ret	lr

/*
 * cpu_fa526_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
	.align	4
ENTRY(cpu_fa526_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mov	r0, #0
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif
	ret	lr

	.type	__fa526_setup, #function
__fa526_setup:
	/* On return of this routine, r0 must carry correct flags for CFG register */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif
	mcr	p15, 0, r0, c7, c5, 5		@ invalidate IScratchpad RAM

	mov	r0, #1
	mcr	p15, 0, r0, c1, c1, 0		@ turn-on ECR

	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 6		@ invalidate BTB All
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush

	mov	r0, #0x1f			@ Domains 0, 1 = manager, 2 = client
	mcr	p15, 0, r0, c3, c0		@ load domain access register

	mrc	p15, 0, r0, c1, c0		@ get control register v4
	ldr	r5, fa526_cr1_clear
	bic	r0, r0, r5
	ldr	r5, fa526_cr1_set
	orr	r0, r0, r5
	ret	lr
	.size	__fa526_setup, . - __fa526_setup

	/*
	 * .RVI ZFRS BLDP WCAM
	 * ..11 1001 .111 1101
	 *
	 */
	.type	fa526_cr1_clear, #object
	.type	fa526_cr1_set, #object
fa526_cr1_clear:
	.word	0x3f3f
fa526_cr1_set:
	.word	0x397D

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions fa526, dabort=v4_early_abort, pabort=legacy_pabort

	.section ".rodata"

	string	cpu_arch_name, "armv4"
	string	cpu_elf_name, "v4"
	string	cpu_fa526_name, "FA526"

	.align

	.section ".proc.info.init", #alloc

	.type	__fa526_proc_info,#object
__fa526_proc_info:
	.long	0x66015261
	.long	0xff01fff1
	.long   PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	initfn	__fa526_setup, __fa526_proc_info
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF
	.long	cpu_fa526_name
	.long	fa526_processor_functions
	.long	fa_tlb_fns
	.long	fa_user_fns
	.long	fa_cache_fns
	.size	__fa526_proc_info, . - __fa526_proc_info
Commit	Line	Data
28853ac8 PZ	1	/*
	2	* linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
	3	*
	4	* Written by : Luke Lee
	5	* Copyright (C) 2005 Faraday Corp.
	6	* Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	*
	14	* These are the low level assembler for performing cache and TLB
	15	* functions on the fa526.
	16	*/
	17	#include <linux/linkage.h>
	18	#include <linux/init.h>
	19	#include <asm/assembler.h>
	20	#include <asm/hwcap.h>
	21	#include <asm/pgtable-hwdef.h>
	22	#include <asm/pgtable.h>
	23	#include <asm/page.h>
	24	#include <asm/ptrace.h>
28853ac8 PZ	25
	26	#include "proc-macros.S"
	27
	28	#define CACHE_DLINESIZE 16
	29
	30	.text
	31	/*
	32	* cpu_fa526_proc_init()
	33	*/
	34	ENTRY(cpu_fa526_proc_init)
6ebbf2ce	35	ret lr
28853ac8 PZ	36
	37	/*
	38	* cpu_fa526_proc_fin()
	39	*/
	40	ENTRY(cpu_fa526_proc_fin)
28853ac8 PZ	41	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	42	bic r0, r0, #0x1000 @ ...i............
	43	bic r0, r0, #0x000e @ ............wca.
	44	mcr p15, 0, r0, c1, c0, 0 @ disable caches
	45	nop
	46	nop
6ebbf2ce	47	ret lr
28853ac8 PZ	48
	49	/*
	50	* cpu_fa526_reset(loc)
	51	*
	52	* Perform a soft reset of the system. Put the CPU into the
	53	* same state as it would be if it had been reset, and branch
	54	* to what would be the reset vector.
	55	*
	56	* loc: location to jump to for soft reset
	57	*/
	58	.align 4
1a4baafa	59	.pushsection .idmap.text, "ax"
28853ac8 PZ	60	ENTRY(cpu_fa526_reset)
	61	/* TODO: Use CP8 if possible... */
	62	mov ip, #0
	63	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	64	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	65	#ifdef CONFIG_MMU
	66	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
	67	#endif
	68	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	69	bic ip, ip, #0x000f @ ............wcam
	70	bic ip, ip, #0x1100 @ ...i...s........
	71	bic ip, ip, #0x0800 @ BTB off
	72	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	73	nop
	74	nop
6ebbf2ce	75	ret r0
1a4baafa WD	76	ENDPROC(cpu_fa526_reset)
1a4baafa WD	77	.popsection
28853ac8 PZ	78
	79	/*
	80	* cpu_fa526_do_idle()
	81	*/
	82	.align 4
	83	ENTRY(cpu_fa526_do_idle)
6ebbf2ce	84	ret lr
28853ac8 PZ	85
	86
	87	ENTRY(cpu_fa526_dcache_clean_area)
	88	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	89	add r0, r0, #CACHE_DLINESIZE
	90	subs r1, r1, #CACHE_DLINESIZE
	91	bhi 1b
	92	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	93	ret lr
28853ac8 PZ	94
	95	/* =============================== PageTable ============================== */
	96
	97	/*
	98	* cpu_fa526_switch_mm(pgd)
	99	*
	100	* Set the translation base pointer to be as described by pgd.
	101	*
	102	* pgd: new page tables
	103	*/
	104	.align 4
	105	ENTRY(cpu_fa526_switch_mm)
	106	#ifdef CONFIG_MMU
	107	mov ip, #0
	108	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	109	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	110	#else
	111	mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
	112	#endif
	113	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	114	mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
	115	mcr p15, 0, ip, c7, c10, 4 @ data write barrier
	116	mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
	117	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	118	mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
	119	#endif
6ebbf2ce	120	ret lr
28853ac8 PZ	121
	122	/*
	123	* cpu_fa526_set_pte_ext(ptep, pte, ext)
	124	*
	125	* Set a PTE and flush it out
	126	*/
	127	.align 4
	128	ENTRY(cpu_fa526_set_pte_ext)
	129	#ifdef CONFIG_MMU
	130	armv3_set_pte_ext
	131	mov r0, r0
	132	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	133	mov r0, #0
	134	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	135	#endif
6ebbf2ce	136	ret lr
28853ac8	137
28853ac8 PZ	138	.type __fa526_setup, #function
	139	__fa526_setup:
	140	/* On return of this routine, r0 must carry correct flags for CFG register */
	141	mov r0, #0
	142	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	143	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
	144	#ifdef CONFIG_MMU
	145	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
	146	#endif
	147	mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
	148
	149	mov r0, #1
	150	mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
	151
	152	mov r0, #0
	153	mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
	154	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
	155	mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
	156
	157	mov r0, #0x1f @ Domains 0, 1 = manager, 2 = client
	158	mcr p15, 0, r0, c3, c0 @ load domain access register
	159
	160	mrc p15, 0, r0, c1, c0 @ get control register v4
	161	ldr r5, fa526_cr1_clear
	162	bic r0, r0, r5
	163	ldr r5, fa526_cr1_set
	164	orr r0, r0, r5
6ebbf2ce	165	ret lr
28853ac8 PZ	166	.size __fa526_setup, . - __fa526_setup
	167
	168	/*
	169	* .RVI ZFRS BLDP WCAM
	170	* ..11 1001 .111 1101
	171	*
	172	*/
	173	.type fa526_cr1_clear, #object
	174	.type fa526_cr1_set, #object
	175	fa526_cr1_clear:
	176	.word 0x3f3f
	177	fa526_cr1_set:
	178	.word 0x397D
	179
	180	__INITDATA
	181
d6ed10ce DM	182	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
d6ed10ce DM	183	define_processor_functions fa526, dabort=v4_early_abort, pabort=legacy_pabort
28853ac8 PZ	184
	185	.section ".rodata"
	186
d6ed10ce DM	187	string cpu_arch_name, "armv4"
	188	string cpu_elf_name, "v4"
	189	string cpu_fa526_name, "FA526"
28853ac8 PZ	190
	191	.align
	192
bf35706f	193	.section ".proc.info.init", #alloc
28853ac8 PZ	194
	195	.type __fa526_proc_info,#object
	196	__fa526_proc_info:
	197	.long 0x66015261
	198	.long 0xff01fff1
	199	.long PMD_TYPE_SECT \| \
	200	PMD_SECT_BUFFERABLE \| \
	201	PMD_SECT_CACHEABLE \| \
	202	PMD_BIT4 \| \
	203	PMD_SECT_AP_WRITE \| \
	204	PMD_SECT_AP_READ
	205	.long PMD_TYPE_SECT \| \
	206	PMD_BIT4 \| \
	207	PMD_SECT_AP_WRITE \| \
	208	PMD_SECT_AP_READ
bf35706f	209	initfn __fa526_setup, __fa526_proc_info
28853ac8 PZ	210	.long cpu_arch_name
	211	.long cpu_elf_name
	212	.long HWCAP_SWP \| HWCAP_HALF
	213	.long cpu_fa526_name
	214	.long fa526_processor_functions
	215	.long fa_tlb_fns
	216	.long fa_user_fns
	217	.long fa_cache_fns
	218	.size __fa526_proc_info, . - __fa526_proc_info