[linux-block.git] / arch / arm / mm / proc-arm946.S

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
 *
 *  Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
 *
 *  (Many of cache codes are from proc-arm926.S)
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/cfi_types.h>
#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
 * comprising 256 lines of 32 bytes (8 words).
 */
#define CACHE_DSIZE	(CONFIG_CPU_DCACHE_SIZE) /* typically 8KB. */
#define CACHE_DLINESIZE	32			/* fixed */
#define CACHE_DSEGMENTS	4			/* fixed */
#define CACHE_DENTRIES	(CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE)
#define CACHE_DLIMIT	(CACHE_DSIZE * 4)	/* benchmark needed */

	.text
/*
 * cpu_arm946_proc_init()
 * cpu_arm946_switch_mm()
 *
 * These are not required.
 */
SYM_TYPED_FUNC_START(cpu_arm946_proc_init)
	ret	lr
SYM_FUNC_END(cpu_arm946_proc_init)

SYM_TYPED_FUNC_START(cpu_arm946_switch_mm)
	ret	lr
SYM_FUNC_END(cpu_arm946_switch_mm)

/*
 * cpu_arm946_proc_fin()
 */
SYM_TYPED_FUNC_START(cpu_arm946_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x00001000		@ i-cache
	bic	r0, r0, #0x00000004		@ d-cache
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ret	lr
SYM_FUNC_END(cpu_arm946_proc_fin)

/*
 * cpu_arm946_reset(loc)
 * Params  : r0 = address to jump to
 * Notes   : This sets up everything for a reset
 */
	.pushsection	.idmap.text, "ax"
SYM_TYPED_FUNC_START(cpu_arm946_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c5, 0		@ flush I cache
	mcr	p15, 0, ip, c7, c6, 0		@ flush D cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x00000005		@ .............c.p
	bic	ip, ip, #0x00001000		@ i-cache
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	ret	r0
SYM_FUNC_END(cpu_arm946_reset)
	.popsection

/*
 * cpu_arm946_do_idle()
 */
	.align	5
SYM_TYPED_FUNC_START(cpu_arm946_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	ret	lr
SYM_FUNC_END(cpu_arm946_do_idle)

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
SYM_TYPED_FUNC_START(arm946_flush_icache_all)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	ret	lr
SYM_FUNC_END(arm946_flush_icache_all)

/*
 *	flush_user_cache_all()
 */
SYM_FUNC_ALIAS(arm946_flush_user_cache_all, arm946_flush_kern_cache_all)

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
SYM_TYPED_FUNC_START(arm946_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ flush D cache
#else
	mov	r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean/flush D index
	subs	r3, r3, #1 << 4
	bcs	2b				@ entries n to 0
	subs	r1, r1, #1 << 29
	bcs	1b				@ segments 3 to 0
#endif
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ flush I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm946_flush_kern_cache_all)

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the
 *	specified address range.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 * (same as arm926)
 */
SYM_TYPED_FUNC_START(arm946_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

1:	tst	r2, #VM_EXEC
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#else
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#endif
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm946_flush_user_cache_range)

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
SYM_TYPED_FUNC_START(arm946_coherent_kern_range)
#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
	b	arm946_coherent_user_range
#endif
SYM_FUNC_END(arm946_coherent_kern_range)

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 * (same as arm926)
 */
SYM_TYPED_FUNC_START(arm946_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	r0, #0
	ret	lr
SYM_FUNC_END(arm946_coherent_user_range)

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 * (same as arm926)
 */
SYM_TYPED_FUNC_START(arm946_flush_kern_dcache_area)
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm946_flush_kern_dcache_area)

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 * (same as arm926)
 */
arm946_dma_inv_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	tst	r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
#endif
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as arm926)
 */
arm946_dma_clean_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as arm926)
 */
SYM_TYPED_FUNC_START(arm946_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
#else
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm946_dma_flush_range)

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
SYM_TYPED_FUNC_START(arm946_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm946_dma_clean_range
	bcs	arm946_dma_inv_range
	b	arm946_dma_flush_range
SYM_FUNC_END(arm946_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
SYM_TYPED_FUNC_START(arm946_dma_unmap_area)
	ret	lr
SYM_FUNC_END(arm946_dma_unmap_area)

SYM_TYPED_FUNC_START(cpu_arm946_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(cpu_arm946_dcache_clean_area)

	.type	__arm946_setup, #function
__arm946_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c6, 0		@ invalidate D cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB

	mcr	p15, 0, r0, c6, c3, 0		@ disable memory region 3~7
	mcr	p15, 0, r0, c6, c4, 0
	mcr	p15, 0, r0, c6, c5, 0
	mcr	p15, 0, r0, c6, c6, 0
	mcr	p15, 0, r0, c6, c7, 0

	mov	r0, #0x0000003F			@ base = 0, size = 4GB
	mcr	p15, 0, r0, c6,	c0, 0		@ set region 0, default

	ldr	r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
	ldr	r7, =CONFIG_DRAM_SIZE		@ size of RAM (must be >= 4KB)
	pr_val	r3, r0, r7, #1
	mcr	p15, 0, r3, c6, c1, 0

	ldr	r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
	ldr	r7, =CONFIG_FLASH_SIZE		@ size of FLASH (must be >= 4KB)
	pr_val	r3, r0, r7, #1
	mcr	p15, 0, r3, c6, c2, 0

	mov	r0, #0x06
	mcr	p15, 0, r0, c2, c0, 0		@ region 1,2 d-cacheable
	mcr	p15, 0, r0, c2, c0, 1		@ region 1,2 i-cacheable
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r0, #0x00			@ disable whole write buffer
#else
	mov	r0, #0x02			@ region 1 write bufferred
#endif
	mcr	p15, 0, r0, c3, c0, 0

/*
 *  Access Permission Settings for future permission control by PU.
 *
 *				priv.	user
 * 	region 0 (whole)	rw	--	: b0001
 * 	region 1 (RAM)		rw	rw	: b0011
 * 	region 2 (FLASH)	rw	r-	: b0010
 *	region 3~7 (none)	--	--	: b0000
 */
	mov	r0, #0x00000031
	orr	r0, r0, #0x00000200
	mcr	p15, 0, r0, c5, c0, 2		@ set data access permission
	mcr	p15, 0, r0, c5, c0, 3		@ set inst. access permission

	mrc	p15, 0, r0, c1, c0		@ get control register
	orr	r0, r0, #0x00001000		@ I-cache
	orr	r0, r0, #0x00000005		@ MPU/D-cache
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x00004000		@ .1.. .... .... ....
#endif
	ret	lr

	.size	__arm946_setup, . - __arm946_setup

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions arm946, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1

	.section ".rodata"

	string	cpu_arch_name, "armv5te"
	string	cpu_elf_name, "v5t"
	string	cpu_arm946_name, "ARM946E-S"

	.align

	.section ".proc.info.init", "a"
	.type	__arm946_proc_info,#object
__arm946_proc_info:
	.long	0x41009460
	.long	0xff00fff0
	.long	0
	.long	0
	initfn	__arm946_setup, __arm946_proc_info
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
	.long	cpu_arm946_name
	.long	arm946_processor_functions
	.long	0
	.long	0
	.long	arm946_cache_fns
	.size	__arm946_proc_info, . - __arm946_proc_info
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
f37f46eb HC	2	/*
	3	* linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
	4	*
	5	* Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
	6	*
	7	* (Many of cache codes are from proc-arm926.S)
f37f46eb HC	8	*/
	9	#include <linux/linkage.h>
	10	#include <linux/init.h>
1036b895	11	#include <linux/cfi_types.h>
65fddcfc	12	#include <linux/pgtable.h>
f37f46eb	13	#include <asm/assembler.h>
5ec9407d	14	#include <asm/hwcap.h>
f37f46eb	15	#include <asm/pgtable-hwdef.h>
f37f46eb	16	#include <asm/ptrace.h>
8a5544c8	17	#include "proc-macros.S"
f37f46eb HC	18
	19	/*
	20	* ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
	21	* comprising 256 lines of 32 bytes (8 words).
	22	*/
	23	#define CACHE_DSIZE (CONFIG_CPU_DCACHE_SIZE) /* typically 8KB. */
	24	#define CACHE_DLINESIZE 32 /* fixed */
	25	#define CACHE_DSEGMENTS 4 /* fixed */
	26	#define CACHE_DENTRIES (CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE)
	27	#define CACHE_DLIMIT (CACHE_DSIZE * 4) /* benchmark needed */
	28
	29	.text
	30	/*
	31	* cpu_arm946_proc_init()
	32	* cpu_arm946_switch_mm()
	33	*
	34	* These are not required.
	35	*/
51db13aa	36	SYM_TYPED_FUNC_START(cpu_arm946_proc_init)
6ebbf2ce	37	ret lr
51db13aa LW	38	SYM_FUNC_END(cpu_arm946_proc_init)
	39
	40	SYM_TYPED_FUNC_START(cpu_arm946_switch_mm)
	41	ret lr
	42	SYM_FUNC_END(cpu_arm946_switch_mm)
f37f46eb HC	43
	44	/*
	45	* cpu_arm946_proc_fin()
	46	*/
51db13aa	47	SYM_TYPED_FUNC_START(cpu_arm946_proc_fin)
f37f46eb HC	48	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	49	bic r0, r0, #0x00001000 @ i-cache
	50	bic r0, r0, #0x00000004 @ d-cache
	51	mcr p15, 0, r0, c1, c0, 0 @ disable caches
6ebbf2ce	52	ret lr
51db13aa	53	SYM_FUNC_END(cpu_arm946_proc_fin)
f37f46eb HC	54
	55	/*
	56	* cpu_arm946_reset(loc)
	57	* Params : r0 = address to jump to
	58	* Notes : This sets up everything for a reset
	59	*/
1a4baafa	60	.pushsection .idmap.text, "ax"
51db13aa	61	SYM_TYPED_FUNC_START(cpu_arm946_reset)
f37f46eb HC	62	mov ip, #0
	63	mcr p15, 0, ip, c7, c5, 0 @ flush I cache
	64	mcr p15, 0, ip, c7, c6, 0 @ flush D cache
	65	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	66	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	67	bic ip, ip, #0x00000005 @ .............c.p
	68	bic ip, ip, #0x00001000 @ i-cache
	69	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
6ebbf2ce	70	ret r0
51db13aa	71	SYM_FUNC_END(cpu_arm946_reset)
1a4baafa	72	.popsection
f37f46eb HC	73
	74	/*
	75	* cpu_arm946_do_idle()
	76	*/
	77	.align 5
51db13aa	78	SYM_TYPED_FUNC_START(cpu_arm946_do_idle)
f37f46eb	79	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
6ebbf2ce	80	ret lr
51db13aa	81	SYM_FUNC_END(cpu_arm946_do_idle)
f37f46eb	82
c8c90860 MW	83	/*
	84	* flush_icache_all()
	85	*
	86	* Unconditionally clean and invalidate the entire icache.
	87	*/
1036b895	88	SYM_TYPED_FUNC_START(arm946_flush_icache_all)
c8c90860 MW	89	mov r0, #0
c8c90860 MW	90	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
6ebbf2ce	91	ret lr
1036b895	92	SYM_FUNC_END(arm946_flush_icache_all)
c8c90860	93
f37f46eb HC	94	/*
	95	* flush_user_cache_all()
	96	*/
2074beeb	97	SYM_FUNC_ALIAS(arm946_flush_user_cache_all, arm946_flush_kern_cache_all)
f37f46eb HC	98
	99	/*
	100	* flush_kern_cache_all()
	101	*
	102	* Clean and invalidate the entire cache.
	103	*/
1036b895	104	SYM_TYPED_FUNC_START(arm946_flush_kern_cache_all)
f37f46eb HC	105	mov r2, #VM_EXEC
	106	mov ip, #0
	107	__flush_whole_cache:
	108	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	109	mcr p15, 0, ip, c7, c6, 0 @ flush D cache
	110	#else
	111	mov r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
	112	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
	113	2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
	114	subs r3, r3, #1 << 4
	115	bcs 2b @ entries n to 0
	116	subs r1, r1, #1 << 29
	117	bcs 1b @ segments 3 to 0
	118	#endif
	119	tst r2, #VM_EXEC
	120	mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
	121	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	122	ret lr
1036b895	123	SYM_FUNC_END(arm946_flush_kern_cache_all)
f37f46eb HC	124
	125	/*
	126	* flush_user_cache_range(start, end, flags)
	127	*
	128	* Clean and invalidate a range of cache entries in the
	129	* specified address range.
	130	*
	131	* - start - start address (inclusive)
	132	* - end - end address (exclusive)
	133	* - flags - vm_flags describing address space
	134	* (same as arm926)
	135	*/
1036b895	136	SYM_TYPED_FUNC_START(arm946_flush_user_cache_range)
f37f46eb HC	137	mov ip, #0
	138	sub r3, r1, r0 @ calculate total size
	139	cmp r3, #CACHE_DLIMIT
	140	bhs __flush_whole_cache
	141
	142	1: tst r2, #VM_EXEC
	143	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	144	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	145	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	146	add r0, r0, #CACHE_DLINESIZE
	147	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	148	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	149	add r0, r0, #CACHE_DLINESIZE
	150	#else
	151	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	152	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	153	add r0, r0, #CACHE_DLINESIZE
	154	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	155	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	156	add r0, r0, #CACHE_DLINESIZE
	157	#endif
	158	cmp r0, r1
	159	blo 1b
	160	tst r2, #VM_EXEC
	161	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	162	ret lr
1036b895	163	SYM_FUNC_END(arm946_flush_user_cache_range)
f37f46eb HC	164
	165	/*
	166	* coherent_kern_range(start, end)
	167	*
	168	* Ensure coherency between the Icache and the Dcache in the
	169	* region described by start, end. If you have non-snooping
	170	* Harvard caches, you need to implement this function.
	171	*
	172	* - start - virtual start address
	173	* - end - virtual end address
	174	*/
1036b895	175	SYM_TYPED_FUNC_START(arm946_coherent_kern_range)
7b749aad	176	#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
1036b895	177	b arm946_coherent_user_range
7b749aad	178	#endif
1036b895	179	SYM_FUNC_END(arm946_coherent_kern_range)
f37f46eb HC	180
	181	/*
	182	* coherent_user_range(start, end)
	183	*
	184	* Ensure coherency between the Icache and the Dcache in the
	185	* region described by start, end. If you have non-snooping
	186	* Harvard caches, you need to implement this function.
	187	*
	188	* - start - virtual start address
	189	* - end - virtual end address
	190	* (same as arm926)
	191	*/
1036b895	192	SYM_TYPED_FUNC_START(arm946_coherent_user_range)
f37f46eb HC	193	bic r0, r0, #CACHE_DLINESIZE - 1
	194	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	195	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
	196	add r0, r0, #CACHE_DLINESIZE
	197	cmp r0, r1
	198	blo 1b
	199	mcr p15, 0, r0, c7, c10, 4 @ drain WB
c5102f59	200	mov r0, #0
6ebbf2ce	201	ret lr
1036b895	202	SYM_FUNC_END(arm946_coherent_user_range)
f37f46eb HC	203
f37f46eb HC	204	/*
2c9b9c84	205	* flush_kern_dcache_area(void *addr, size_t size)
f37f46eb HC	206	*
	207	* Ensure no D cache aliasing occurs, either with itself or
	208	* the I cache
	209	*
2c9b9c84 RK	210	* - addr - kernel address
2c9b9c84 RK	211	* - size - region size
f37f46eb HC	212	* (same as arm926)
f37f46eb HC	213	*/
1036b895	214	SYM_TYPED_FUNC_START(arm946_flush_kern_dcache_area)
2c9b9c84	215	add r1, r0, r1
f37f46eb HC	216	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	217	add r0, r0, #CACHE_DLINESIZE
	218	cmp r0, r1
	219	blo 1b
	220	mov r0, #0
	221	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	222	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	223	ret lr
1036b895	224	SYM_FUNC_END(arm946_flush_kern_dcache_area)
f37f46eb HC	225
	226	/*
	227	* dma_inv_range(start, end)
	228	*
	229	* Invalidate (discard) the specified virtual address range.
	230	* May not write back any entries. If 'start' or 'end'
	231	* are not cache line aligned, those lines must be written
	232	* back.
	233	*
	234	* - start - virtual start address
	235	* - end - virtual end address
	236	* (same as arm926)
	237	*/
702b94bf	238	arm946_dma_inv_range:
f37f46eb HC	239	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	240	tst r0, #CACHE_DLINESIZE - 1
	241	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	242	tst r1, #CACHE_DLINESIZE - 1
	243	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	244	#endif
	245	bic r0, r0, #CACHE_DLINESIZE - 1
	246	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	247	add r0, r0, #CACHE_DLINESIZE
	248	cmp r0, r1
	249	blo 1b
	250	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	251	ret lr
f37f46eb HC	252
	253	/*
	254	* dma_clean_range(start, end)
	255	*
	256	* Clean the specified virtual address range.
	257	*
	258	* - start - virtual start address
	259	* - end - virtual end address
	260	*
	261	* (same as arm926)
	262	*/
702b94bf	263	arm946_dma_clean_range:
f37f46eb HC	264	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	265	bic r0, r0, #CACHE_DLINESIZE - 1
	266	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	267	add r0, r0, #CACHE_DLINESIZE
	268	cmp r0, r1
	269	blo 1b
	270	#endif
	271	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	272	ret lr
f37f46eb HC	273
	274	/*
	275	* dma_flush_range(start, end)
	276	*
	277	* Clean and invalidate the specified virtual address range.
	278	*
	279	* - start - virtual start address
	280	* - end - virtual end address
	281	*
	282	* (same as arm926)
	283	*/
1036b895	284	SYM_TYPED_FUNC_START(arm946_dma_flush_range)
f37f46eb HC	285	bic r0, r0, #CACHE_DLINESIZE - 1
	286	1:
	287	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	288	mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	289	#else
b3a8b751	290	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
f37f46eb HC	291	#endif
	292	add r0, r0, #CACHE_DLINESIZE
	293	cmp r0, r1
	294	blo 1b
	295	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	296	ret lr
1036b895	297	SYM_FUNC_END(arm946_dma_flush_range)
f37f46eb	298
a9c9147e RK	299	/*
	300	* dma_map_area(start, size, dir)
	301	* - start - kernel virtual start address
	302	* - size - size of region
	303	* - dir - DMA direction
	304	*/
1036b895	305	SYM_TYPED_FUNC_START(arm946_dma_map_area)
a9c9147e RK	306	add r1, r1, r0
	307	cmp r2, #DMA_TO_DEVICE
	308	beq arm946_dma_clean_range
	309	bcs arm946_dma_inv_range
	310	b arm946_dma_flush_range
1036b895	311	SYM_FUNC_END(arm946_dma_map_area)
a9c9147e RK	312
	313	/*
	314	* dma_unmap_area(start, size, dir)
	315	* - start - kernel virtual start address
	316	* - size - size of region
	317	* - dir - DMA direction
	318	*/
1036b895	319	SYM_TYPED_FUNC_START(arm946_dma_unmap_area)
6ebbf2ce	320	ret lr
1036b895	321	SYM_FUNC_END(arm946_dma_unmap_area)
a9c9147e	322
51db13aa	323	SYM_TYPED_FUNC_START(cpu_arm946_dcache_clean_area)
f37f46eb HC	324	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	325	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	326	add r0, r0, #CACHE_DLINESIZE
	327	subs r1, r1, #CACHE_DLINESIZE
	328	bhi 1b
	329	#endif
	330	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	331	ret lr
51db13aa	332	SYM_FUNC_END(cpu_arm946_dcache_clean_area)
f37f46eb	333
f37f46eb HC	334	.type __arm946_setup, #function
	335	__arm946_setup:
	336	mov r0, #0
	337	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	338	mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
	339	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	340
	341	mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
	342	mcr p15, 0, r0, c6, c4, 0
	343	mcr p15, 0, r0, c6, c5, 0
	344	mcr p15, 0, r0, c6, c6, 0
	345	mcr p15, 0, r0, c6, c7, 0
	346
	347	mov r0, #0x0000003F @ base = 0, size = 4GB
	348	mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
	349
	350	ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
6c5c2a01 RK	351	ldr r7, =CONFIG_DRAM_SIZE @ size of RAM (must be >= 4KB)
	352	pr_val r3, r0, r7, #1
	353	mcr p15, 0, r3, c6, c1, 0
f37f46eb HC	354
f37f46eb HC	355	ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
6c5c2a01 RK	356	ldr r7, =CONFIG_FLASH_SIZE @ size of FLASH (must be >= 4KB)
	357	pr_val r3, r0, r7, #1
	358	mcr p15, 0, r3, c6, c2, 0
f37f46eb HC	359
	360	mov r0, #0x06
	361	mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
	362	mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
	363	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	364	mov r0, #0x00 @ disable whole write buffer
	365	#else
	366	mov r0, #0x02 @ region 1 write bufferred
	367	#endif
	368	mcr p15, 0, r0, c3, c0, 0
	369
	370	/*
	371	* Access Permission Settings for future permission control by PU.
	372	*
	373	* priv. user
	374	* region 0 (whole) rw -- : b0001
	375	* region 1 (RAM) rw rw : b0011
	376	* region 2 (FLASH) rw r- : b0010
	377	* region 3~7 (none) -- -- : b0000
	378	*/
	379	mov r0, #0x00000031
	380	orr r0, r0, #0x00000200
	381	mcr p15, 0, r0, c5, c0, 2 @ set data access permission
	382	mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
	383
	384	mrc p15, 0, r0, c1, c0 @ get control register
	385	orr r0, r0, #0x00001000 @ I-cache
	386	orr r0, r0, #0x00000005 @ MPU/D-cache
	387	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	388	orr r0, r0, #0x00004000 @ .1.. .... .... ....
	389	#endif
6ebbf2ce	390	ret lr
f37f46eb HC	391
	392	.size __arm946_setup, . - __arm946_setup
	393
	394	__INITDATA
	395
b1b9892b DM	396	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
b1b9892b DM	397	define_processor_functions arm946, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
f37f46eb HC	398
	399	.section ".rodata"
	400
b1b9892b DM	401	string cpu_arch_name, "armv5te"
	402	string cpu_elf_name, "v5t"
	403	string cpu_arm946_name, "ARM946E-S"
f37f46eb HC	404
	405	.align
	406
790756c7	407	.section ".proc.info.init", "a"
f37f46eb HC	408	.type __arm946_proc_info,#object
	409	__arm946_proc_info:
	410	.long 0x41009460
	411	.long 0xff00fff0
	412	.long 0
7760d546	413	.long 0
bf35706f	414	initfn __arm946_setup, __arm946_proc_info
f37f46eb HC	415	.long cpu_arch_name
	416	.long cpu_elf_name
	417	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB
	418	.long cpu_arm946_name
	419	.long arm946_processor_functions
	420	.long 0
	421	.long 0
7760d546	422	.long arm946_cache_fns
f37f46eb HC	423	.size __arm946_proc_info, . - __arm946_proc_info
f37f46eb HC	424