[linux-2.6-block.git] / arch / arm / mm / proc-arm946.S

/*
 *  linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
 *
 *  Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
 *
 *  (Many of cache codes are from proc-arm926.S)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
 * comprising 256 lines of 32 bytes (8 words).
 */
#define CACHE_DSIZE	(CONFIG_CPU_DCACHE_SIZE) /* typically 8KB. */
#define CACHE_DLINESIZE	32			/* fixed */
#define CACHE_DSEGMENTS	4			/* fixed */
#define CACHE_DENTRIES	(CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE)
#define CACHE_DLIMIT	(CACHE_DSIZE * 4)	/* benchmark needed */

	.text
/*
 * cpu_arm946_proc_init()
 * cpu_arm946_switch_mm()
 *
 * These are not required.
 */
ENTRY(cpu_arm946_proc_init)
ENTRY(cpu_arm946_switch_mm)
	ret	lr

/*
 * cpu_arm946_proc_fin()
 */
ENTRY(cpu_arm946_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x00001000		@ i-cache
	bic	r0, r0, #0x00000004		@ d-cache
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ret	lr

/*
 * cpu_arm946_reset(loc)
 * Params  : r0 = address to jump to
 * Notes   : This sets up everything for a reset
 */
	.pushsection	.idmap.text, "ax"
ENTRY(cpu_arm946_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c5, 0		@ flush I cache
	mcr	p15, 0, ip, c7, c6, 0		@ flush D cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x00000005		@ .............c.p
	bic	ip, ip, #0x00001000		@ i-cache
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	ret	r0
ENDPROC(cpu_arm946_reset)
	.popsection

/*
 * cpu_arm946_do_idle()
 */
	.align	5
ENTRY(cpu_arm946_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	ret	lr

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
ENTRY(arm946_flush_icache_all)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	ret	lr
ENDPROC(arm946_flush_icache_all)

/*
 *	flush_user_cache_all()
 */
ENTRY(arm946_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm946_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ flush D cache
#else
	mov	r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean/flush D index
	subs	r3, r3, #1 << 4
	bcs	2b				@ entries n to 0
	subs	r1, r1, #1 << 29
	bcs	1b				@ segments 3 to 0
#endif
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ flush I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the
 *	specified address range.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 * (same as arm926)
 */
ENTRY(arm946_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

1:	tst	r2, #VM_EXEC
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#else
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#endif
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm946_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 * (same as arm926)
 */
ENTRY(arm946_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	r0, #0
	ret	lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 * (same as arm926)
 */
ENTRY(arm946_flush_kern_dcache_area)
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 * (same as arm926)
 */
arm946_dma_inv_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	tst	r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
#endif
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as arm926)
 */
arm946_dma_clean_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as arm926)
 */
ENTRY(arm946_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
#else
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm946_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm946_dma_clean_range
	bcs	arm946_dma_inv_range
	b	arm946_dma_flush_range
ENDPROC(arm946_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm946_dma_unmap_area)
	ret	lr
ENDPROC(arm946_dma_unmap_area)

	.globl	arm946_flush_kern_cache_louis
	.equ	arm946_flush_kern_cache_louis, arm946_flush_kern_cache_all

	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
	define_cache_functions arm946

ENTRY(cpu_arm946_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

	.type	__arm946_setup, #function
__arm946_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c6, 0		@ invalidate D cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB

	mcr	p15, 0, r0, c6, c3, 0		@ disable memory region 3~7
	mcr	p15, 0, r0, c6, c4, 0
	mcr	p15, 0, r0, c6, c5, 0
	mcr	p15, 0, r0, c6, c6, 0
	mcr	p15, 0, r0, c6, c7, 0

	mov	r0, #0x0000003F			@ base = 0, size = 4GB
	mcr	p15, 0, r0, c6,	c0, 0		@ set region 0, default

	ldr	r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
	ldr	r1, =(CONFIG_DRAM_SIZE >> 12)	@ size of RAM (must be >= 4KB)
	mov	r2, #10				@ 11 is the minimum (4KB)
1:	add	r2, r2, #1			@ area size *= 2
	mov	r1, r1, lsr #1
	bne	1b				@ count not zero r-shift
	orr	r0, r0, r2, lsl #1		@ the region register value
	orr	r0, r0, #1			@ set enable bit
	mcr	p15, 0, r0, c6,	c1, 0		@ set region 1, RAM

	ldr	r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
	ldr	r1, =(CONFIG_FLASH_SIZE >> 12)	@ size of FLASH (must be >= 4KB)
	mov	r2, #10				@ 11 is the minimum (4KB)
1:	add	r2, r2, #1			@ area size *= 2
	mov	r1, r1, lsr #1
	bne	1b				@ count not zero r-shift
	orr	r0, r0, r2, lsl #1		@ the region register value
	orr	r0, r0, #1			@ set enable bit
	mcr	p15, 0, r0, c6,	c2, 0		@ set region 2, ROM/FLASH

	mov	r0, #0x06
	mcr	p15, 0, r0, c2, c0, 0		@ region 1,2 d-cacheable
	mcr	p15, 0, r0, c2, c0, 1		@ region 1,2 i-cacheable
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r0, #0x00			@ disable whole write buffer
#else
	mov	r0, #0x02			@ region 1 write bufferred
#endif
	mcr	p15, 0, r0, c3, c0, 0

/*
 *  Access Permission Settings for future permission control by PU.
 *
 *				priv.	user
 * 	region 0 (whole)	rw	--	: b0001
 * 	region 1 (RAM)		rw	rw	: b0011
 * 	region 2 (FLASH)	rw	r-	: b0010
 *	region 3~7 (none)	--	--	: b0000
 */
	mov	r0, #0x00000031
	orr	r0, r0, #0x00000200
	mcr	p15, 0, r0, c5, c0, 2		@ set data access permission
	mcr	p15, 0, r0, c5, c0, 3		@ set inst. access permission

	mrc	p15, 0, r0, c1, c0		@ get control register
	orr	r0, r0, #0x00001000		@ I-cache
	orr	r0, r0, #0x00000005		@ MPU/D-cache
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x00004000		@ .1.. .... .... ....
#endif
	ret	lr

	.size	__arm946_setup, . - __arm946_setup

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions arm946, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1

	.section ".rodata"

	string	cpu_arch_name, "armv5te"
	string	cpu_elf_name, "v5t"
	string	cpu_arm946_name, "ARM946E-S"

	.align

	.section ".proc.info.init", #alloc, #execinstr
	.type	__arm946_proc_info,#object
__arm946_proc_info:
	.long	0x41009460
	.long	0xff00fff0
	.long	0
	.long	0
	b	__arm946_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
	.long	cpu_arm946_name
	.long	arm946_processor_functions
	.long	0
	.long	0
	.long	arm946_cache_fns
	.size	__arm946_proc_info, . - __arm946_proc_info
Commit	Line	Data
f37f46eb HC	1	/*
	2	* linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
	3	*
	4	* Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
	5	*
	6	* (Many of cache codes are from proc-arm926.S)
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	*/
	13	#include <linux/linkage.h>
	14	#include <linux/init.h>
	15	#include <asm/assembler.h>
5ec9407d	16	#include <asm/hwcap.h>
f37f46eb HC	17	#include <asm/pgtable-hwdef.h>
f37f46eb HC	18	#include <asm/pgtable.h>
f37f46eb	19	#include <asm/ptrace.h>
8a5544c8	20	#include "proc-macros.S"
f37f46eb HC	21
	22	/*
	23	* ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
	24	* comprising 256 lines of 32 bytes (8 words).
	25	*/
	26	#define CACHE_DSIZE (CONFIG_CPU_DCACHE_SIZE) /* typically 8KB. */
	27	#define CACHE_DLINESIZE 32 /* fixed */
	28	#define CACHE_DSEGMENTS 4 /* fixed */
	29	#define CACHE_DENTRIES (CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE)
	30	#define CACHE_DLIMIT (CACHE_DSIZE * 4) /* benchmark needed */
	31
	32	.text
	33	/*
	34	* cpu_arm946_proc_init()
	35	* cpu_arm946_switch_mm()
	36	*
	37	* These are not required.
	38	*/
	39	ENTRY(cpu_arm946_proc_init)
	40	ENTRY(cpu_arm946_switch_mm)
6ebbf2ce	41	ret lr
f37f46eb HC	42
	43	/*
	44	* cpu_arm946_proc_fin()
	45	*/
	46	ENTRY(cpu_arm946_proc_fin)
f37f46eb HC	47	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	48	bic r0, r0, #0x00001000 @ i-cache
	49	bic r0, r0, #0x00000004 @ d-cache
	50	mcr p15, 0, r0, c1, c0, 0 @ disable caches
6ebbf2ce	51	ret lr
f37f46eb HC	52
	53	/*
	54	* cpu_arm946_reset(loc)
	55	* Params : r0 = address to jump to
	56	* Notes : This sets up everything for a reset
	57	*/
1a4baafa	58	.pushsection .idmap.text, "ax"
f37f46eb HC	59	ENTRY(cpu_arm946_reset)
	60	mov ip, #0
	61	mcr p15, 0, ip, c7, c5, 0 @ flush I cache
	62	mcr p15, 0, ip, c7, c6, 0 @ flush D cache
	63	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	64	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	65	bic ip, ip, #0x00000005 @ .............c.p
	66	bic ip, ip, #0x00001000 @ i-cache
	67	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
6ebbf2ce	68	ret r0
1a4baafa WD	69	ENDPROC(cpu_arm946_reset)
1a4baafa WD	70	.popsection
f37f46eb HC	71
	72	/*
	73	* cpu_arm946_do_idle()
	74	*/
	75	.align 5
	76	ENTRY(cpu_arm946_do_idle)
	77	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
6ebbf2ce	78	ret lr
f37f46eb	79
c8c90860 MW	80	/*
	81	* flush_icache_all()
	82	*
	83	* Unconditionally clean and invalidate the entire icache.
	84	*/
	85	ENTRY(arm946_flush_icache_all)
	86	mov r0, #0
	87	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
6ebbf2ce	88	ret lr
c8c90860 MW	89	ENDPROC(arm946_flush_icache_all)
c8c90860 MW	90
f37f46eb HC	91	/*
	92	* flush_user_cache_all()
	93	*/
	94	ENTRY(arm946_flush_user_cache_all)
	95	/* FALLTHROUGH */
	96
	97	/*
	98	* flush_kern_cache_all()
	99	*
	100	* Clean and invalidate the entire cache.
	101	*/
	102	ENTRY(arm946_flush_kern_cache_all)
	103	mov r2, #VM_EXEC
	104	mov ip, #0
	105	__flush_whole_cache:
	106	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	107	mcr p15, 0, ip, c7, c6, 0 @ flush D cache
	108	#else
	109	mov r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
	110	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
	111	2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
	112	subs r3, r3, #1 << 4
	113	bcs 2b @ entries n to 0
	114	subs r1, r1, #1 << 29
	115	bcs 1b @ segments 3 to 0
	116	#endif
	117	tst r2, #VM_EXEC
	118	mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
	119	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	120	ret lr
f37f46eb HC	121
	122	/*
	123	* flush_user_cache_range(start, end, flags)
	124	*
	125	* Clean and invalidate a range of cache entries in the
	126	* specified address range.
	127	*
	128	* - start - start address (inclusive)
	129	* - end - end address (exclusive)
	130	* - flags - vm_flags describing address space
	131	* (same as arm926)
	132	*/
	133	ENTRY(arm946_flush_user_cache_range)
	134	mov ip, #0
	135	sub r3, r1, r0 @ calculate total size
	136	cmp r3, #CACHE_DLIMIT
	137	bhs __flush_whole_cache
	138
	139	1: tst r2, #VM_EXEC
	140	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	141	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	142	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	143	add r0, r0, #CACHE_DLINESIZE
	144	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	145	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	146	add r0, r0, #CACHE_DLINESIZE
	147	#else
	148	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	149	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	150	add r0, r0, #CACHE_DLINESIZE
	151	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	152	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	153	add r0, r0, #CACHE_DLINESIZE
	154	#endif
	155	cmp r0, r1
	156	blo 1b
	157	tst r2, #VM_EXEC
	158	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	159	ret lr
f37f46eb HC	160
	161	/*
	162	* coherent_kern_range(start, end)
	163	*
	164	* Ensure coherency between the Icache and the Dcache in the
	165	* region described by start, end. If you have non-snooping
	166	* Harvard caches, you need to implement this function.
	167	*
	168	* - start - virtual start address
	169	* - end - virtual end address
	170	*/
	171	ENTRY(arm946_coherent_kern_range)
	172	/* FALLTHROUGH */
	173
	174	/*
	175	* coherent_user_range(start, end)
	176	*
	177	* Ensure coherency between the Icache and the Dcache in the
	178	* region described by start, end. If you have non-snooping
	179	* Harvard caches, you need to implement this function.
	180	*
	181	* - start - virtual start address
	182	* - end - virtual end address
	183	* (same as arm926)
	184	*/
	185	ENTRY(arm946_coherent_user_range)
	186	bic r0, r0, #CACHE_DLINESIZE - 1
	187	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	188	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
	189	add r0, r0, #CACHE_DLINESIZE
	190	cmp r0, r1
	191	blo 1b
	192	mcr p15, 0, r0, c7, c10, 4 @ drain WB
c5102f59	193	mov r0, #0
6ebbf2ce	194	ret lr
f37f46eb HC	195
f37f46eb HC	196	/*
2c9b9c84	197	* flush_kern_dcache_area(void *addr, size_t size)
f37f46eb HC	198	*
	199	* Ensure no D cache aliasing occurs, either with itself or
	200	* the I cache
	201	*
2c9b9c84 RK	202	* - addr - kernel address
2c9b9c84 RK	203	* - size - region size
f37f46eb HC	204	* (same as arm926)
f37f46eb HC	205	*/
2c9b9c84 RK	206	ENTRY(arm946_flush_kern_dcache_area)
2c9b9c84 RK	207	add r1, r0, r1
f37f46eb HC	208	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	209	add r0, r0, #CACHE_DLINESIZE
	210	cmp r0, r1
	211	blo 1b
	212	mov r0, #0
	213	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	214	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	215	ret lr
f37f46eb HC	216
	217	/*
	218	* dma_inv_range(start, end)
	219	*
	220	* Invalidate (discard) the specified virtual address range.
	221	* May not write back any entries. If 'start' or 'end'
	222	* are not cache line aligned, those lines must be written
	223	* back.
	224	*
	225	* - start - virtual start address
	226	* - end - virtual end address
	227	* (same as arm926)
	228	*/
702b94bf	229	arm946_dma_inv_range:
f37f46eb HC	230	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	231	tst r0, #CACHE_DLINESIZE - 1
	232	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	233	tst r1, #CACHE_DLINESIZE - 1
	234	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	235	#endif
	236	bic r0, r0, #CACHE_DLINESIZE - 1
	237	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	238	add r0, r0, #CACHE_DLINESIZE
	239	cmp r0, r1
	240	blo 1b
	241	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	242	ret lr
f37f46eb HC	243
	244	/*
	245	* dma_clean_range(start, end)
	246	*
	247	* Clean the specified virtual address range.
	248	*
	249	* - start - virtual start address
	250	* - end - virtual end address
	251	*
	252	* (same as arm926)
	253	*/
702b94bf	254	arm946_dma_clean_range:
f37f46eb HC	255	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	256	bic r0, r0, #CACHE_DLINESIZE - 1
	257	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	258	add r0, r0, #CACHE_DLINESIZE
	259	cmp r0, r1
	260	blo 1b
	261	#endif
	262	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	263	ret lr
f37f46eb HC	264
	265	/*
	266	* dma_flush_range(start, end)
	267	*
	268	* Clean and invalidate the specified virtual address range.
	269	*
	270	* - start - virtual start address
	271	* - end - virtual end address
	272	*
	273	* (same as arm926)
	274	*/
	275	ENTRY(arm946_dma_flush_range)
	276	bic r0, r0, #CACHE_DLINESIZE - 1
	277	1:
	278	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	279	mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	280	#else
b3a8b751	281	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
f37f46eb HC	282	#endif
	283	add r0, r0, #CACHE_DLINESIZE
	284	cmp r0, r1
	285	blo 1b
	286	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	287	ret lr
f37f46eb	288
a9c9147e RK	289	/*
	290	* dma_map_area(start, size, dir)
	291	* - start - kernel virtual start address
	292	* - size - size of region
	293	* - dir - DMA direction
	294	*/
	295	ENTRY(arm946_dma_map_area)
	296	add r1, r1, r0
	297	cmp r2, #DMA_TO_DEVICE
	298	beq arm946_dma_clean_range
	299	bcs arm946_dma_inv_range
	300	b arm946_dma_flush_range
	301	ENDPROC(arm946_dma_map_area)
	302
	303	/*
	304	* dma_unmap_area(start, size, dir)
	305	* - start - kernel virtual start address
	306	* - size - size of region
	307	* - dir - DMA direction
	308	*/
	309	ENTRY(arm946_dma_unmap_area)
6ebbf2ce	310	ret lr
a9c9147e RK	311	ENDPROC(arm946_dma_unmap_area)
a9c9147e RK	312
031bd879 LP	313	.globl arm946_flush_kern_cache_louis
	314	.equ arm946_flush_kern_cache_louis, arm946_flush_kern_cache_all
	315
b1b9892b DM	316	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
b1b9892b DM	317	define_cache_functions arm946
f37f46eb HC	318
	319	ENTRY(cpu_arm946_dcache_clean_area)
	320	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	321	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	322	add r0, r0, #CACHE_DLINESIZE
	323	subs r1, r1, #CACHE_DLINESIZE
	324	bhi 1b
	325	#endif
	326	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	327	ret lr
f37f46eb	328
f37f46eb HC	329	.type __arm946_setup, #function
	330	__arm946_setup:
	331	mov r0, #0
	332	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	333	mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
	334	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	335
	336	mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
	337	mcr p15, 0, r0, c6, c4, 0
	338	mcr p15, 0, r0, c6, c5, 0
	339	mcr p15, 0, r0, c6, c6, 0
	340	mcr p15, 0, r0, c6, c7, 0
	341
	342	mov r0, #0x0000003F @ base = 0, size = 4GB
	343	mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
	344
	345	ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
	346	ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
	347	mov r2, #10 @ 11 is the minimum (4KB)
	348	1: add r2, r2, #1 @ area size *= 2
	349	mov r1, r1, lsr #1
	350	bne 1b @ count not zero r-shift
	351	orr r0, r0, r2, lsl #1 @ the region register value
	352	orr r0, r0, #1 @ set enable bit
	353	mcr p15, 0, r0, c6, c1, 0 @ set region 1, RAM
	354
	355	ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
	356	ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
	357	mov r2, #10 @ 11 is the minimum (4KB)
	358	1: add r2, r2, #1 @ area size *= 2
	359	mov r1, r1, lsr #1
	360	bne 1b @ count not zero r-shift
	361	orr r0, r0, r2, lsl #1 @ the region register value
	362	orr r0, r0, #1 @ set enable bit
	363	mcr p15, 0, r0, c6, c2, 0 @ set region 2, ROM/FLASH
	364
	365	mov r0, #0x06
	366	mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
	367	mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
	368	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	369	mov r0, #0x00 @ disable whole write buffer
	370	#else
	371	mov r0, #0x02 @ region 1 write bufferred
	372	#endif
	373	mcr p15, 0, r0, c3, c0, 0
	374
	375	/*
	376	* Access Permission Settings for future permission control by PU.
	377	*
	378	* priv. user
	379	* region 0 (whole) rw -- : b0001
	380	* region 1 (RAM) rw rw : b0011
	381	* region 2 (FLASH) rw r- : b0010
	382	* region 3~7 (none) -- -- : b0000
	383	*/
	384	mov r0, #0x00000031
	385	orr r0, r0, #0x00000200
	386	mcr p15, 0, r0, c5, c0, 2 @ set data access permission
	387	mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
	388
	389	mrc p15, 0, r0, c1, c0 @ get control register
	390	orr r0, r0, #0x00001000 @ I-cache
	391	orr r0, r0, #0x00000005 @ MPU/D-cache
	392	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
393	orr r0, r0, #0x00004000 @ .1.. .... .... ....
394	#endif
6ebbf2ce	395	ret lr
f37f46eb HC	396
	397	.size __arm946_setup, . - __arm946_setup
	398
	399	__INITDATA
	400
b1b9892b DM	401	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
b1b9892b DM	402	define_processor_functions arm946, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
f37f46eb HC	403
	404	.section ".rodata"
	405
b1b9892b DM	406	string cpu_arch_name, "armv5te"
	407	string cpu_elf_name, "v5t"
	408	string cpu_arm946_name, "ARM946E-S"
f37f46eb HC	409
	410	.align
	411
	412	.section ".proc.info.init", #alloc, #execinstr
	413	.type __arm946_proc_info,#object
	414	__arm946_proc_info:
	415	.long 0x41009460
	416	.long 0xff00fff0
	417	.long 0
7760d546	418	.long 0
f37f46eb HC	419	b __arm946_setup
	420	.long cpu_arch_name
	421	.long cpu_elf_name
	422	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB
	423	.long cpu_arm946_name
	424	.long arm946_processor_functions
	425	.long 0
	426	.long 0
7760d546	427	.long arm946_cache_fns
f37f46eb HC	428	.size __arm946_proc_info, . - __arm946_proc_info
f37f46eb HC	429