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1 | /* |
2 | * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S | |
3 | * | |
4 | * Copyright (C) 1999-2001 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | * | |
21 | * | |
22 | * These are the low level assembler for performing cache and TLB | |
23 | * functions on the arm926. | |
24 | * | |
25 | * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt | |
26 | */ | |
27 | #include <linux/linkage.h> | |
28 | #include <linux/config.h> | |
29 | #include <linux/init.h> | |
30 | #include <asm/assembler.h> | |
74945c86 | 31 | #include <asm/pgtable-hwdef.h> |
1da177e4 LT |
32 | #include <asm/pgtable.h> |
33 | #include <asm/procinfo.h> | |
1da177e4 LT |
34 | #include <asm/page.h> |
35 | #include <asm/ptrace.h> | |
36 | #include "proc-macros.S" | |
37 | ||
38 | /* | |
39 | * This is the maximum size of an area which will be invalidated | |
40 | * using the single invalidate entry instructions. Anything larger | |
41 | * than this, and we go for the whole cache. | |
42 | * | |
43 | * This value should be chosen such that we choose the cheapest | |
44 | * alternative. | |
45 | */ | |
46 | #define CACHE_DLIMIT 16384 | |
47 | ||
48 | /* | |
49 | * the cache line size of the I and D cache | |
50 | */ | |
51 | #define CACHE_DLINESIZE 32 | |
52 | ||
53 | .text | |
54 | /* | |
55 | * cpu_arm926_proc_init() | |
56 | */ | |
57 | ENTRY(cpu_arm926_proc_init) | |
58 | mov pc, lr | |
59 | ||
60 | /* | |
61 | * cpu_arm926_proc_fin() | |
62 | */ | |
63 | ENTRY(cpu_arm926_proc_fin) | |
64 | stmfd sp!, {lr} | |
65 | mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE | |
66 | msr cpsr_c, ip | |
67 | bl arm926_flush_kern_cache_all | |
68 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | |
69 | bic r0, r0, #0x1000 @ ...i............ | |
70 | bic r0, r0, #0x000e @ ............wca. | |
71 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
72 | ldmfd sp!, {pc} | |
73 | ||
74 | /* | |
75 | * cpu_arm926_reset(loc) | |
76 | * | |
77 | * Perform a soft reset of the system. Put the CPU into the | |
78 | * same state as it would be if it had been reset, and branch | |
79 | * to what would be the reset vector. | |
80 | * | |
81 | * loc: location to jump to for soft reset | |
82 | */ | |
83 | .align 5 | |
84 | ENTRY(cpu_arm926_reset) | |
85 | mov ip, #0 | |
86 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | |
87 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
88 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | |
89 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register | |
90 | bic ip, ip, #0x000f @ ............wcam | |
91 | bic ip, ip, #0x1100 @ ...i...s........ | |
92 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | |
93 | mov pc, r0 | |
94 | ||
95 | /* | |
96 | * cpu_arm926_do_idle() | |
97 | * | |
98 | * Called with IRQs disabled | |
99 | */ | |
100 | .align 10 | |
101 | ENTRY(cpu_arm926_do_idle) | |
102 | mov r0, #0 | |
103 | mrc p15, 0, r1, c1, c0, 0 @ Read control register | |
104 | mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer | |
105 | bic r2, r1, #1 << 12 | |
106 | mcr p15, 0, r2, c1, c0, 0 @ Disable I cache | |
107 | mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt | |
108 | mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable | |
109 | mov pc, lr | |
110 | ||
111 | /* | |
112 | * flush_user_cache_all() | |
113 | * | |
114 | * Clean and invalidate all cache entries in a particular | |
115 | * address space. | |
116 | */ | |
117 | ENTRY(arm926_flush_user_cache_all) | |
118 | /* FALLTHROUGH */ | |
119 | ||
120 | /* | |
121 | * flush_kern_cache_all() | |
122 | * | |
123 | * Clean and invalidate the entire cache. | |
124 | */ | |
125 | ENTRY(arm926_flush_kern_cache_all) | |
126 | mov r2, #VM_EXEC | |
127 | mov ip, #0 | |
128 | __flush_whole_cache: | |
129 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
130 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
131 | #else | |
132 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate | |
133 | bne 1b | |
134 | #endif | |
135 | tst r2, #VM_EXEC | |
136 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
137 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
138 | mov pc, lr | |
139 | ||
140 | /* | |
141 | * flush_user_cache_range(start, end, flags) | |
142 | * | |
143 | * Clean and invalidate a range of cache entries in the | |
144 | * specified address range. | |
145 | * | |
146 | * - start - start address (inclusive) | |
147 | * - end - end address (exclusive) | |
148 | * - flags - vm_flags describing address space | |
149 | */ | |
150 | ENTRY(arm926_flush_user_cache_range) | |
151 | mov ip, #0 | |
152 | sub r3, r1, r0 @ calculate total size | |
153 | cmp r3, #CACHE_DLIMIT | |
154 | bgt __flush_whole_cache | |
155 | 1: tst r2, #VM_EXEC | |
156 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
157 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | |
158 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
159 | add r0, r0, #CACHE_DLINESIZE | |
160 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | |
161 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
162 | add r0, r0, #CACHE_DLINESIZE | |
163 | #else | |
164 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | |
165 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
166 | add r0, r0, #CACHE_DLINESIZE | |
167 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | |
168 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
169 | add r0, r0, #CACHE_DLINESIZE | |
170 | #endif | |
171 | cmp r0, r1 | |
172 | blo 1b | |
173 | tst r2, #VM_EXEC | |
174 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
175 | mov pc, lr | |
176 | ||
177 | /* | |
178 | * coherent_kern_range(start, end) | |
179 | * | |
180 | * Ensure coherency between the Icache and the Dcache in the | |
181 | * region described by start, end. If you have non-snooping | |
182 | * Harvard caches, you need to implement this function. | |
183 | * | |
184 | * - start - virtual start address | |
185 | * - end - virtual end address | |
186 | */ | |
187 | ENTRY(arm926_coherent_kern_range) | |
188 | /* FALLTHROUGH */ | |
189 | ||
190 | /* | |
191 | * coherent_user_range(start, end) | |
192 | * | |
193 | * Ensure coherency between the Icache and the Dcache in the | |
194 | * region described by start, end. If you have non-snooping | |
195 | * Harvard caches, you need to implement this function. | |
196 | * | |
197 | * - start - virtual start address | |
198 | * - end - virtual end address | |
199 | */ | |
200 | ENTRY(arm926_coherent_user_range) | |
201 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
202 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
203 | mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
204 | add r0, r0, #CACHE_DLINESIZE | |
205 | cmp r0, r1 | |
206 | blo 1b | |
207 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
208 | mov pc, lr | |
209 | ||
210 | /* | |
211 | * flush_kern_dcache_page(void *page) | |
212 | * | |
213 | * Ensure no D cache aliasing occurs, either with itself or | |
214 | * the I cache | |
215 | * | |
216 | * - addr - page aligned address | |
217 | */ | |
218 | ENTRY(arm926_flush_kern_dcache_page) | |
219 | add r1, r0, #PAGE_SZ | |
220 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | |
221 | add r0, r0, #CACHE_DLINESIZE | |
222 | cmp r0, r1 | |
223 | blo 1b | |
224 | mov r0, #0 | |
225 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
226 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
227 | mov pc, lr | |
228 | ||
229 | /* | |
230 | * dma_inv_range(start, end) | |
231 | * | |
232 | * Invalidate (discard) the specified virtual address range. | |
233 | * May not write back any entries. If 'start' or 'end' | |
234 | * are not cache line aligned, those lines must be written | |
235 | * back. | |
236 | * | |
237 | * - start - virtual start address | |
238 | * - end - virtual end address | |
239 | * | |
240 | * (same as v4wb) | |
241 | */ | |
242 | ENTRY(arm926_dma_inv_range) | |
243 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | |
244 | tst r0, #CACHE_DLINESIZE - 1 | |
245 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | |
246 | tst r1, #CACHE_DLINESIZE - 1 | |
247 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry | |
248 | #endif | |
249 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
250 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | |
251 | add r0, r0, #CACHE_DLINESIZE | |
252 | cmp r0, r1 | |
253 | blo 1b | |
254 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
255 | mov pc, lr | |
256 | ||
257 | /* | |
258 | * dma_clean_range(start, end) | |
259 | * | |
260 | * Clean the specified virtual address range. | |
261 | * | |
262 | * - start - virtual start address | |
263 | * - end - virtual end address | |
264 | * | |
265 | * (same as v4wb) | |
266 | */ | |
267 | ENTRY(arm926_dma_clean_range) | |
268 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | |
269 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
270 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
271 | add r0, r0, #CACHE_DLINESIZE | |
272 | cmp r0, r1 | |
273 | blo 1b | |
274 | #endif | |
275 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
276 | mov pc, lr | |
277 | ||
278 | /* | |
279 | * dma_flush_range(start, end) | |
280 | * | |
281 | * Clean and invalidate the specified virtual address range. | |
282 | * | |
283 | * - start - virtual start address | |
284 | * - end - virtual end address | |
285 | */ | |
286 | ENTRY(arm926_dma_flush_range) | |
287 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
288 | 1: | |
289 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | |
290 | mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | |
291 | #else | |
292 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
293 | #endif | |
294 | add r0, r0, #CACHE_DLINESIZE | |
295 | cmp r0, r1 | |
296 | blo 1b | |
297 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
298 | mov pc, lr | |
299 | ||
300 | ENTRY(arm926_cache_fns) | |
301 | .long arm926_flush_kern_cache_all | |
302 | .long arm926_flush_user_cache_all | |
303 | .long arm926_flush_user_cache_range | |
304 | .long arm926_coherent_kern_range | |
305 | .long arm926_coherent_user_range | |
306 | .long arm926_flush_kern_dcache_page | |
307 | .long arm926_dma_inv_range | |
308 | .long arm926_dma_clean_range | |
309 | .long arm926_dma_flush_range | |
310 | ||
311 | ENTRY(cpu_arm926_dcache_clean_area) | |
312 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | |
313 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
314 | add r0, r0, #CACHE_DLINESIZE | |
315 | subs r1, r1, #CACHE_DLINESIZE | |
316 | bhi 1b | |
317 | #endif | |
318 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
319 | mov pc, lr | |
320 | ||
321 | /* =============================== PageTable ============================== */ | |
322 | ||
323 | /* | |
324 | * cpu_arm926_switch_mm(pgd) | |
325 | * | |
326 | * Set the translation base pointer to be as described by pgd. | |
327 | * | |
328 | * pgd: new page tables | |
329 | */ | |
330 | .align 5 | |
331 | ENTRY(cpu_arm926_switch_mm) | |
332 | mov ip, #0 | |
333 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
334 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
335 | #else | |
336 | @ && 'Clean & Invalidate whole DCache' | |
337 | 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate | |
338 | bne 1b | |
339 | #endif | |
340 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
341 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
342 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer | |
343 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | |
344 | mov pc, lr | |
345 | ||
346 | /* | |
347 | * cpu_arm926_set_pte(ptep, pte) | |
348 | * | |
349 | * Set a PTE and flush it out | |
350 | */ | |
351 | .align 5 | |
352 | ENTRY(cpu_arm926_set_pte) | |
353 | str r1, [r0], #-2048 @ linux version | |
354 | ||
355 | eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY | |
356 | ||
357 | bic r2, r1, #PTE_SMALL_AP_MASK | |
358 | bic r2, r2, #PTE_TYPE_MASK | |
359 | orr r2, r2, #PTE_TYPE_SMALL | |
360 | ||
361 | tst r1, #L_PTE_USER @ User? | |
362 | orrne r2, r2, #PTE_SMALL_AP_URO_SRW | |
363 | ||
364 | tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? | |
365 | orreq r2, r2, #PTE_SMALL_AP_UNO_SRW | |
366 | ||
367 | tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? | |
368 | movne r2, #0 | |
369 | ||
370 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
371 | eor r3, r2, #0x0a @ C & small page? | |
372 | tst r3, #0x0b | |
373 | biceq r2, r2, #4 | |
374 | #endif | |
375 | str r2, [r0] @ hardware version | |
376 | mov r0, r0 | |
377 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | |
378 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
379 | #endif | |
380 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
381 | mov pc, lr | |
382 | ||
383 | __INIT | |
384 | ||
385 | .type __arm926_setup, #function | |
386 | __arm926_setup: | |
387 | mov r0, #0 | |
388 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 | |
389 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 | |
390 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 | |
391 | ||
392 | ||
393 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
394 | mov r0, #4 @ disable write-back on caches explicitly | |
395 | mcr p15, 7, r0, c15, c0, 0 | |
396 | #endif | |
397 | ||
398 | mrc p15, 0, r0, c1, c0 @ get control register v4 | |
399 | ldr r5, arm926_cr1_clear | |
400 | bic r0, r0, r5 | |
401 | ldr r5, arm926_cr1_set | |
402 | orr r0, r0, r5 | |
403 | #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN | |
404 | orr r0, r0, #0x4000 @ .1.. .... .... .... | |
405 | #endif | |
406 | mov pc, lr | |
407 | .size __arm926_setup, . - __arm926_setup | |
408 | ||
409 | /* | |
410 | * R | |
411 | * .RVI ZFRS BLDP WCAM | |
412 | * .011 0001 ..11 0101 | |
413 | * | |
414 | */ | |
415 | .type arm926_cr1_clear, #object | |
416 | .type arm926_cr1_set, #object | |
417 | arm926_cr1_clear: | |
418 | .word 0x7f3f | |
419 | arm926_cr1_set: | |
420 | .word 0x3135 | |
421 | ||
422 | __INITDATA | |
423 | ||
424 | /* | |
425 | * Purpose : Function pointers used to access above functions - all calls | |
426 | * come through these | |
427 | */ | |
428 | .type arm926_processor_functions, #object | |
429 | arm926_processor_functions: | |
430 | .word v5tj_early_abort | |
431 | .word cpu_arm926_proc_init | |
432 | .word cpu_arm926_proc_fin | |
433 | .word cpu_arm926_reset | |
434 | .word cpu_arm926_do_idle | |
435 | .word cpu_arm926_dcache_clean_area | |
436 | .word cpu_arm926_switch_mm | |
437 | .word cpu_arm926_set_pte | |
438 | .size arm926_processor_functions, . - arm926_processor_functions | |
439 | ||
440 | .section ".rodata" | |
441 | ||
442 | .type cpu_arch_name, #object | |
443 | cpu_arch_name: | |
444 | .asciz "armv5tej" | |
445 | .size cpu_arch_name, . - cpu_arch_name | |
446 | ||
447 | .type cpu_elf_name, #object | |
448 | cpu_elf_name: | |
449 | .asciz "v5" | |
450 | .size cpu_elf_name, . - cpu_elf_name | |
451 | ||
452 | .type cpu_arm926_name, #object | |
453 | cpu_arm926_name: | |
454 | .ascii "ARM926EJ-S" | |
455 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
456 | .ascii "i" | |
457 | #endif | |
458 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
459 | .ascii "d" | |
460 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
461 | .ascii "(wt)" | |
462 | #else | |
463 | .ascii "(wb)" | |
464 | #endif | |
465 | #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN | |
466 | .ascii "RR" | |
467 | #endif | |
468 | #endif | |
469 | .ascii "\0" | |
470 | .size cpu_arm926_name, . - cpu_arm926_name | |
471 | ||
472 | .align | |
473 | ||
02b7dd12 | 474 | .section ".proc.info.init", #alloc, #execinstr |
1da177e4 LT |
475 | |
476 | .type __arm926_proc_info,#object | |
477 | __arm926_proc_info: | |
478 | .long 0x41069260 @ ARM926EJ-S (v5TEJ) | |
479 | .long 0xff0ffff0 | |
480 | .long PMD_TYPE_SECT | \ | |
481 | PMD_SECT_BUFFERABLE | \ | |
482 | PMD_SECT_CACHEABLE | \ | |
483 | PMD_BIT4 | \ | |
484 | PMD_SECT_AP_WRITE | \ | |
485 | PMD_SECT_AP_READ | |
486 | b __arm926_setup | |
487 | .long cpu_arch_name | |
488 | .long cpu_elf_name | |
489 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA | |
490 | .long cpu_arm926_name | |
491 | .long arm926_processor_functions | |
492 | .long v4wbi_tlb_fns | |
493 | .long v4wb_user_fns | |
494 | .long arm926_cache_fns | |
495 | .size __arm926_proc_info, . - __arm926_proc_info |