[linux-block.git] / arch / arm / mm / proc-arm926.S

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 *  linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
 *
 *  Copyright (C) 1999-2001 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm926.
 *
 *  CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/cfi_types.h>
#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define CACHE_DLIMIT	16384

/*
 * the cache line size of the I and D cache
 */
#define CACHE_DLINESIZE	32

	.text
/*
 * cpu_arm926_proc_init()
 */
SYM_TYPED_FUNC_START(cpu_arm926_proc_init)
	ret	lr
SYM_FUNC_END(cpu_arm926_proc_init)

/*
 * cpu_arm926_proc_fin()
 */
SYM_TYPED_FUNC_START(cpu_arm926_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ret	lr
SYM_FUNC_END(cpu_arm926_proc_fin)

/*
 * cpu_arm926_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
	.pushsection	.idmap.text, "ax"
SYM_TYPED_FUNC_START(cpu_arm926_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	ret	r0
SYM_FUNC_END(cpu_arm926_reset)
	.popsection

/*
 * cpu_arm926_do_idle()
 *
 * Called with IRQs disabled
 */
	.align	10
SYM_TYPED_FUNC_START(cpu_arm926_do_idle)
	mov	r0, #0
	mrc	p15, 0, r1, c1, c0, 0		@ Read control register
	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
	bic	r2, r1, #1 << 12
	mrs	r3, cpsr			@ Disable FIQs while Icache
	orr	ip, r3, #PSR_F_BIT		@ is disabled
	msr	cpsr_c, ip
	mcr	p15, 0, r2, c1, c0, 0		@ Disable I cache
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mcr	p15, 0, r1, c1, c0, 0		@ Restore ICache enable
	msr	cpsr_c, r3			@ Restore FIQ state
	ret	lr
SYM_FUNC_END(cpu_arm926_do_idle)

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
SYM_TYPED_FUNC_START(arm926_flush_icache_all)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	ret	lr
SYM_FUNC_END(arm926_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Clean and invalidate all cache entries in a particular
 *	address space.
 */
SYM_FUNC_ALIAS(arm926_flush_user_cache_all, arm926_flush_kern_cache_all)

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
SYM_TYPED_FUNC_START(arm926_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3 	@ test,clean,invalidate
	bne	1b
#endif
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm926_flush_kern_cache_all)

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the
 *	specified address range.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 */
SYM_TYPED_FUNC_START(arm926_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bgt	__flush_whole_cache
1:	tst	r2, #VM_EXEC
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#else
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#endif
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm926_flush_user_cache_range)

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
SYM_TYPED_FUNC_START(arm926_coherent_kern_range)
#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
	b	arm926_coherent_user_range
#endif
SYM_FUNC_END(arm926_coherent_kern_range)

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
SYM_TYPED_FUNC_START(arm926_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	r0, #0
	ret	lr
SYM_FUNC_END(arm926_coherent_user_range)

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
SYM_TYPED_FUNC_START(arm926_flush_kern_dcache_area)
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm926_flush_kern_dcache_area)

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm926_dma_inv_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	tst	r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
#endif
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm926_dma_clean_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
SYM_TYPED_FUNC_START(arm926_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
#else
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm926_dma_flush_range)

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
SYM_TYPED_FUNC_START(arm926_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm926_dma_clean_range
	bcs	arm926_dma_inv_range
	b	arm926_dma_flush_range
SYM_FUNC_END(arm926_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
SYM_TYPED_FUNC_START(arm926_dma_unmap_area)
	ret	lr
SYM_FUNC_END(arm926_dma_unmap_area)

SYM_TYPED_FUNC_START(cpu_arm926_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(cpu_arm926_dcache_clean_area)

/* =============================== PageTable ============================== */

/*
 * cpu_arm926_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5

SYM_TYPED_FUNC_START(cpu_arm926_switch_mm)
#ifdef CONFIG_MMU
	mov	ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
@ && 'Clean & Invalidate whole DCache'
1:	mrc	p15, 0, APSR_nzcv, c7, c14, 3 	@ test,clean,invalidate
	bne	1b
#endif
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	ret	lr
SYM_FUNC_END(cpu_arm926_switch_mm)

/*
 * cpu_arm926_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
	.align	5
SYM_TYPED_FUNC_START(cpu_arm926_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif
	ret	lr
SYM_FUNC_END(cpu_arm926_set_pte_ext)

/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
.globl	cpu_arm926_suspend_size
.equ	cpu_arm926_suspend_size, 4 * 3
#ifdef CONFIG_ARM_CPU_SUSPEND
SYM_TYPED_FUNC_START(cpu_arm926_do_suspend)
	stmfd	sp!, {r4 - r6, lr}
	mrc	p15, 0, r4, c13, c0, 0	@ PID
	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
	mrc	p15, 0, r6, c1, c0, 0	@ Control register
	stmia	r0, {r4 - r6}
	ldmfd	sp!, {r4 - r6, pc}
SYM_FUNC_END(cpu_arm926_do_suspend)

SYM_TYPED_FUNC_START(cpu_arm926_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I+D TLBs
	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I+D caches
	ldmia	r0, {r4 - r6}
	mcr	p15, 0, r4, c13, c0, 0	@ PID
	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
	mcr	p15, 0, r1, c2, c0, 0	@ TTB address
	mov	r0, r6			@ control register
	b	cpu_resume_mmu
SYM_FUNC_END(cpu_arm926_do_resume)
#endif

	.type	__arm926_setup, #function
__arm926_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif


#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r0, #4				@ disable write-back on caches explicitly
	mcr	p15, 7, r0, c15, c0, 0
#endif 

	adr	r5, arm926_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000			@ .1.. .... .... ....
#endif
	ret	lr
	.size	__arm926_setup, . - __arm926_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 0001 ..11 0101
	 * 
	 */
	.type	arm926_crval, #object
arm926_crval:
	crval	clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions arm926, dabort=v5tj_early_abort, pabort=legacy_pabort, suspend=1

	.section ".rodata"

	string	cpu_arch_name, "armv5tej"
	string	cpu_elf_name, "v5"
	string	cpu_arm926_name, "ARM926EJ-S"

	.align

	.section ".proc.info.init", "a"

	.type	__arm926_proc_info,#object
__arm926_proc_info:
	.long	0x41069260			@ ARM926EJ-S (v5TEJ)
	.long	0xff0ffff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	initfn	__arm926_setup, __arm926_proc_info
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
	.long	cpu_arm926_name
	.long	arm926_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm926_cache_fns
	.size	__arm926_proc_info, . - __arm926_proc_info
Commit	Line	Data
1a59d1b8	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
1da177e4 LT	2	/*
	3	* linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
	4	*
	5	* Copyright (C) 1999-2001 ARM Limited
	6	* Copyright (C) 2000 Deep Blue Solutions Ltd.
d090ddda	7	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4	8	*
1da177e4 LT	9	* These are the low level assembler for performing cache and TLB
	10	* functions on the arm926.
	11	*
	12	* CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
	13	*/
	14	#include <linux/linkage.h>
1da177e4	15	#include <linux/init.h>
1036b895	16	#include <linux/cfi_types.h>
65fddcfc	17	#include <linux/pgtable.h>
1da177e4	18	#include <asm/assembler.h>
5ec9407d	19	#include <asm/hwcap.h>
74945c86	20	#include <asm/pgtable-hwdef.h>
1da177e4 LT	21	#include <asm/page.h>
	22	#include <asm/ptrace.h>
	23	#include "proc-macros.S"
	24
	25	/*
	26	* This is the maximum size of an area which will be invalidated
	27	* using the single invalidate entry instructions. Anything larger
	28	* than this, and we go for the whole cache.
	29	*
	30	* This value should be chosen such that we choose the cheapest
	31	* alternative.
	32	*/
	33	#define CACHE_DLIMIT 16384
	34
	35	/*
	36	* the cache line size of the I and D cache
	37	*/
	38	#define CACHE_DLINESIZE 32
	39
	40	.text
	41	/*
	42	* cpu_arm926_proc_init()
	43	*/
51db13aa	44	SYM_TYPED_FUNC_START(cpu_arm926_proc_init)
6ebbf2ce	45	ret lr
51db13aa	46	SYM_FUNC_END(cpu_arm926_proc_init)
1da177e4 LT	47
	48	/*
	49	* cpu_arm926_proc_fin()
	50	*/
51db13aa	51	SYM_TYPED_FUNC_START(cpu_arm926_proc_fin)
1da177e4 LT	52	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	53	bic r0, r0, #0x1000 @ ...i............
	54	bic r0, r0, #0x000e @ ............wca.
	55	mcr p15, 0, r0, c1, c0, 0 @ disable caches
6ebbf2ce	56	ret lr
51db13aa	57	SYM_FUNC_END(cpu_arm926_proc_fin)
1da177e4 LT	58
	59	/*
	60	* cpu_arm926_reset(loc)
	61	*
	62	* Perform a soft reset of the system. Put the CPU into the
	63	* same state as it would be if it had been reset, and branch
	64	* to what would be the reset vector.
	65	*
	66	* loc: location to jump to for soft reset
	67	*/
	68	.align 5
1a4baafa	69	.pushsection .idmap.text, "ax"
51db13aa	70	SYM_TYPED_FUNC_START(cpu_arm926_reset)
1da177e4 LT	71	mov ip, #0
	72	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	73	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	74	#ifdef CONFIG_MMU
1da177e4	75	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	76	#endif
1da177e4 LT	77	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	78	bic ip, ip, #0x000f @ ............wcam
	79	bic ip, ip, #0x1100 @ ...i...s........
	80	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
6ebbf2ce	81	ret r0
51db13aa	82	SYM_FUNC_END(cpu_arm926_reset)
1a4baafa	83	.popsection
1da177e4 LT	84
	85	/*
	86	* cpu_arm926_do_idle()
	87	*
	88	* Called with IRQs disabled
	89	*/
	90	.align 10
51db13aa	91	SYM_TYPED_FUNC_START(cpu_arm926_do_idle)
1da177e4 LT	92	mov r0, #0
	93	mrc p15, 0, r1, c1, c0, 0 @ Read control register
	94	mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
	95	bic r2, r1, #1 << 12
0214f922 RK	96	mrs r3, cpsr @ Disable FIQs while Icache
	97	orr ip, r3, #PSR_F_BIT @ is disabled
	98	msr cpsr_c, ip
1da177e4 LT	99	mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
	100	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	101	mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
0214f922	102	msr cpsr_c, r3 @ Restore FIQ state
6ebbf2ce	103	ret lr
51db13aa	104	SYM_FUNC_END(cpu_arm926_do_idle)
1da177e4	105
c8c90860 MW	106	/*
	107	* flush_icache_all()
	108	*
	109	* Unconditionally clean and invalidate the entire icache.
	110	*/
1036b895	111	SYM_TYPED_FUNC_START(arm926_flush_icache_all)
c8c90860 MW	112	mov r0, #0
c8c90860 MW	113	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
6ebbf2ce	114	ret lr
1036b895	115	SYM_FUNC_END(arm926_flush_icache_all)
c8c90860	116
1da177e4 LT	117	/*
	118	* flush_user_cache_all()
	119	*
	120	* Clean and invalidate all cache entries in a particular
	121	* address space.
	122	*/
2074beeb	123	SYM_FUNC_ALIAS(arm926_flush_user_cache_all, arm926_flush_kern_cache_all)
1da177e4 LT	124
	125	/*
	126	* flush_kern_cache_all()
	127	*
	128	* Clean and invalidate the entire cache.
	129	*/
1036b895	130	SYM_TYPED_FUNC_START(arm926_flush_kern_cache_all)
1da177e4 LT	131	mov r2, #VM_EXEC
	132	mov ip, #0
	133	__flush_whole_cache:
	134	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	135	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	136	#else
9f1984c6	137	1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
1da177e4 LT	138	bne 1b
	139	#endif
	140	tst r2, #VM_EXEC
	141	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	142	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	143	ret lr
1036b895	144	SYM_FUNC_END(arm926_flush_kern_cache_all)
1da177e4 LT	145
	146	/*
	147	* flush_user_cache_range(start, end, flags)
	148	*
	149	* Clean and invalidate a range of cache entries in the
	150	* specified address range.
	151	*
	152	* - start - start address (inclusive)
	153	* - end - end address (exclusive)
	154	* - flags - vm_flags describing address space
	155	*/
1036b895	156	SYM_TYPED_FUNC_START(arm926_flush_user_cache_range)
1da177e4 LT	157	mov ip, #0
	158	sub r3, r1, r0 @ calculate total size
	159	cmp r3, #CACHE_DLIMIT
	160	bgt __flush_whole_cache
	161	1: tst r2, #VM_EXEC
	162	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	163	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	164	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	165	add r0, r0, #CACHE_DLINESIZE
	166	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	167	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	168	add r0, r0, #CACHE_DLINESIZE
	169	#else
	170	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	171	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	172	add r0, r0, #CACHE_DLINESIZE
	173	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	174	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	175	add r0, r0, #CACHE_DLINESIZE
	176	#endif
	177	cmp r0, r1
	178	blo 1b
	179	tst r2, #VM_EXEC
	180	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	181	ret lr
1036b895	182	SYM_FUNC_END(arm926_flush_user_cache_range)
1da177e4 LT	183
	184	/*
	185	* coherent_kern_range(start, end)
	186	*
	187	* Ensure coherency between the Icache and the Dcache in the
	188	* region described by start, end. If you have non-snooping
	189	* Harvard caches, you need to implement this function.
	190	*
	191	* - start - virtual start address
	192	* - end - virtual end address
	193	*/
1036b895	194	SYM_TYPED_FUNC_START(arm926_coherent_kern_range)
7b749aad	195	#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
1036b895	196	b arm926_coherent_user_range
7b749aad	197	#endif
1036b895	198	SYM_FUNC_END(arm926_coherent_kern_range)
1da177e4 LT	199
	200	/*
	201	* coherent_user_range(start, end)
	202	*
	203	* Ensure coherency between the Icache and the Dcache in the
	204	* region described by start, end. If you have non-snooping
	205	* Harvard caches, you need to implement this function.
	206	*
	207	* - start - virtual start address
	208	* - end - virtual end address
	209	*/
1036b895	210	SYM_TYPED_FUNC_START(arm926_coherent_user_range)
1da177e4 LT	211	bic r0, r0, #CACHE_DLINESIZE - 1
	212	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	213	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
	214	add r0, r0, #CACHE_DLINESIZE
	215	cmp r0, r1
	216	blo 1b
	217	mcr p15, 0, r0, c7, c10, 4 @ drain WB
c5102f59	218	mov r0, #0
6ebbf2ce	219	ret lr
1036b895	220	SYM_FUNC_END(arm926_coherent_user_range)
1da177e4 LT	221
1da177e4 LT	222	/*
2c9b9c84	223	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	224	*
	225	* Ensure no D cache aliasing occurs, either with itself or
	226	* the I cache
	227	*
2c9b9c84 RK	228	* - addr - kernel address
2c9b9c84 RK	229	* - size - region size
1da177e4	230	*/
1036b895	231	SYM_TYPED_FUNC_START(arm926_flush_kern_dcache_area)
2c9b9c84	232	add r1, r0, r1
1da177e4 LT	233	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	234	add r0, r0, #CACHE_DLINESIZE
	235	cmp r0, r1
	236	blo 1b
	237	mov r0, #0
	238	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	239	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	240	ret lr
1036b895	241	SYM_FUNC_END(arm926_flush_kern_dcache_area)
1da177e4 LT	242
	243	/*
	244	* dma_inv_range(start, end)
	245	*
	246	* Invalidate (discard) the specified virtual address range.
	247	* May not write back any entries. If 'start' or 'end'
	248	* are not cache line aligned, those lines must be written
	249	* back.
	250	*
	251	* - start - virtual start address
	252	* - end - virtual end address
	253	*
	254	* (same as v4wb)
	255	*/
702b94bf	256	arm926_dma_inv_range:
1da177e4 LT	257	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	258	tst r0, #CACHE_DLINESIZE - 1
	259	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	260	tst r1, #CACHE_DLINESIZE - 1
	261	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	262	#endif
	263	bic r0, r0, #CACHE_DLINESIZE - 1
	264	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	265	add r0, r0, #CACHE_DLINESIZE
	266	cmp r0, r1
	267	blo 1b
	268	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	269	ret lr
1da177e4 LT	270
	271	/*
	272	* dma_clean_range(start, end)
	273	*
	274	* Clean the specified virtual address range.
	275	*
	276	* - start - virtual start address
	277	* - end - virtual end address
	278	*
	279	* (same as v4wb)
	280	*/
702b94bf	281	arm926_dma_clean_range:
1da177e4 LT	282	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	283	bic r0, r0, #CACHE_DLINESIZE - 1
	284	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	285	add r0, r0, #CACHE_DLINESIZE
	286	cmp r0, r1
	287	blo 1b
	288	#endif
	289	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	290	ret lr
1da177e4 LT	291
	292	/*
	293	* dma_flush_range(start, end)
	294	*
	295	* Clean and invalidate the specified virtual address range.
	296	*
	297	* - start - virtual start address
	298	* - end - virtual end address
	299	*/
1036b895	300	SYM_TYPED_FUNC_START(arm926_dma_flush_range)
1da177e4 LT	301	bic r0, r0, #CACHE_DLINESIZE - 1
	302	1:
	303	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	304	mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	305	#else
b3a8b751	306	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
1da177e4 LT	307	#endif
	308	add r0, r0, #CACHE_DLINESIZE
	309	cmp r0, r1
	310	blo 1b
	311	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	312	ret lr
1036b895	313	SYM_FUNC_END(arm926_dma_flush_range)
1da177e4	314
a9c9147e RK	315	/*
	316	* dma_map_area(start, size, dir)
	317	* - start - kernel virtual start address
	318	* - size - size of region
	319	* - dir - DMA direction
	320	*/
1036b895	321	SYM_TYPED_FUNC_START(arm926_dma_map_area)
a9c9147e RK	322	add r1, r1, r0
	323	cmp r2, #DMA_TO_DEVICE
	324	beq arm926_dma_clean_range
	325	bcs arm926_dma_inv_range
	326	b arm926_dma_flush_range
1036b895	327	SYM_FUNC_END(arm926_dma_map_area)
a9c9147e RK	328
	329	/*
	330	* dma_unmap_area(start, size, dir)
	331	* - start - kernel virtual start address
	332	* - size - size of region
	333	* - dir - DMA direction
	334	*/
1036b895	335	SYM_TYPED_FUNC_START(arm926_dma_unmap_area)
6ebbf2ce	336	ret lr
1036b895	337	SYM_FUNC_END(arm926_dma_unmap_area)
a9c9147e	338
51db13aa	339	SYM_TYPED_FUNC_START(cpu_arm926_dcache_clean_area)
1da177e4 LT	340	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	341	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	342	add r0, r0, #CACHE_DLINESIZE
	343	subs r1, r1, #CACHE_DLINESIZE
	344	bhi 1b
	345	#endif
	346	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	347	ret lr
51db13aa	348	SYM_FUNC_END(cpu_arm926_dcache_clean_area)
1da177e4 LT	349
	350	/* =============================== PageTable ============================== */
	351
	352	/*
	353	* cpu_arm926_switch_mm(pgd)
	354	*
	355	* Set the translation base pointer to be as described by pgd.
	356	*
	357	* pgd: new page tables
	358	*/
	359	.align 5
51db13aa LW	360
51db13aa LW	361	SYM_TYPED_FUNC_START(cpu_arm926_switch_mm)
d090ddda	362	#ifdef CONFIG_MMU
1da177e4 LT	363	mov ip, #0
	364	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	365	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	366	#else
	367	@ && 'Clean & Invalidate whole DCache'
9f1984c6	368	1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
1da177e4 LT	369	bne 1b
	370	#endif
	371	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	372	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	373	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	374	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	375	#endif
6ebbf2ce	376	ret lr
51db13aa	377	SYM_FUNC_END(cpu_arm926_switch_mm)
1da177e4 LT	378
1da177e4 LT	379	/*
ad1ae2fe	380	* cpu_arm926_set_pte_ext(ptep, pte, ext)
1da177e4 LT	381	*
	382	* Set a PTE and flush it out
	383	*/
	384	.align 5
51db13aa	385	SYM_TYPED_FUNC_START(cpu_arm926_set_pte_ext)
d090ddda	386	#ifdef CONFIG_MMU
da091653	387	armv3_set_pte_ext
1da177e4 LT	388	mov r0, r0
	389	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	390	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	391	#endif
	392	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	393	#endif
6ebbf2ce	394	ret lr
51db13aa	395	SYM_FUNC_END(cpu_arm926_set_pte_ext)
1da177e4	396
f6b0fa02 RK	397	/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
f6b0fa02 RK	398	.globl cpu_arm926_suspend_size
de8e71ca	399	.equ cpu_arm926_suspend_size, 4 * 3
b6c7aabd	400	#ifdef CONFIG_ARM_CPU_SUSPEND
51db13aa	401	SYM_TYPED_FUNC_START(cpu_arm926_do_suspend)
de8e71ca	402	stmfd sp!, {r4 - r6, lr}
f6b0fa02 RK	403	mrc p15, 0, r4, c13, c0, 0 @ PID
f6b0fa02 RK	404	mrc p15, 0, r5, c3, c0, 0 @ Domain ID
de8e71ca RK	405	mrc p15, 0, r6, c1, c0, 0 @ Control register
	406	stmia r0, {r4 - r6}
	407	ldmfd sp!, {r4 - r6, pc}
51db13aa	408	SYM_FUNC_END(cpu_arm926_do_suspend)
f6b0fa02	409
51db13aa	410	SYM_TYPED_FUNC_START(cpu_arm926_do_resume)
f6b0fa02 RK	411	mov ip, #0
	412	mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
	413	mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
de8e71ca	414	ldmia r0, {r4 - r6}
f6b0fa02 RK	415	mcr p15, 0, r4, c13, c0, 0 @ PID
f6b0fa02 RK	416	mcr p15, 0, r5, c3, c0, 0 @ Domain ID
de8e71ca RK	417	mcr p15, 0, r1, c2, c0, 0 @ TTB address
de8e71ca RK	418	mov r0, r6 @ control register
f6b0fa02	419	b cpu_resume_mmu
51db13aa	420	SYM_FUNC_END(cpu_arm926_do_resume)
f6b0fa02 RK	421	#endif
f6b0fa02 RK	422
1da177e4 LT	423	.type __arm926_setup, #function
	424	__arm926_setup:
	425	mov r0, #0
	426	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	427	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	428	#ifdef CONFIG_MMU
1da177e4	429	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	430	#endif
1da177e4 LT	431
	432
	433	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	434	mov r0, #4 @ disable write-back on caches explicitly
	435	mcr p15, 7, r0, c15, c0, 0
	436	#endif
	437
22b19086 RK	438	adr r5, arm926_crval
22b19086 RK	439	ldmia r5, {r5, r6}
1da177e4	440	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	441	bic r0, r0, r5
22b19086	442	orr r0, r0, r6
1da177e4 LT	443	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	444	orr r0, r0, #0x4000 @ .1.. .... .... ....
	445	#endif
6ebbf2ce	446	ret lr
1da177e4 LT	447	.size __arm926_setup, . - __arm926_setup
	448
	449	/*
	450	* R
	451	* .RVI ZFRS BLDP WCAM
	452	* .011 0001 ..11 0101
	453	*
	454	*/
22b19086 RK	455	.type arm926_crval, #object
	456	arm926_crval:
	457	crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
1da177e4 LT	458
	459	__INITDATA
	460
be90da45 DM	461	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
be90da45 DM	462	define_processor_functions arm926, dabort=v5tj_early_abort, pabort=legacy_pabort, suspend=1
1da177e4 LT	463
	464	.section ".rodata"
	465
be90da45 DM	466	string cpu_arch_name, "armv5tej"
	467	string cpu_elf_name, "v5"
	468	string cpu_arm926_name, "ARM926EJ-S"
1da177e4 LT	469
	470	.align
	471
790756c7	472	.section ".proc.info.init", "a"
1da177e4 LT	473
	474	.type __arm926_proc_info,#object
	475	__arm926_proc_info:
	476	.long 0x41069260 @ ARM926EJ-S (v5TEJ)
	477	.long 0xff0ffff0
	478	.long PMD_TYPE_SECT \| \
	479	PMD_SECT_BUFFERABLE \| \
	480	PMD_SECT_CACHEABLE \| \
	481	PMD_BIT4 \| \
	482	PMD_SECT_AP_WRITE \| \
	483	PMD_SECT_AP_READ
8799ee9f RK	484	.long PMD_TYPE_SECT \| \
	485	PMD_BIT4 \| \
	486	PMD_SECT_AP_WRITE \| \
	487	PMD_SECT_AP_READ
bf35706f	488	initfn __arm926_setup, __arm926_proc_info
1da177e4 LT	489	.long cpu_arch_name
1da177e4 LT	490	.long cpu_elf_name
efe90d27	491	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_JAVA
1da177e4 LT	492	.long cpu_arm926_name
	493	.long arm926_processor_functions
	494	.long v4wbi_tlb_fns
	495	.long v4wb_user_fns
	496	.long arm926_cache_fns
	497	.size __arm926_proc_info, . - __arm926_proc_info