[linux-block.git] / arch / arm / mm / proc-arm920.S

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 *  linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920
 *
 *  Copyright (C) 1999,2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm920.
 *
 *  CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/cfi_types.h>
#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * The size of one data cache line.
 */
#define CACHE_DLINESIZE	32

/*
 * The number of data cache segments.
 */
#define CACHE_DSEGMENTS	8

/*
 * The number of lines in a cache segment.
 */
#define CACHE_DENTRIES	64

/*
 * This is the size at which it becomes more efficient to
 * clean the whole cache, rather than using the individual
 * cache line maintenance instructions.
 */
#define CACHE_DLIMIT	65536


	.text
/*
 * cpu_arm920_proc_init()
 */
SYM_TYPED_FUNC_START(cpu_arm920_proc_init)
	ret	lr
SYM_FUNC_END(cpu_arm920_proc_init)

/*
 * cpu_arm920_proc_fin()
 */
SYM_TYPED_FUNC_START(cpu_arm920_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ret	lr
SYM_FUNC_END(cpu_arm920_proc_fin)

/*
 * cpu_arm920_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
	.pushsection	.idmap.text, "ax"
SYM_TYPED_FUNC_START(cpu_arm920_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	ret	r0
SYM_FUNC_END(cpu_arm920_reset)
	.popsection

/*
 * cpu_arm920_do_idle()
 */
	.align	5
SYM_TYPED_FUNC_START(cpu_arm920_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	ret	lr
SYM_FUNC_END(cpu_arm920_do_idle)

#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
SYM_TYPED_FUNC_START(arm920_flush_icache_all)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	ret	lr
SYM_FUNC_END(arm920_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 */
SYM_FUNC_ALIAS(arm920_flush_user_cache_all, arm920_flush_kern_cache_all)

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
SYM_TYPED_FUNC_START(arm920_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 8 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 5
	bcs	1b				@ segments 7 to 0
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm920_flush_kern_cache_all)

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags for address space
 */
SYM_TYPED_FUNC_START(arm920_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	tst	r2, #VM_EXEC
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm920_flush_user_cache_range)

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
SYM_TYPED_FUNC_START(arm920_coherent_kern_range)
#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
	b	arm920_coherent_user_range
#endif
SYM_FUNC_END(arm920_coherent_kern_range)

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
SYM_TYPED_FUNC_START(arm920_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	r0, #0
	ret	lr
SYM_FUNC_END(arm920_coherent_user_range)

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
SYM_TYPED_FUNC_START(arm920_flush_kern_dcache_area)
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm920_flush_kern_dcache_area)

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm920_dma_inv_range:
	tst	r0, #CACHE_DLINESIZE - 1
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm920_dma_clean_range:
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
SYM_TYPED_FUNC_START(arm920_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm920_dma_flush_range)

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
SYM_TYPED_FUNC_START(arm920_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm920_dma_clean_range
	bcs	arm920_dma_inv_range
	b	arm920_dma_flush_range
SYM_FUNC_END(arm920_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
SYM_TYPED_FUNC_START(arm920_dma_unmap_area)
	ret	lr
SYM_FUNC_END(arm920_dma_unmap_area)

#endif /* !CONFIG_CPU_DCACHE_WRITETHROUGH */


SYM_TYPED_FUNC_START(cpu_arm920_dcache_clean_area)
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
	ret	lr
SYM_FUNC_END(cpu_arm920_dcache_clean_area)

/* =============================== PageTable ============================== */

/*
 * cpu_arm920_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
SYM_TYPED_FUNC_START(cpu_arm920_switch_mm)
#ifdef CONFIG_MMU
	mov	ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
@ && 'Clean & Invalidate whole DCache'
@ && Re-written to use Index Ops.
@ && Uses registers r1, r3 and ip

	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 8 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean & invalidate D index
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 5
	bcs	1b				@ segments 7 to 0
#endif
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	ret	lr
SYM_FUNC_END(cpu_arm920_switch_mm)

/*
 * cpu_arm920_set_pte(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
	.align	5
SYM_TYPED_FUNC_START(cpu_arm920_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif
	ret	lr
SYM_FUNC_END(cpu_arm920_set_pte_ext)

/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
.globl	cpu_arm920_suspend_size
.equ	cpu_arm920_suspend_size, 4 * 3
#ifdef CONFIG_ARM_CPU_SUSPEND
SYM_TYPED_FUNC_START(cpu_arm920_do_suspend)
	stmfd	sp!, {r4 - r6, lr}
	mrc	p15, 0, r4, c13, c0, 0	@ PID
	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
	mrc	p15, 0, r6, c1, c0, 0	@ Control register
	stmia	r0, {r4 - r6}
	ldmfd	sp!, {r4 - r6, pc}
SYM_FUNC_END(cpu_arm920_do_suspend)

SYM_TYPED_FUNC_START(cpu_arm920_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I+D TLBs
	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I+D caches
	ldmia	r0, {r4 - r6}
	mcr	p15, 0, r4, c13, c0, 0	@ PID
	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
	mcr	p15, 0, r1, c2, c0, 0	@ TTB address
	mov	r0, r6			@ control register
	b	cpu_resume_mmu
SYM_FUNC_END(cpu_arm920_do_resume)
#endif

	.type	__arm920_setup, #function
__arm920_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif
	adr	r5, arm920_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
	ret	lr
	.size	__arm920_setup, . - __arm920_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * ..11 0001 ..11 0101
	 * 
	 */
	.type	arm920_crval, #object
arm920_crval:
	crval	clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130

	__INITDATA
	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions arm920, dabort=v4t_early_abort, pabort=legacy_pabort, suspend=1

	.section ".rodata"

	string	cpu_arch_name, "armv4t"
	string	cpu_elf_name, "v4"
	string	cpu_arm920_name, "ARM920T"

	.align

	.section ".proc.info.init", "a"

	.type	__arm920_proc_info,#object
__arm920_proc_info:
	.long	0x41009200
	.long	0xff00fff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	initfn	__arm920_setup, __arm920_proc_info
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
	.long	cpu_arm920_name
	.long	arm920_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	.long	arm920_cache_fns
#else
	.long	v4wt_cache_fns
#endif
	.size	__arm920_proc_info, . - __arm920_proc_info
Commit	Line	Data
1a59d1b8	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
1da177e4 LT	2	/*
	3	* linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920
	4	*
	5	* Copyright (C) 1999,2000 ARM Limited
	6	* Copyright (C) 2000 Deep Blue Solutions Ltd.
d090ddda	7	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4	8	*
1da177e4 LT	9	* These are the low level assembler for performing cache and TLB
	10	* functions on the arm920.
	11	*
	12	* CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
	13	*/
	14	#include <linux/linkage.h>
1da177e4	15	#include <linux/init.h>
1036b895	16	#include <linux/cfi_types.h>
65fddcfc	17	#include <linux/pgtable.h>
1da177e4	18	#include <asm/assembler.h>
5ec9407d	19	#include <asm/hwcap.h>
74945c86	20	#include <asm/pgtable-hwdef.h>
1da177e4 LT	21	#include <asm/page.h>
	22	#include <asm/ptrace.h>
	23	#include "proc-macros.S"
	24
	25	/*
	26	* The size of one data cache line.
	27	*/
	28	#define CACHE_DLINESIZE 32
	29
	30	/*
	31	* The number of data cache segments.
	32	*/
	33	#define CACHE_DSEGMENTS 8
	34
	35	/*
	36	* The number of lines in a cache segment.
	37	*/
	38	#define CACHE_DENTRIES 64
	39
	40	/*
	41	* This is the size at which it becomes more efficient to
	42	* clean the whole cache, rather than using the individual
25985edc	43	* cache line maintenance instructions.
1da177e4 LT	44	*/
	45	#define CACHE_DLIMIT 65536
	46
	47
	48	.text
	49	/*
	50	* cpu_arm920_proc_init()
	51	*/
51db13aa	52	SYM_TYPED_FUNC_START(cpu_arm920_proc_init)
6ebbf2ce	53	ret lr
51db13aa	54	SYM_FUNC_END(cpu_arm920_proc_init)
1da177e4 LT	55
	56	/*
	57	* cpu_arm920_proc_fin()
	58	*/
51db13aa	59	SYM_TYPED_FUNC_START(cpu_arm920_proc_fin)
1da177e4 LT	60	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	61	bic r0, r0, #0x1000 @ ...i............
	62	bic r0, r0, #0x000e @ ............wca.
	63	mcr p15, 0, r0, c1, c0, 0 @ disable caches
6ebbf2ce	64	ret lr
51db13aa	65	SYM_FUNC_END(cpu_arm920_proc_fin)
1da177e4 LT	66
	67	/*
	68	* cpu_arm920_reset(loc)
	69	*
	70	* Perform a soft reset of the system. Put the CPU into the
	71	* same state as it would be if it had been reset, and branch
	72	* to what would be the reset vector.
	73	*
	74	* loc: location to jump to for soft reset
	75	*/
	76	.align 5
1a4baafa	77	.pushsection .idmap.text, "ax"
51db13aa	78	SYM_TYPED_FUNC_START(cpu_arm920_reset)
1da177e4 LT	79	mov ip, #0
	80	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	81	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	82	#ifdef CONFIG_MMU
1da177e4	83	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	84	#endif
1da177e4 LT	85	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	86	bic ip, ip, #0x000f @ ............wcam
	87	bic ip, ip, #0x1100 @ ...i...s........
	88	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
6ebbf2ce	89	ret r0
51db13aa	90	SYM_FUNC_END(cpu_arm920_reset)
1a4baafa	91	.popsection
1da177e4 LT	92
	93	/*
	94	* cpu_arm920_do_idle()
	95	*/
	96	.align 5
51db13aa	97	SYM_TYPED_FUNC_START(cpu_arm920_do_idle)
1da177e4	98	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
6ebbf2ce	99	ret lr
51db13aa	100	SYM_FUNC_END(cpu_arm920_do_idle)
1da177e4 LT	101
	102	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	103
c8c90860 MW	104	/*
	105	* flush_icache_all()
	106	*
	107	* Unconditionally clean and invalidate the entire icache.
	108	*/
1036b895	109	SYM_TYPED_FUNC_START(arm920_flush_icache_all)
c8c90860 MW	110	mov r0, #0
c8c90860 MW	111	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
6ebbf2ce	112	ret lr
1036b895	113	SYM_FUNC_END(arm920_flush_icache_all)
c8c90860	114
1da177e4 LT	115	/*
	116	* flush_user_cache_all()
	117	*
	118	* Invalidate all cache entries in a particular address
	119	* space.
	120	*/
2074beeb	121	SYM_FUNC_ALIAS(arm920_flush_user_cache_all, arm920_flush_kern_cache_all)
1da177e4 LT	122
	123	/*
	124	* flush_kern_cache_all()
	125	*
	126	* Clean and invalidate the entire cache.
	127	*/
1036b895	128	SYM_TYPED_FUNC_START(arm920_flush_kern_cache_all)
1da177e4 LT	129	mov r2, #VM_EXEC
	130	mov ip, #0
	131	__flush_whole_cache:
	132	mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
	133	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
	134	2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
	135	subs r3, r3, #1 << 26
	136	bcs 2b @ entries 63 to 0
	137	subs r1, r1, #1 << 5
	138	bcs 1b @ segments 7 to 0
	139	tst r2, #VM_EXEC
	140	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	141	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	142	ret lr
1036b895	143	SYM_FUNC_END(arm920_flush_kern_cache_all)
1da177e4 LT	144
	145	/*
	146	* flush_user_cache_range(start, end, flags)
	147	*
	148	* Invalidate a range of cache entries in the specified
	149	* address space.
	150	*
	151	* - start - start address (inclusive)
	152	* - end - end address (exclusive)
	153	* - flags - vm_flags for address space
	154	*/
1036b895	155	SYM_TYPED_FUNC_START(arm920_flush_user_cache_range)
1da177e4 LT	156	mov ip, #0
	157	sub r3, r1, r0 @ calculate total size
	158	cmp r3, #CACHE_DLIMIT
	159	bhs __flush_whole_cache
	160
	161	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	162	tst r2, #VM_EXEC
	163	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	164	add r0, r0, #CACHE_DLINESIZE
	165	cmp r0, r1
	166	blo 1b
	167	tst r2, #VM_EXEC
	168	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	169	ret lr
1036b895	170	SYM_FUNC_END(arm920_flush_user_cache_range)
1da177e4 LT	171
	172	/*
	173	* coherent_kern_range(start, end)
	174	*
	175	* Ensure coherency between the Icache and the Dcache in the
	176	* region described by start, end. If you have non-snooping
	177	* Harvard caches, you need to implement this function.
	178	*
	179	* - start - virtual start address
	180	* - end - virtual end address
	181	*/
1036b895	182	SYM_TYPED_FUNC_START(arm920_coherent_kern_range)
7b749aad	183	#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
1036b895	184	b arm920_coherent_user_range
7b749aad	185	#endif
1036b895	186	SYM_FUNC_END(arm920_coherent_kern_range)
1da177e4 LT	187
	188	/*
	189	* coherent_user_range(start, end)
	190	*
	191	* Ensure coherency between the Icache and the Dcache in the
	192	* region described by start, end. If you have non-snooping
	193	* Harvard caches, you need to implement this function.
	194	*
	195	* - start - virtual start address
	196	* - end - virtual end address
	197	*/
1036b895	198	SYM_TYPED_FUNC_START(arm920_coherent_user_range)
1da177e4 LT	199	bic r0, r0, #CACHE_DLINESIZE - 1
	200	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	201	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
	202	add r0, r0, #CACHE_DLINESIZE
	203	cmp r0, r1
	204	blo 1b
	205	mcr p15, 0, r0, c7, c10, 4 @ drain WB
c5102f59	206	mov r0, #0
6ebbf2ce	207	ret lr
1036b895	208	SYM_FUNC_END(arm920_coherent_user_range)
1da177e4 LT	209
1da177e4 LT	210	/*
2c9b9c84	211	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	212	*
	213	* Ensure no D cache aliasing occurs, either with itself or
	214	* the I cache
	215	*
2c9b9c84 RK	216	* - addr - kernel address
2c9b9c84 RK	217	* - size - region size
1da177e4	218	*/
1036b895	219	SYM_TYPED_FUNC_START(arm920_flush_kern_dcache_area)
2c9b9c84	220	add r1, r0, r1
1da177e4 LT	221	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	222	add r0, r0, #CACHE_DLINESIZE
	223	cmp r0, r1
	224	blo 1b
	225	mov r0, #0
	226	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	227	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	228	ret lr
1036b895	229	SYM_FUNC_END(arm920_flush_kern_dcache_area)
1da177e4 LT	230
	231	/*
	232	* dma_inv_range(start, end)
	233	*
	234	* Invalidate (discard) the specified virtual address range.
	235	* May not write back any entries. If 'start' or 'end'
	236	* are not cache line aligned, those lines must be written
	237	* back.
	238	*
	239	* - start - virtual start address
	240	* - end - virtual end address
	241	*
	242	* (same as v4wb)
	243	*/
702b94bf	244	arm920_dma_inv_range:
1da177e4 LT	245	tst r0, #CACHE_DLINESIZE - 1
	246	bic r0, r0, #CACHE_DLINESIZE - 1
	247	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	248	tst r1, #CACHE_DLINESIZE - 1
	249	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	250	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	251	add r0, r0, #CACHE_DLINESIZE
	252	cmp r0, r1
	253	blo 1b
	254	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	255	ret lr
1da177e4 LT	256
	257	/*
	258	* dma_clean_range(start, end)
	259	*
	260	* Clean the specified virtual address range.
	261	*
	262	* - start - virtual start address
	263	* - end - virtual end address
	264	*
	265	* (same as v4wb)
	266	*/
702b94bf	267	arm920_dma_clean_range:
1da177e4 LT	268	bic r0, r0, #CACHE_DLINESIZE - 1
	269	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	270	add r0, r0, #CACHE_DLINESIZE
	271	cmp r0, r1
	272	blo 1b
	273	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	274	ret lr
1da177e4 LT	275
	276	/*
	277	* dma_flush_range(start, end)
	278	*
	279	* Clean and invalidate the specified virtual address range.
	280	*
	281	* - start - virtual start address
	282	* - end - virtual end address
	283	*/
1036b895	284	SYM_TYPED_FUNC_START(arm920_dma_flush_range)
1da177e4 LT	285	bic r0, r0, #CACHE_DLINESIZE - 1
	286	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	287	add r0, r0, #CACHE_DLINESIZE
	288	cmp r0, r1
	289	blo 1b
	290	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	291	ret lr
1036b895	292	SYM_FUNC_END(arm920_dma_flush_range)
1da177e4	293
a9c9147e RK	294	/*
	295	* dma_map_area(start, size, dir)
	296	* - start - kernel virtual start address
	297	* - size - size of region
	298	* - dir - DMA direction
	299	*/
1036b895	300	SYM_TYPED_FUNC_START(arm920_dma_map_area)
a9c9147e RK	301	add r1, r1, r0
	302	cmp r2, #DMA_TO_DEVICE
	303	beq arm920_dma_clean_range
	304	bcs arm920_dma_inv_range
	305	b arm920_dma_flush_range
1036b895	306	SYM_FUNC_END(arm920_dma_map_area)
a9c9147e RK	307
	308	/*
	309	* dma_unmap_area(start, size, dir)
	310	* - start - kernel virtual start address
	311	* - size - size of region
	312	* - dir - DMA direction
	313	*/
1036b895	314	SYM_TYPED_FUNC_START(arm920_dma_unmap_area)
6ebbf2ce	315	ret lr
1036b895	316	SYM_FUNC_END(arm920_dma_unmap_area)
a9c9147e	317
1036b895	318	#endif /* !CONFIG_CPU_DCACHE_WRITETHROUGH */
1da177e4 LT	319
1da177e4 LT	320
51db13aa	321	SYM_TYPED_FUNC_START(cpu_arm920_dcache_clean_area)
1da177e4 LT	322	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	323	add r0, r0, #CACHE_DLINESIZE
	324	subs r1, r1, #CACHE_DLINESIZE
	325	bhi 1b
6ebbf2ce	326	ret lr
51db13aa	327	SYM_FUNC_END(cpu_arm920_dcache_clean_area)
1da177e4 LT	328
	329	/* =============================== PageTable ============================== */
	330
	331	/*
	332	* cpu_arm920_switch_mm(pgd)
	333	*
	334	* Set the translation base pointer to be as described by pgd.
	335	*
	336	* pgd: new page tables
	337	*/
	338	.align 5
51db13aa	339	SYM_TYPED_FUNC_START(cpu_arm920_switch_mm)
d090ddda	340	#ifdef CONFIG_MMU
1da177e4 LT	341	mov ip, #0
	342	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	343	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	344	#else
	345	@ && 'Clean & Invalidate whole DCache'
	346	@ && Re-written to use Index Ops.
	347	@ && Uses registers r1, r3 and ip
	348
	349	mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
	350	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
	351	2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
	352	subs r3, r3, #1 << 26
	353	bcs 2b @ entries 63 to 0
	354	subs r1, r1, #1 << 5
	355	bcs 1b @ segments 7 to 0
	356	#endif
	357	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	358	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	359	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	360	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	361	#endif
6ebbf2ce	362	ret lr
51db13aa	363	SYM_FUNC_END(cpu_arm920_switch_mm)
1da177e4 LT	364
1da177e4 LT	365	/*
ad1ae2fe	366	* cpu_arm920_set_pte(ptep, pte, ext)
1da177e4 LT	367	*
	368	* Set a PTE and flush it out
	369	*/
	370	.align 5
51db13aa	371	SYM_TYPED_FUNC_START(cpu_arm920_set_pte_ext)
d090ddda	372	#ifdef CONFIG_MMU
da091653	373	armv3_set_pte_ext
1da177e4 LT	374	mov r0, r0
	375	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	376	mcr p15, 0, r0, c7, c10, 4 @ drain WB
da091653	377	#endif
6ebbf2ce	378	ret lr
51db13aa	379	SYM_FUNC_END(cpu_arm920_set_pte_ext)
1da177e4	380
f6b0fa02 RK	381	/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
f6b0fa02 RK	382	.globl cpu_arm920_suspend_size
de8e71ca	383	.equ cpu_arm920_suspend_size, 4 * 3
b6c7aabd	384	#ifdef CONFIG_ARM_CPU_SUSPEND
51db13aa	385	SYM_TYPED_FUNC_START(cpu_arm920_do_suspend)
de8e71ca	386	stmfd sp!, {r4 - r6, lr}
f6b0fa02 RK	387	mrc p15, 0, r4, c13, c0, 0 @ PID
f6b0fa02 RK	388	mrc p15, 0, r5, c3, c0, 0 @ Domain ID
de8e71ca RK	389	mrc p15, 0, r6, c1, c0, 0 @ Control register
	390	stmia r0, {r4 - r6}
	391	ldmfd sp!, {r4 - r6, pc}
51db13aa	392	SYM_FUNC_END(cpu_arm920_do_suspend)
f6b0fa02	393
51db13aa	394	SYM_TYPED_FUNC_START(cpu_arm920_do_resume)
f6b0fa02 RK	395	mov ip, #0
	396	mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
	397	mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
de8e71ca	398	ldmia r0, {r4 - r6}
f6b0fa02 RK	399	mcr p15, 0, r4, c13, c0, 0 @ PID
f6b0fa02 RK	400	mcr p15, 0, r5, c3, c0, 0 @ Domain ID
de8e71ca RK	401	mcr p15, 0, r1, c2, c0, 0 @ TTB address
de8e71ca RK	402	mov r0, r6 @ control register
f6b0fa02	403	b cpu_resume_mmu
51db13aa	404	SYM_FUNC_END(cpu_arm920_do_resume)
f6b0fa02 RK	405	#endif
f6b0fa02 RK	406
1da177e4 LT	407	.type __arm920_setup, #function
	408	__arm920_setup:
	409	mov r0, #0
	410	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	411	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	412	#ifdef CONFIG_MMU
1da177e4	413	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	414	#endif
22b19086 RK	415	adr r5, arm920_crval
22b19086 RK	416	ldmia r5, {r5, r6}
1da177e4	417	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	418	bic r0, r0, r5
22b19086	419	orr r0, r0, r6
6ebbf2ce	420	ret lr
1da177e4 LT	421	.size __arm920_setup, . - __arm920_setup
	422
	423	/*
	424	* R
	425	* .RVI ZFRS BLDP WCAM
	426	* ..11 0001 ..11 0101
	427	*
	428	*/
22b19086 RK	429	.type arm920_crval, #object
	430	arm920_crval:
	431	crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
1da177e4 LT	432
1da177e4 LT	433	__INITDATA
68f5e1ac DM	434	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
68f5e1ac DM	435	define_processor_functions arm920, dabort=v4t_early_abort, pabort=legacy_pabort, suspend=1
1da177e4 LT	436
	437	.section ".rodata"
	438
68f5e1ac DM	439	string cpu_arch_name, "armv4t"
	440	string cpu_elf_name, "v4"
	441	string cpu_arm920_name, "ARM920T"
1da177e4 LT	442
	443	.align
	444
790756c7	445	.section ".proc.info.init", "a"
1da177e4 LT	446
	447	.type __arm920_proc_info,#object
	448	__arm920_proc_info:
	449	.long 0x41009200
	450	.long 0xff00fff0
	451	.long PMD_TYPE_SECT \| \
	452	PMD_SECT_BUFFERABLE \| \
	453	PMD_SECT_CACHEABLE \| \
	454	PMD_BIT4 \| \
	455	PMD_SECT_AP_WRITE \| \
	456	PMD_SECT_AP_READ
8799ee9f RK	457	.long PMD_TYPE_SECT \| \
	458	PMD_BIT4 \| \
	459	PMD_SECT_AP_WRITE \| \
	460	PMD_SECT_AP_READ
bf35706f	461	initfn __arm920_setup, __arm920_proc_info
1da177e4 LT	462	.long cpu_arch_name
	463	.long cpu_elf_name
	464	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB
	465	.long cpu_arm920_name
	466	.long arm920_processor_functions
	467	.long v4wbi_tlb_fns
	468	.long v4wb_user_fns
	469	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	470	.long arm920_cache_fns
	471	#else
	472	.long v4wt_cache_fns
	473	#endif
	474	.size __arm920_proc_info, . - __arm920_proc_info