[linux-2.6-block.git] / arch / arm / mm / proc-arm720.S

/*
 *  linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
 *
 *  Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
 *                     Rob Scott (rscott@mtrob.fdns.net)
 *  Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2004.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the ARM720T.  The ARM720T has a writethrough IDC
 * cache, so we don't need to clean it.
 *
 *  Changelog:
 *   05-09-2000 SJH	Created by moving 720 specific functions
 *			out of 'proc-arm6,7.S' per RMK discussion
 *   07-25-2000 SJH	Added idle function.
 *   08-25-2000	DBS	Updated for integration of ARM Ltd version.
 *   04-20-2004 HSC	modified for non-paged memory management mode.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/elf.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>

#include "proc-macros.S"

/*
 * Function: arm720_proc_init (void)
 *	   : arm720_proc_fin (void)
 *
 * Notes   : This processor does not require these
 */
ENTRY(cpu_arm720_dcache_clean_area)
ENTRY(cpu_arm720_proc_init)
		mov	pc, lr

ENTRY(cpu_arm720_proc_fin)
		stmfd	sp!, {lr}
		mov	ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
		msr	cpsr_c, ip
		mrc	p15, 0, r0, c1, c0, 0
		bic	r0, r0, #0x1000			@ ...i............
		bic	r0, r0, #0x000e			@ ............wca.
		mcr	p15, 0, r0, c1, c0, 0		@ disable caches
		mcr	p15, 0, r1, c7, c7, 0		@ invalidate cache
		ldmfd	sp!, {pc}

/*
 * Function: arm720_proc_do_idle(void)
 * Params  : r0 = unused
 * Purpose : put the processer in proper idle mode
 */
ENTRY(cpu_arm720_do_idle)
		mov	pc, lr

/*
 * Function: arm720_switch_mm(unsigned long pgd_phys)
 * Params  : pgd_phys	Physical address of page table
 * Purpose : Perform a task switch, saving the old process' state and restoring
 *	     the new.
 */
ENTRY(cpu_arm720_switch_mm)
#ifdef CONFIG_MMU
		mov	r1, #0
		mcr	p15, 0, r1, c7, c7, 0		@ invalidate cache
		mcr	p15, 0, r0, c2, c0, 0		@ update page table ptr
		mcr	p15, 0, r1, c8, c7, 0		@ flush TLB (v4)
#endif
		mov	pc, lr

/*
 * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
 * Params  : r0 = Address to set
 *	   : r1 = value to set
 * Purpose : Set a PTE and flush it out of any WB cache
 */
		.align	5
ENTRY(cpu_arm720_set_pte_ext)
#ifdef CONFIG_MMU
		str	r1, [r0], #-2048		@ linux version

		eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY

		bic	r2, r1, #PTE_SMALL_AP_MASK
		bic	r2, r2, #PTE_TYPE_MASK
		orr	r2, r2, #PTE_TYPE_SMALL

		tst	r1, #L_PTE_USER			@ User?
		orrne	r2, r2, #PTE_SMALL_AP_URO_SRW

		tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?
		orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW

		tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young
		movne	r2, #0

		str	r2, [r0]			@ hardware version
#endif
		mov	pc, lr

/*
 * Function: arm720_reset
 * Params  : r0 = address to jump to
 * Notes   : This sets up everything for a reset
 */
ENTRY(cpu_arm720_reset)
		mov	ip, #0
		mcr	p15, 0, ip, c7, c7, 0		@ invalidate cache
#ifdef CONFIG_MMU
		mcr	p15, 0, ip, c8, c7, 0		@ flush TLB (v4)
#endif
		mrc	p15, 0, ip, c1, c0, 0		@ get ctrl register
		bic	ip, ip, #0x000f			@ ............wcam
		bic	ip, ip, #0x2100			@ ..v....s........
		mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
		mov	pc, r0

	__INIT

	.type	__arm710_setup, #function
__arm710_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0		@ invalidate caches
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
#endif
	mrc	p15, 0, r0, c1, c0		@ get control register
	ldr	r5, arm710_cr1_clear
	bic	r0, r0, r5
	ldr	r5, arm710_cr1_set
	orr	r0, r0, r5
	mov	pc, lr				@ __ret (head.S)
	.size	__arm710_setup, . - __arm710_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .... 0001 ..11 1101
	 * 
	 */
	.type	arm710_cr1_clear, #object
	.type	arm710_cr1_set, #object
arm710_cr1_clear:
	.word	0x0f3f
arm710_cr1_set:
	.word	0x013d

	.type	__arm720_setup, #function
__arm720_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0		@ invalidate caches
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
#endif
	adr	r5, arm720_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register
	bic	r0, r0, r5
	orr	r0, r0, r6
	mov	pc, lr				@ __ret (head.S)
	.size	__arm720_setup, . - __arm720_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * ..1. 1001 ..11 1101
	 * 
	 */
	.type	arm720_crval, #object
arm720_crval:
	crval	clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130

		__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
		.type	arm720_processor_functions, #object
ENTRY(arm720_processor_functions)
		.word	v4t_late_abort
		.word	pabort_noifar
		.word	cpu_arm720_proc_init
		.word	cpu_arm720_proc_fin
		.word	cpu_arm720_reset
		.word	cpu_arm720_do_idle
		.word	cpu_arm720_dcache_clean_area
		.word	cpu_arm720_switch_mm
		.word	cpu_arm720_set_pte_ext
		.size	arm720_processor_functions, . - arm720_processor_functions

		.section ".rodata"

		.type	cpu_arch_name, #object
cpu_arch_name:	.asciz	"armv4t"
		.size	cpu_arch_name, . - cpu_arch_name

		.type	cpu_elf_name, #object
cpu_elf_name:	.asciz	"v4"
		.size	cpu_elf_name, . - cpu_elf_name

		.type	cpu_arm710_name, #object
cpu_arm710_name:
		.asciz	"ARM710T"
		.size	cpu_arm710_name, . - cpu_arm710_name

		.type	cpu_arm720_name, #object
cpu_arm720_name:
		.asciz	"ARM720T"
		.size	cpu_arm720_name, . - cpu_arm720_name

		.align

/*
 * See <asm/procinfo.h> for a definition of this structure.
 */
	
		.section ".proc.info.init", #alloc, #execinstr

		.type	__arm710_proc_info, #object
__arm710_proc_info:
		.long	0x41807100				@ cpu_val
		.long	0xffffff00				@ cpu_mask
		.long   PMD_TYPE_SECT | \
			PMD_SECT_BUFFERABLE | \
			PMD_SECT_CACHEABLE | \
			PMD_BIT4 | \
			PMD_SECT_AP_WRITE | \
			PMD_SECT_AP_READ
		.long   PMD_TYPE_SECT | \
			PMD_BIT4 | \
			PMD_SECT_AP_WRITE | \
			PMD_SECT_AP_READ
		b	__arm710_setup				@ cpu_flush
		.long	cpu_arch_name				@ arch_name
		.long	cpu_elf_name				@ elf_name
		.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB	@ elf_hwcap
		.long	cpu_arm710_name				@ name
		.long	arm720_processor_functions
		.long	v4_tlb_fns
		.long	v4wt_user_fns
		.long	v4_cache_fns
		.size	__arm710_proc_info, . - __arm710_proc_info

		.type	__arm720_proc_info, #object
__arm720_proc_info:
		.long	0x41807200				@ cpu_val
		.long	0xffffff00				@ cpu_mask
		.long   PMD_TYPE_SECT | \
			PMD_SECT_BUFFERABLE | \
			PMD_SECT_CACHEABLE | \
			PMD_BIT4 | \
			PMD_SECT_AP_WRITE | \
			PMD_SECT_AP_READ
		.long   PMD_TYPE_SECT | \
			PMD_BIT4 | \
			PMD_SECT_AP_WRITE | \
			PMD_SECT_AP_READ
		b	__arm720_setup				@ cpu_flush
		.long	cpu_arch_name				@ arch_name
		.long	cpu_elf_name				@ elf_name
		.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB	@ elf_hwcap
		.long	cpu_arm720_name				@ name
		.long	arm720_processor_functions
		.long	v4_tlb_fns
		.long	v4wt_user_fns
		.long	v4_cache_fns
		.size	__arm720_proc_info, . - __arm720_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
	3	*
	4	* Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
	5	* Rob Scott (rscott@mtrob.fdns.net)
	6	* Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
d090ddda	7	* hacked for non-paged-MM by Hyok S. Choi, 2004.
1da177e4 LT	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	*
	24	* These are the low level assembler for performing cache and TLB
	25	* functions on the ARM720T. The ARM720T has a writethrough IDC
	26	* cache, so we don't need to clean it.
	27	*
	28	* Changelog:
	29	* 05-09-2000 SJH Created by moving 720 specific functions
	30	* out of 'proc-arm6,7.S' per RMK discussion
	31	* 07-25-2000 SJH Added idle function.
	32	* 08-25-2000 DBS Updated for integration of ARM Ltd version.
d090ddda	33	* 04-20-2004 HSC modified for non-paged memory management mode.
1da177e4 LT	34	*/
	35	#include <linux/linkage.h>
	36	#include <linux/init.h>
	37	#include <asm/assembler.h>
e6ae744d	38	#include <asm/asm-offsets.h>
ee90dabc	39	#include <asm/elf.h>
74945c86	40	#include <asm/pgtable-hwdef.h>
1da177e4	41	#include <asm/pgtable.h>
1da177e4	42	#include <asm/ptrace.h>
1da177e4	43
bb8d5a55 TG	44	#include "proc-macros.S"
bb8d5a55 TG	45
1da177e4 LT	46	/*
	47	* Function: arm720_proc_init (void)
	48	* : arm720_proc_fin (void)
	49	*
	50	* Notes : This processor does not require these
	51	*/
	52	ENTRY(cpu_arm720_dcache_clean_area)
	53	ENTRY(cpu_arm720_proc_init)
	54	mov pc, lr
	55
	56	ENTRY(cpu_arm720_proc_fin)
	57	stmfd sp!, {lr}
	58	mov ip, #PSR_F_BIT \| PSR_I_BIT \| SVC_MODE
	59	msr cpsr_c, ip
	60	mrc p15, 0, r0, c1, c0, 0
	61	bic r0, r0, #0x1000 @ ...i............
	62	bic r0, r0, #0x000e @ ............wca.
	63	mcr p15, 0, r0, c1, c0, 0 @ disable caches
	64	mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
	65	ldmfd sp!, {pc}
	66
	67	/*
	68	* Function: arm720_proc_do_idle(void)
	69	* Params : r0 = unused
	70	* Purpose : put the processer in proper idle mode
	71	*/
	72	ENTRY(cpu_arm720_do_idle)
	73	mov pc, lr
	74
	75	/*
	76	* Function: arm720_switch_mm(unsigned long pgd_phys)
	77	* Params : pgd_phys Physical address of page table
	78	* Purpose : Perform a task switch, saving the old process' state and restoring
	79	* the new.
	80	*/
	81	ENTRY(cpu_arm720_switch_mm)
d090ddda	82	#ifdef CONFIG_MMU
1da177e4 LT	83	mov r1, #0
	84	mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
	85	mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
	86	mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
d090ddda	87	#endif
1da177e4 LT	88	mov pc, lr
	89
	90	/*
ad1ae2fe	91	* Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
1da177e4 LT	92	* Params : r0 = Address to set
	93	* : r1 = value to set
	94	* Purpose : Set a PTE and flush it out of any WB cache
	95	*/
	96	.align 5
ad1ae2fe	97	ENTRY(cpu_arm720_set_pte_ext)
d090ddda	98	#ifdef CONFIG_MMU
1da177e4 LT	99	str r1, [r0], #-2048 @ linux version
	100
	101	eor r1, r1, #L_PTE_PRESENT \| L_PTE_YOUNG \| L_PTE_WRITE \| L_PTE_DIRTY
	102
	103	bic r2, r1, #PTE_SMALL_AP_MASK
	104	bic r2, r2, #PTE_TYPE_MASK
	105	orr r2, r2, #PTE_TYPE_SMALL
	106
	107	tst r1, #L_PTE_USER @ User?
	108	orrne r2, r2, #PTE_SMALL_AP_URO_SRW
	109
	110	tst r1, #L_PTE_WRITE \| L_PTE_DIRTY @ Write and Dirty?
	111	orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
	112
	113	tst r1, #L_PTE_PRESENT \| L_PTE_YOUNG @ Present and Young
	114	movne r2, #0
	115
	116	str r2, [r0] @ hardware version
d090ddda	117	#endif
1da177e4 LT	118	mov pc, lr
	119
	120	/*
	121	* Function: arm720_reset
	122	* Params : r0 = address to jump to
	123	* Notes : This sets up everything for a reset
	124	*/
	125	ENTRY(cpu_arm720_reset)
	126	mov ip, #0
	127	mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
d090ddda	128	#ifdef CONFIG_MMU
1da177e4	129	mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
d090ddda	130	#endif
1da177e4 LT	131	mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
	132	bic ip, ip, #0x000f @ ............wcam
	133	bic ip, ip, #0x2100 @ ..v....s........
	134	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	135	mov pc, r0
	136
	137	__INIT
	138
	139	.type __arm710_setup, #function
	140	__arm710_setup:
	141	mov r0, #0
	142	mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
d090ddda	143	#ifdef CONFIG_MMU
1da177e4	144	mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
d090ddda	145	#endif
1da177e4 LT	146	mrc p15, 0, r0, c1, c0 @ get control register
	147	ldr r5, arm710_cr1_clear
	148	bic r0, r0, r5
	149	ldr r5, arm710_cr1_set
	150	orr r0, r0, r5
	151	mov pc, lr @ __ret (head.S)
	152	.size __arm710_setup, . - __arm710_setup
	153
	154	/*
	155	* R
	156	* .RVI ZFRS BLDP WCAM
	157	* .... 0001 ..11 1101
	158	*
	159	*/
	160	.type arm710_cr1_clear, #object
	161	.type arm710_cr1_set, #object
	162	arm710_cr1_clear:
	163	.word 0x0f3f
	164	arm710_cr1_set:
	165	.word 0x013d
	166
	167	.type __arm720_setup, #function
	168	__arm720_setup:
	169	mov r0, #0
	170	mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
d090ddda	171	#ifdef CONFIG_MMU
1da177e4	172	mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
d090ddda	173	#endif
22b19086 RK	174	adr r5, arm720_crval
22b19086 RK	175	ldmia r5, {r5, r6}
1da177e4	176	mrc p15, 0, r0, c1, c0 @ get control register
1da177e4	177	bic r0, r0, r5
22b19086	178	orr r0, r0, r6
1da177e4 LT	179	mov pc, lr @ __ret (head.S)
	180	.size __arm720_setup, . - __arm720_setup
	181
	182	/*
	183	* R
	184	* .RVI ZFRS BLDP WCAM
	185	* ..1. 1001 ..11 1101
	186	*
	187	*/
22b19086 RK	188	.type arm720_crval, #object
	189	arm720_crval:
	190	crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
1da177e4 LT	191
	192	__INITDATA
	193
	194	/*
	195	* Purpose : Function pointers used to access above functions - all calls
	196	* come through these
	197	*/
	198	.type arm720_processor_functions, #object
	199	ENTRY(arm720_processor_functions)
	200	.word v4t_late_abort
4a1fd556	201	.word pabort_noifar
1da177e4 LT	202	.word cpu_arm720_proc_init
	203	.word cpu_arm720_proc_fin
	204	.word cpu_arm720_reset
	205	.word cpu_arm720_do_idle
	206	.word cpu_arm720_dcache_clean_area
	207	.word cpu_arm720_switch_mm
ad1ae2fe	208	.word cpu_arm720_set_pte_ext
1da177e4 LT	209	.size arm720_processor_functions, . - arm720_processor_functions
	210
	211	.section ".rodata"
	212
	213	.type cpu_arch_name, #object
	214	cpu_arch_name: .asciz "armv4t"
	215	.size cpu_arch_name, . - cpu_arch_name
	216
	217	.type cpu_elf_name, #object
	218	cpu_elf_name: .asciz "v4"
	219	.size cpu_elf_name, . - cpu_elf_name
	220
	221	.type cpu_arm710_name, #object
	222	cpu_arm710_name:
	223	.asciz "ARM710T"
	224	.size cpu_arm710_name, . - cpu_arm710_name
	225
	226	.type cpu_arm720_name, #object
	227	cpu_arm720_name:
	228	.asciz "ARM720T"
	229	.size cpu_arm720_name, . - cpu_arm720_name
	230
	231	.align
	232
	233	/*
4baa9922	234	* See <asm/procinfo.h> for a definition of this structure.
1da177e4 LT	235	*/
1da177e4 LT	236
02b7dd12	237	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	238
	239	.type __arm710_proc_info, #object
	240	__arm710_proc_info:
	241	.long 0x41807100 @ cpu_val
	242	.long 0xffffff00 @ cpu_mask
	243	.long PMD_TYPE_SECT \| \
	244	PMD_SECT_BUFFERABLE \| \
	245	PMD_SECT_CACHEABLE \| \
	246	PMD_BIT4 \| \
	247	PMD_SECT_AP_WRITE \| \
	248	PMD_SECT_AP_READ
8799ee9f RK	249	.long PMD_TYPE_SECT \| \
	250	PMD_BIT4 \| \
	251	PMD_SECT_AP_WRITE \| \
	252	PMD_SECT_AP_READ
1da177e4 LT	253	b __arm710_setup @ cpu_flush
	254	.long cpu_arch_name @ arch_name
	255	.long cpu_elf_name @ elf_name
	256	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB @ elf_hwcap
	257	.long cpu_arm710_name @ name
	258	.long arm720_processor_functions
	259	.long v4_tlb_fns
	260	.long v4wt_user_fns
	261	.long v4_cache_fns
	262	.size __arm710_proc_info, . - __arm710_proc_info
	263
	264	.type __arm720_proc_info, #object
	265	__arm720_proc_info:
	266	.long 0x41807200 @ cpu_val
	267	.long 0xffffff00 @ cpu_mask
	268	.long PMD_TYPE_SECT \| \
	269	PMD_SECT_BUFFERABLE \| \
	270	PMD_SECT_CACHEABLE \| \
	271	PMD_BIT4 \| \
	272	PMD_SECT_AP_WRITE \| \
	273	PMD_SECT_AP_READ
8799ee9f RK	274	.long PMD_TYPE_SECT \| \
	275	PMD_BIT4 \| \
	276	PMD_SECT_AP_WRITE \| \
	277	PMD_SECT_AP_READ
1da177e4 LT	278	b __arm720_setup @ cpu_flush
	279	.long cpu_arch_name @ arch_name
	280	.long cpu_elf_name @ elf_name
	281	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB @ elf_hwcap
	282	.long cpu_arm720_name @ name
	283	.long arm720_processor_functions
	284	.long v4_tlb_fns
	285	.long v4wt_user_fns
	286	.long v4_cache_fns
	287	.size __arm720_proc_info, . - __arm720_proc_info