[linux-block.git] / arch / arm / mm / proc-arm1022.S

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 *  linux/arch/arm/mm/proc-arm1022.S: MMU functions for ARM1022E
 *
 *  Copyright (C) 2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the ARM1022E.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/cfi_types.h>
#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/ptrace.h>

#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define MAX_AREA_SIZE	32768

/*
 * The size of one data cache line.
 */
#define CACHE_DLINESIZE	32

/*
 * The number of data cache segments.
 */
#define CACHE_DSEGMENTS	16

/*
 * The number of lines in a cache segment.
 */
#define CACHE_DENTRIES	64

/*
 * This is the size at which it becomes more efficient to
 * clean the whole cache, rather than using the individual
 * cache line maintenance instructions.
 */
#define CACHE_DLIMIT	32768

	.text
/*
 * cpu_arm1022_proc_init()
 */
SYM_TYPED_FUNC_START(cpu_arm1022_proc_init)
	ret	lr
SYM_FUNC_END(cpu_arm1022_proc_init)

/*
 * cpu_arm1022_proc_fin()
 */
SYM_TYPED_FUNC_START(cpu_arm1022_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000 		@ ...i............
	bic	r0, r0, #0x000e 		@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ret	lr
SYM_FUNC_END(cpu_arm1022_proc_fin)

/*
 * cpu_arm1022_reset(loc)
 *
 * Perform a soft reset of the system.	Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
	.pushsection	.idmap.text, "ax"
SYM_TYPED_FUNC_START(cpu_arm1022_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f 		@ ............wcam
	bic	ip, ip, #0x1100 		@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	ret	r0
SYM_FUNC_END(cpu_arm1022_reset)
	.popsection

/*
 * cpu_arm1022_do_idle()
 */
	.align	5
SYM_TYPED_FUNC_START(cpu_arm1022_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	ret	lr
SYM_FUNC_END(cpu_arm1022_do_idle)

/* ================================= CACHE ================================ */

	.align	5

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
SYM_TYPED_FUNC_START(arm1022_flush_icache_all)
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
#endif
	ret	lr
SYM_FUNC_END(arm1022_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 */
SYM_FUNC_ALIAS(arm1022_flush_user_cache_all, arm1022_flush_kern_cache_all)

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
SYM_TYPED_FUNC_START(arm1022_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 16 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 5
	bcs	1b				@ segments 15 to 0
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm1022_flush_kern_cache_all)

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags for this space
 */
SYM_TYPED_FUNC_START(arm1022_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

#ifndef CONFIG_CPU_DCACHE_DISABLE
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm1022_flush_user_cache_range)

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
SYM_TYPED_FUNC_START(arm1022_coherent_kern_range)
#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
	b	arm1022_coherent_user_range
#endif
SYM_FUNC_END(arm1022_coherent_kern_range)

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
SYM_TYPED_FUNC_START(arm1022_coherent_user_range)
	mov	ip, #0
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	r0, #0
	ret	lr
SYM_FUNC_END(arm1022_coherent_user_range)

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
SYM_TYPED_FUNC_START(arm1022_flush_kern_dcache_area)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm1022_flush_kern_dcache_area)

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1022_dma_inv_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	tst	r0, #CACHE_DLINESIZE - 1
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1022_dma_clean_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
SYM_TYPED_FUNC_START(arm1022_dma_flush_range)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm1022_dma_flush_range)

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
SYM_TYPED_FUNC_START(arm1022_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm1022_dma_clean_range
	bcs	arm1022_dma_inv_range
	b	arm1022_dma_flush_range
SYM_FUNC_END(arm1022_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
SYM_TYPED_FUNC_START(arm1022_dma_unmap_area)
	ret	lr
SYM_FUNC_END(arm1022_dma_unmap_area)

	.align	5
SYM_TYPED_FUNC_START(cpu_arm1022_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mov	ip, #0
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	ret	lr
SYM_FUNC_END(cpu_arm1022_dcache_clean_area)

/* =============================== PageTable ============================== */

/*
 * cpu_arm1022_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
SYM_TYPED_FUNC_START(cpu_arm1022_switch_mm)
#ifdef CONFIG_MMU
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 16 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 5
	bcs	1b				@ segments 15 to 0
#endif
	mov	r1, #0
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r1, c7, c5, 0		@ invalidate I cache
#endif
	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs
#endif
	ret	lr
SYM_FUNC_END(cpu_arm1022_switch_mm)

/*
 * cpu_arm1022_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
	.align	5
SYM_TYPED_FUNC_START(cpu_arm1022_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
#endif /* CONFIG_MMU */
	ret	lr
SYM_FUNC_END(cpu_arm1022_set_pte_ext)

	.type	__arm1022_setup, #function
__arm1022_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif
	adr	r5, arm1022_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000 		@ .R..............
#endif
	ret	lr
	.size	__arm1022_setup, . - __arm1022_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 1001 ..11 0101
	 * 
	 */
	.type	arm1022_crval, #object
arm1022_crval:
	crval	clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930

	__INITDATA
	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions arm1022, dabort=v4t_early_abort, pabort=legacy_pabort

	.section ".rodata"

	string	cpu_arch_name, "armv5te"
	string	cpu_elf_name, "v5"
	string	cpu_arm1022_name, "ARM1022"

	.align

	.section ".proc.info.init", "a"

	.type	__arm1022_proc_info,#object
__arm1022_proc_info:
	.long	0x4105a220			@ ARM 1022E (v5TE)
	.long	0xff0ffff0
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	initfn	__arm1022_setup, __arm1022_proc_info
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
	.long	cpu_arm1022_name
	.long	arm1022_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm1022_cache_fns
	.size	__arm1022_proc_info, . - __arm1022_proc_info
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
1da177e4 LT	2	/*
	3	* linux/arch/arm/mm/proc-arm1022.S: MMU functions for ARM1022E
	4	*
	5	* Copyright (C) 2000 ARM Limited
	6	* Copyright (C) 2000 Deep Blue Solutions Ltd.
d090ddda	7	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4	8	*
1da177e4 LT	9	* These are the low level assembler for performing cache and TLB
	10	* functions on the ARM1022E.
	11	*/
	12	#include <linux/linkage.h>
1da177e4	13	#include <linux/init.h>
1036b895	14	#include <linux/cfi_types.h>
65fddcfc	15	#include <linux/pgtable.h>
1da177e4	16	#include <asm/assembler.h>
e6ae744d	17	#include <asm/asm-offsets.h>
5ec9407d	18	#include <asm/hwcap.h>
74945c86	19	#include <asm/pgtable-hwdef.h>
1da177e4 LT	20	#include <asm/ptrace.h>
1da177e4 LT	21
00eb0f6b RK	22	#include "proc-macros.S"
00eb0f6b RK	23
1da177e4 LT	24	/*
	25	* This is the maximum size of an area which will be invalidated
	26	* using the single invalidate entry instructions. Anything larger
	27	* than this, and we go for the whole cache.
	28	*
	29	* This value should be chosen such that we choose the cheapest
	30	* alternative.
	31	*/
	32	#define MAX_AREA_SIZE 32768
	33
	34	/*
	35	* The size of one data cache line.
	36	*/
	37	#define CACHE_DLINESIZE 32
	38
	39	/*
	40	* The number of data cache segments.
	41	*/
	42	#define CACHE_DSEGMENTS 16
	43
	44	/*
	45	* The number of lines in a cache segment.
	46	*/
	47	#define CACHE_DENTRIES 64
	48
	49	/*
	50	* This is the size at which it becomes more efficient to
	51	* clean the whole cache, rather than using the individual
25985edc	52	* cache line maintenance instructions.
1da177e4 LT	53	*/
	54	#define CACHE_DLIMIT 32768
	55
	56	.text
	57	/*
	58	* cpu_arm1022_proc_init()
	59	*/
51db13aa	60	SYM_TYPED_FUNC_START(cpu_arm1022_proc_init)
6ebbf2ce	61	ret lr
51db13aa	62	SYM_FUNC_END(cpu_arm1022_proc_init)
1da177e4 LT	63
	64	/*
	65	* cpu_arm1022_proc_fin()
	66	*/
51db13aa	67	SYM_TYPED_FUNC_START(cpu_arm1022_proc_fin)
1da177e4 LT	68	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	69	bic r0, r0, #0x1000 @ ...i............
	70	bic r0, r0, #0x000e @ ............wca.
	71	mcr p15, 0, r0, c1, c0, 0 @ disable caches
6ebbf2ce	72	ret lr
51db13aa	73	SYM_FUNC_END(cpu_arm1022_proc_fin)
1da177e4 LT	74
	75	/*
	76	* cpu_arm1022_reset(loc)
	77	*
	78	* Perform a soft reset of the system. Put the CPU into the
	79	* same state as it would be if it had been reset, and branch
	80	* to what would be the reset vector.
	81	*
	82	* loc: location to jump to for soft reset
	83	*/
	84	.align 5
1a4baafa	85	.pushsection .idmap.text, "ax"
51db13aa	86	SYM_TYPED_FUNC_START(cpu_arm1022_reset)
1da177e4 LT	87	mov ip, #0
	88	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	89	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	90	#ifdef CONFIG_MMU
1da177e4	91	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	92	#endif
1da177e4 LT	93	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	94	bic ip, ip, #0x000f @ ............wcam
	95	bic ip, ip, #0x1100 @ ...i...s........
	96	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
6ebbf2ce	97	ret r0
51db13aa	98	SYM_FUNC_END(cpu_arm1022_reset)
1a4baafa	99	.popsection
1da177e4 LT	100
	101	/*
	102	* cpu_arm1022_do_idle()
	103	*/
	104	.align 5
51db13aa	105	SYM_TYPED_FUNC_START(cpu_arm1022_do_idle)
1da177e4	106	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
6ebbf2ce	107	ret lr
51db13aa	108	SYM_FUNC_END(cpu_arm1022_do_idle)
1da177e4 LT	109
	110	/* ================================= CACHE ================================ */
	111
	112	.align 5
c8c90860 MW	113
	114	/*
	115	* flush_icache_all()
	116	*
	117	* Unconditionally clean and invalidate the entire icache.
	118	*/
1036b895	119	SYM_TYPED_FUNC_START(arm1022_flush_icache_all)
c8c90860 MW	120	#ifndef CONFIG_CPU_ICACHE_DISABLE
	121	mov r0, #0
	122	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	123	#endif
6ebbf2ce	124	ret lr
1036b895	125	SYM_FUNC_END(arm1022_flush_icache_all)
c8c90860	126
1da177e4 LT	127	/*
	128	* flush_user_cache_all()
	129	*
	130	* Invalidate all cache entries in a particular address
	131	* space.
	132	*/
2074beeb	133	SYM_FUNC_ALIAS(arm1022_flush_user_cache_all, arm1022_flush_kern_cache_all)
1036b895	134
1da177e4 LT	135	/*
	136	* flush_kern_cache_all()
	137	*
	138	* Clean and invalidate the entire cache.
	139	*/
1036b895	140	SYM_TYPED_FUNC_START(arm1022_flush_kern_cache_all)
1da177e4 LT	141	mov r2, #VM_EXEC
	142	mov ip, #0
	143	__flush_whole_cache:
	144	#ifndef CONFIG_CPU_DCACHE_DISABLE
	145	mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
	146	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
	147	2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
	148	subs r3, r3, #1 << 26
	149	bcs 2b @ entries 63 to 0
	150	subs r1, r1, #1 << 5
	151	bcs 1b @ segments 15 to 0
	152	#endif
	153	tst r2, #VM_EXEC
	154	#ifndef CONFIG_CPU_ICACHE_DISABLE
	155	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	156	#endif
	157	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	158	ret lr
1036b895	159	SYM_FUNC_END(arm1022_flush_kern_cache_all)
1da177e4 LT	160
	161	/*
	162	* flush_user_cache_range(start, end, flags)
	163	*
	164	* Invalidate a range of cache entries in the specified
	165	* address space.
	166	*
	167	* - start - start address (inclusive)
	168	* - end - end address (exclusive)
	169	* - flags - vm_flags for this space
	170	*/
1036b895	171	SYM_TYPED_FUNC_START(arm1022_flush_user_cache_range)
1da177e4 LT	172	mov ip, #0
	173	sub r3, r1, r0 @ calculate total size
	174	cmp r3, #CACHE_DLIMIT
	175	bhs __flush_whole_cache
	176
	177	#ifndef CONFIG_CPU_DCACHE_DISABLE
	178	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	179	add r0, r0, #CACHE_DLINESIZE
	180	cmp r0, r1
	181	blo 1b
	182	#endif
	183	tst r2, #VM_EXEC
	184	#ifndef CONFIG_CPU_ICACHE_DISABLE
	185	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	186	#endif
	187	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	188	ret lr
1036b895	189	SYM_FUNC_END(arm1022_flush_user_cache_range)
1da177e4 LT	190
	191	/*
	192	* coherent_kern_range(start, end)
	193	*
	194	* Ensure coherency between the Icache and the Dcache in the
	195	* region described by start. If you have non-snooping
	196	* Harvard caches, you need to implement this function.
	197	*
	198	* - start - virtual start address
	199	* - end - virtual end address
	200	*/
1036b895	201	SYM_TYPED_FUNC_START(arm1022_coherent_kern_range)
7b749aad	202	#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
1036b895	203	b arm1022_coherent_user_range
7b749aad	204	#endif
1036b895	205	SYM_FUNC_END(arm1022_coherent_kern_range)
1da177e4 LT	206
	207	/*
	208	* coherent_user_range(start, end)
	209	*
	210	* Ensure coherency between the Icache and the Dcache in the
	211	* region described by start. If you have non-snooping
	212	* Harvard caches, you need to implement this function.
	213	*
	214	* - start - virtual start address
	215	* - end - virtual end address
	216	*/
1036b895	217	SYM_TYPED_FUNC_START(arm1022_coherent_user_range)
1da177e4 LT	218	mov ip, #0
	219	bic r0, r0, #CACHE_DLINESIZE - 1
	220	1:
	221	#ifndef CONFIG_CPU_DCACHE_DISABLE
	222	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	223	#endif
	224	#ifndef CONFIG_CPU_ICACHE_DISABLE
	225	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
	226	#endif
	227	add r0, r0, #CACHE_DLINESIZE
	228	cmp r0, r1
	229	blo 1b
	230	mcr p15, 0, ip, c7, c10, 4 @ drain WB
c5102f59	231	mov r0, #0
6ebbf2ce	232	ret lr
1036b895	233	SYM_FUNC_END(arm1022_coherent_user_range)
1da177e4 LT	234
1da177e4 LT	235	/*
2c9b9c84	236	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	237	*
	238	* Ensure no D cache aliasing occurs, either with itself or
	239	* the I cache
	240	*
2c9b9c84 RK	241	* - addr - kernel address
2c9b9c84 RK	242	* - size - region size
1da177e4	243	*/
1036b895	244	SYM_TYPED_FUNC_START(arm1022_flush_kern_dcache_area)
1da177e4 LT	245	mov ip, #0
1da177e4 LT	246	#ifndef CONFIG_CPU_DCACHE_DISABLE
2c9b9c84	247	add r1, r0, r1
1da177e4 LT	248	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	249	add r0, r0, #CACHE_DLINESIZE
	250	cmp r0, r1
	251	blo 1b
	252	#endif
	253	mcr p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	254	ret lr
1036b895	255	SYM_FUNC_END(arm1022_flush_kern_dcache_area)
1da177e4 LT	256
	257	/*
	258	* dma_inv_range(start, end)
	259	*
	260	* Invalidate (discard) the specified virtual address range.
	261	* May not write back any entries. If 'start' or 'end'
	262	* are not cache line aligned, those lines must be written
	263	* back.
	264	*
	265	* - start - virtual start address
	266	* - end - virtual end address
	267	*
	268	* (same as v4wb)
	269	*/
702b94bf	270	arm1022_dma_inv_range:
1da177e4 LT	271	mov ip, #0
	272	#ifndef CONFIG_CPU_DCACHE_DISABLE
	273	tst r0, #CACHE_DLINESIZE - 1
	274	bic r0, r0, #CACHE_DLINESIZE - 1
	275	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	276	tst r1, #CACHE_DLINESIZE - 1
	277	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	278	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	279	add r0, r0, #CACHE_DLINESIZE
	280	cmp r0, r1
	281	blo 1b
	282	#endif
	283	mcr p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	284	ret lr
1da177e4 LT	285
	286	/*
	287	* dma_clean_range(start, end)
	288	*
	289	* Clean the specified virtual address range.
	290	*
	291	* - start - virtual start address
	292	* - end - virtual end address
	293	*
	294	* (same as v4wb)
	295	*/
702b94bf	296	arm1022_dma_clean_range:
1da177e4 LT	297	mov ip, #0
	298	#ifndef CONFIG_CPU_DCACHE_DISABLE
	299	bic r0, r0, #CACHE_DLINESIZE - 1
	300	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	301	add r0, r0, #CACHE_DLINESIZE
	302	cmp r0, r1
	303	blo 1b
	304	#endif
	305	mcr p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	306	ret lr
1da177e4 LT	307
	308	/*
	309	* dma_flush_range(start, end)
	310	*
	311	* Clean and invalidate the specified virtual address range.
	312	*
	313	* - start - virtual start address
	314	* - end - virtual end address
	315	*/
1036b895	316	SYM_TYPED_FUNC_START(arm1022_dma_flush_range)
1da177e4 LT	317	mov ip, #0
	318	#ifndef CONFIG_CPU_DCACHE_DISABLE
	319	bic r0, r0, #CACHE_DLINESIZE - 1
	320	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	321	add r0, r0, #CACHE_DLINESIZE
	322	cmp r0, r1
	323	blo 1b
	324	#endif
	325	mcr p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	326	ret lr
1036b895	327	SYM_FUNC_END(arm1022_dma_flush_range)
1da177e4	328
a9c9147e RK	329	/*
	330	* dma_map_area(start, size, dir)
	331	* - start - kernel virtual start address
	332	* - size - size of region
	333	* - dir - DMA direction
	334	*/
1036b895	335	SYM_TYPED_FUNC_START(arm1022_dma_map_area)
a9c9147e RK	336	add r1, r1, r0
	337	cmp r2, #DMA_TO_DEVICE
	338	beq arm1022_dma_clean_range
	339	bcs arm1022_dma_inv_range
	340	b arm1022_dma_flush_range
1036b895	341	SYM_FUNC_END(arm1022_dma_map_area)
a9c9147e RK	342
	343	/*
	344	* dma_unmap_area(start, size, dir)
	345	* - start - kernel virtual start address
	346	* - size - size of region
	347	* - dir - DMA direction
	348	*/
1036b895	349	SYM_TYPED_FUNC_START(arm1022_dma_unmap_area)
6ebbf2ce	350	ret lr
1036b895	351	SYM_FUNC_END(arm1022_dma_unmap_area)
a9c9147e	352
1da177e4	353	.align 5
51db13aa	354	SYM_TYPED_FUNC_START(cpu_arm1022_dcache_clean_area)
1da177e4 LT	355	#ifndef CONFIG_CPU_DCACHE_DISABLE
	356	mov ip, #0
	357	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	358	add r0, r0, #CACHE_DLINESIZE
	359	subs r1, r1, #CACHE_DLINESIZE
	360	bhi 1b
	361	#endif
6ebbf2ce	362	ret lr
51db13aa	363	SYM_FUNC_END(cpu_arm1022_dcache_clean_area)
1da177e4 LT	364
	365	/* =============================== PageTable ============================== */
	366
	367	/*
	368	* cpu_arm1022_switch_mm(pgd)
	369	*
	370	* Set the translation base pointer to be as described by pgd.
	371	*
	372	* pgd: new page tables
	373	*/
	374	.align 5
51db13aa	375	SYM_TYPED_FUNC_START(cpu_arm1022_switch_mm)
d090ddda	376	#ifdef CONFIG_MMU
1da177e4 LT	377	#ifndef CONFIG_CPU_DCACHE_DISABLE
	378	mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
	379	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
	380	2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
	381	subs r3, r3, #1 << 26
	382	bcs 2b @ entries 63 to 0
	383	subs r1, r1, #1 << 5
	384	bcs 1b @ segments 15 to 0
	385	#endif
	386	mov r1, #0
	387	#ifndef CONFIG_CPU_ICACHE_DISABLE
	388	mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
	389	#endif
	390	mcr p15, 0, r1, c7, c10, 4 @ drain WB
	391	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	392	mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	393	#endif
6ebbf2ce	394	ret lr
51db13aa LW	395	SYM_FUNC_END(cpu_arm1022_switch_mm)
51db13aa LW	396
1da177e4	397	/*
ad1ae2fe	398	* cpu_arm1022_set_pte_ext(ptep, pte, ext)
1da177e4 LT	399	*
	400	* Set a PTE and flush it out
	401	*/
	402	.align 5
51db13aa	403	SYM_TYPED_FUNC_START(cpu_arm1022_set_pte_ext)
d090ddda	404	#ifdef CONFIG_MMU
da091653	405	armv3_set_pte_ext
1da177e4 LT	406	mov r0, r0
	407	#ifndef CONFIG_CPU_DCACHE_DISABLE
	408	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	409	#endif
d090ddda	410	#endif /* CONFIG_MMU */
6ebbf2ce	411	ret lr
51db13aa	412	SYM_FUNC_END(cpu_arm1022_set_pte_ext)
1da177e4	413
1da177e4 LT	414	.type __arm1022_setup, #function
	415	__arm1022_setup:
	416	mov r0, #0
	417	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	418	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	419	#ifdef CONFIG_MMU
1da177e4	420	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	421	#endif
22b19086 RK	422	adr r5, arm1022_crval
22b19086 RK	423	ldmia r5, {r5, r6}
1da177e4	424	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	425	bic r0, r0, r5
22b19086	426	orr r0, r0, r6
1da177e4 LT	427	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	428	orr r0, r0, #0x4000 @ .R..............
	429	#endif
6ebbf2ce	430	ret lr
1da177e4 LT	431	.size __arm1022_setup, . - __arm1022_setup
	432
	433	/*
	434	* R
	435	* .RVI ZFRS BLDP WCAM
	436	* .011 1001 ..11 0101
	437	*
	438	*/
22b19086 RK	439	.type arm1022_crval, #object
	440	arm1022_crval:
	441	crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
1da177e4 LT	442
1da177e4 LT	443	__INITDATA
f2d8cae1 DM	444	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
f2d8cae1 DM	445	define_processor_functions arm1022, dabort=v4t_early_abort, pabort=legacy_pabort
1da177e4 LT	446
	447	.section ".rodata"
	448
f2d8cae1 DM	449	string cpu_arch_name, "armv5te"
	450	string cpu_elf_name, "v5"
	451	string cpu_arm1022_name, "ARM1022"
1da177e4 LT	452
	453	.align
	454
790756c7	455	.section ".proc.info.init", "a"
1da177e4 LT	456
	457	.type __arm1022_proc_info,#object
	458	__arm1022_proc_info:
	459	.long 0x4105a220 @ ARM 1022E (v5TE)
	460	.long 0xff0ffff0
8799ee9f RK	461	.long PMD_TYPE_SECT \| \
	462	PMD_BIT4 \| \
	463	PMD_SECT_AP_WRITE \| \
	464	PMD_SECT_AP_READ
1da177e4 LT	465	.long PMD_TYPE_SECT \| \
	466	PMD_BIT4 \| \
	467	PMD_SECT_AP_WRITE \| \
	468	PMD_SECT_AP_READ
bf35706f	469	initfn __arm1022_setup, __arm1022_proc_info
1da177e4 LT	470	.long cpu_arch_name
	471	.long cpu_elf_name
	472	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB \| HWCAP_EDSP
	473	.long cpu_arm1022_name
	474	.long arm1022_processor_functions
	475	.long v4wbi_tlb_fns
	476	.long v4wb_user_fns
	477	.long arm1022_cache_fns
	478	.size __arm1022_proc_info, . - __arm1022_proc_info