[linux-block.git] / arch / arm / mm / proc-arm1020.S

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 *  linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
 *
 *  Copyright (C) 2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm1020.
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <linux/cfi_types.h>
#include <linux/pgtable.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/ptrace.h>

#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define MAX_AREA_SIZE	32768

/*
 * The size of one data cache line.
 */
#define CACHE_DLINESIZE	32

/*
 * The number of data cache segments.
 */
#define CACHE_DSEGMENTS	16

/*
 * The number of lines in a cache segment.
 */
#define CACHE_DENTRIES	64

/*
 * This is the size at which it becomes more efficient to
 * clean the whole cache, rather than using the individual
 * cache line maintenance instructions.
 */
#define CACHE_DLIMIT	32768

	.text
/*
 * cpu_arm1020_proc_init()
 */
SYM_TYPED_FUNC_START(cpu_arm1020_proc_init)
	ret	lr
SYM_FUNC_END(cpu_arm1020_proc_init)

/*
 * cpu_arm1020_proc_fin()
 */
SYM_TYPED_FUNC_START(cpu_arm1020_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000 		@ ...i............
	bic	r0, r0, #0x000e 		@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ret	lr
SYM_FUNC_END(cpu_arm1020_proc_fin)

/*
 * cpu_arm1020_reset(loc)
 *
 * Perform a soft reset of the system.	Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
	.pushsection	.idmap.text, "ax"
SYM_TYPED_FUNC_START(cpu_arm1020_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f 		@ ............wcam
	bic	ip, ip, #0x1100 		@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	ret	r0
SYM_FUNC_END(cpu_arm1020_reset)
	.popsection

/*
 * cpu_arm1020_do_idle()
 */
	.align	5
SYM_TYPED_FUNC_START(cpu_arm1020_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	ret	lr
SYM_FUNC_END(cpu_arm1020_do_idle)

/* ================================= CACHE ================================ */

	.align	5

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
SYM_TYPED_FUNC_START(arm1020_flush_icache_all)
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
#endif
	ret	lr
SYM_FUNC_END(arm1020_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 */
SYM_FUNC_ALIAS(arm1020_flush_user_cache_all, arm1020_flush_kern_cache_all)

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
SYM_TYPED_FUNC_START(arm1020_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 16 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 5
	bcs	1b				@ segments 15 to 0
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm1020_flush_kern_cache_all)

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags for this space
 */
SYM_TYPED_FUNC_START(arm1020_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, ip, c7, c10, 4
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm1020_flush_user_cache_range)

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
SYM_TYPED_FUNC_START(arm1020_coherent_kern_range)
#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
	b	arm1020_coherent_user_range
#endif
SYM_FUNC_END(arm1020_coherent_kern_range)

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
SYM_TYPED_FUNC_START(arm1020_coherent_user_range)
	mov	ip, #0
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcr	p15, 0, ip, c7, c10, 4
1:
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	r0, #0
	ret	lr
SYM_FUNC_END(arm1020_coherent_user_range)

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
SYM_TYPED_FUNC_START(arm1020_flush_kern_dcache_area)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm1020_flush_kern_dcache_area)

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1020_dma_inv_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	tst	r0, #CACHE_DLINESIZE - 1
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, ip, c7, c10, 4
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, ip, c7, c10, 4
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1020_dma_clean_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
SYM_TYPED_FUNC_START(arm1020_dma_flush_range)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcr	p15, 0, ip, c7, c10, 4
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr
SYM_FUNC_END(arm1020_dma_flush_range)

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
SYM_TYPED_FUNC_START(arm1020_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm1020_dma_clean_range
	bcs	arm1020_dma_inv_range
	b	arm1020_dma_flush_range
SYM_FUNC_END(arm1020_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
SYM_TYPED_FUNC_START(arm1020_dma_unmap_area)
	ret	lr
SYM_FUNC_END(arm1020_dma_unmap_area)

	.align	5
SYM_TYPED_FUNC_START(cpu_arm1020_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mov	ip, #0
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	ret	lr
SYM_FUNC_END(cpu_arm1020_dcache_clean_area)

/* =============================== PageTable ============================== */

/*
 * cpu_arm1020_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
SYM_TYPED_FUNC_START(cpu_arm1020_switch_mm)
#ifdef CONFIG_MMU
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r3, c7, c10, 4
	mov	r1, #0xF			@ 16 segments
1:	mov	r3, #0x3F			@ 64 entries
2:	mov	ip, r3, LSL #26 		@ shift up entry
	orr	ip, ip, r1, LSL #5		@ shift in/up index
	mcr	p15, 0, ip, c7, c14, 2		@ Clean & Inval DCache entry
	mov	ip, #0
	mcr	p15, 0, ip, c7, c10, 4
	subs	r3, r3, #1
	cmp	r3, #0
	bge	2b				@ entries 3F to 0
	subs	r1, r1, #1
	cmp	r1, #0
	bge	1b				@ segments 15 to 0

#endif
	mov	r1, #0
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r1, c7, c5, 0		@ invalidate I cache
#endif
	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs
#endif /* CONFIG_MMU */
	ret	lr
SYM_FUNC_END(cpu_arm1020_switch_mm)

/*
 * cpu_arm1020_set_pte(ptep, pte)
 *
 * Set a PTE and flush it out
 */
	.align	5
SYM_TYPED_FUNC_START(cpu_arm1020_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 4
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif /* CONFIG_MMU */
	ret	lr
SYM_FUNC_END(cpu_arm1020_set_pte_ext)

	.type	__arm1020_setup, #function
__arm1020_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif

	adr	r5, arm1020_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000 		@ .R.. .... .... ....
#endif
	ret	lr
	.size	__arm1020_setup, . - __arm1020_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 1001 ..11 0101
	 */
	.type	arm1020_crval, #object
arm1020_crval:
	crval	clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930

	__INITDATA
	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort


	.section ".rodata"

	string	cpu_arch_name, "armv5t"
	string	cpu_elf_name, "v5"

	.type	cpu_arm1020_name, #object
cpu_arm1020_name:
	.ascii	"ARM1020"
#ifndef CONFIG_CPU_ICACHE_DISABLE
	.ascii	"i"
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
	.ascii	"d"
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	.ascii	"(wt)"
#else
	.ascii	"(wb)"
#endif
#endif
#ifndef CONFIG_CPU_BPREDICT_DISABLE
	.ascii	"B"
#endif
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	.ascii	"RR"
#endif
	.ascii	"\0"
	.size	cpu_arm1020_name, . - cpu_arm1020_name

	.align

	.section ".proc.info.init", "a"

	.type	__arm1020_proc_info,#object
__arm1020_proc_info:
	.long	0x4104a200			@ ARM 1020T (Architecture v5T)
	.long	0xff0ffff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	initfn	__arm1020_setup, __arm1020_proc_info
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
	.long	cpu_arm1020_name
	.long	arm1020_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm1020_cache_fns
	.size	__arm1020_proc_info, . - __arm1020_proc_info
Commit	Line	Data
1a59d1b8	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
1da177e4 LT	2	/*
	3	* linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
	4	*
	5	* Copyright (C) 2000 ARM Limited
	6	* Copyright (C) 2000 Deep Blue Solutions Ltd.
d090ddda	7	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4	8	*
1da177e4 LT	9	* These are the low level assembler for performing cache and TLB
1da177e4 LT	10	* functions on the arm1020.
1da177e4 LT	11	*/
1da177e4 LT	12	#include <linux/linkage.h>
1da177e4	13	#include <linux/init.h>
1036b895	14	#include <linux/cfi_types.h>
65fddcfc	15	#include <linux/pgtable.h>
1da177e4	16	#include <asm/assembler.h>
e6ae744d	17	#include <asm/asm-offsets.h>
5ec9407d	18	#include <asm/hwcap.h>
74945c86	19	#include <asm/pgtable-hwdef.h>
1da177e4	20	#include <asm/ptrace.h>
1da177e4	21
00eb0f6b RK	22	#include "proc-macros.S"
00eb0f6b RK	23
1da177e4 LT	24	/*
	25	* This is the maximum size of an area which will be invalidated
	26	* using the single invalidate entry instructions. Anything larger
	27	* than this, and we go for the whole cache.
	28	*
	29	* This value should be chosen such that we choose the cheapest
	30	* alternative.
	31	*/
	32	#define MAX_AREA_SIZE 32768
	33
	34	/*
	35	* The size of one data cache line.
	36	*/
	37	#define CACHE_DLINESIZE 32
	38
	39	/*
	40	* The number of data cache segments.
	41	*/
	42	#define CACHE_DSEGMENTS 16
	43
	44	/*
	45	* The number of lines in a cache segment.
	46	*/
	47	#define CACHE_DENTRIES 64
	48
	49	/*
	50	* This is the size at which it becomes more efficient to
	51	* clean the whole cache, rather than using the individual
25985edc	52	* cache line maintenance instructions.
1da177e4 LT	53	*/
	54	#define CACHE_DLIMIT 32768
	55
	56	.text
	57	/*
	58	* cpu_arm1020_proc_init()
	59	*/
51db13aa	60	SYM_TYPED_FUNC_START(cpu_arm1020_proc_init)
6ebbf2ce	61	ret lr
51db13aa	62	SYM_FUNC_END(cpu_arm1020_proc_init)
1da177e4 LT	63
	64	/*
	65	* cpu_arm1020_proc_fin()
	66	*/
51db13aa	67	SYM_TYPED_FUNC_START(cpu_arm1020_proc_fin)
1da177e4 LT	68	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	69	bic r0, r0, #0x1000 @ ...i............
	70	bic r0, r0, #0x000e @ ............wca.
	71	mcr p15, 0, r0, c1, c0, 0 @ disable caches
6ebbf2ce	72	ret lr
51db13aa	73	SYM_FUNC_END(cpu_arm1020_proc_fin)
1da177e4 LT	74
	75	/*
	76	* cpu_arm1020_reset(loc)
	77	*
	78	* Perform a soft reset of the system. Put the CPU into the
	79	* same state as it would be if it had been reset, and branch
	80	* to what would be the reset vector.
	81	*
	82	* loc: location to jump to for soft reset
	83	*/
	84	.align 5
1a4baafa	85	.pushsection .idmap.text, "ax"
51db13aa	86	SYM_TYPED_FUNC_START(cpu_arm1020_reset)
1da177e4 LT	87	mov ip, #0
	88	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	89	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	90	#ifdef CONFIG_MMU
1da177e4	91	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	92	#endif
1da177e4 LT	93	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	94	bic ip, ip, #0x000f @ ............wcam
	95	bic ip, ip, #0x1100 @ ...i...s........
	96	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
6ebbf2ce	97	ret r0
51db13aa	98	SYM_FUNC_END(cpu_arm1020_reset)
1a4baafa	99	.popsection
1da177e4 LT	100
	101	/*
	102	* cpu_arm1020_do_idle()
	103	*/
	104	.align 5
51db13aa	105	SYM_TYPED_FUNC_START(cpu_arm1020_do_idle)
1da177e4	106	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
6ebbf2ce	107	ret lr
51db13aa	108	SYM_FUNC_END(cpu_arm1020_do_idle)
1da177e4 LT	109
	110	/* ================================= CACHE ================================ */
	111
	112	.align 5
c8c90860 MW	113
	114	/*
	115	* flush_icache_all()
	116	*
	117	* Unconditionally clean and invalidate the entire icache.
	118	*/
1036b895	119	SYM_TYPED_FUNC_START(arm1020_flush_icache_all)
c8c90860 MW	120	#ifndef CONFIG_CPU_ICACHE_DISABLE
	121	mov r0, #0
	122	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	123	#endif
6ebbf2ce	124	ret lr
1036b895	125	SYM_FUNC_END(arm1020_flush_icache_all)
c8c90860	126
1da177e4 LT	127	/*
	128	* flush_user_cache_all()
	129	*
	130	* Invalidate all cache entries in a particular address
	131	* space.
	132	*/
2074beeb	133	SYM_FUNC_ALIAS(arm1020_flush_user_cache_all, arm1020_flush_kern_cache_all)
1036b895	134
1da177e4 LT	135	/*
	136	* flush_kern_cache_all()
	137	*
	138	* Clean and invalidate the entire cache.
	139	*/
1036b895	140	SYM_TYPED_FUNC_START(arm1020_flush_kern_cache_all)
1da177e4 LT	141	mov r2, #VM_EXEC
	142	mov ip, #0
	143	__flush_whole_cache:
	144	#ifndef CONFIG_CPU_DCACHE_DISABLE
	145	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	146	mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
	147	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
	148	2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
	149	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	150	subs r3, r3, #1 << 26
	151	bcs 2b @ entries 63 to 0
	152	subs r1, r1, #1 << 5
	153	bcs 1b @ segments 15 to 0
	154	#endif
	155	tst r2, #VM_EXEC
	156	#ifndef CONFIG_CPU_ICACHE_DISABLE
	157	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	158	#endif
	159	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	160	ret lr
1036b895	161	SYM_FUNC_END(arm1020_flush_kern_cache_all)
1da177e4 LT	162
	163	/*
	164	* flush_user_cache_range(start, end, flags)
	165	*
	166	* Invalidate a range of cache entries in the specified
	167	* address space.
	168	*
	169	* - start - start address (inclusive)
	170	* - end - end address (exclusive)
	171	* - flags - vm_flags for this space
	172	*/
1036b895	173	SYM_TYPED_FUNC_START(arm1020_flush_user_cache_range)
1da177e4 LT	174	mov ip, #0
	175	sub r3, r1, r0 @ calculate total size
	176	cmp r3, #CACHE_DLIMIT
	177	bhs __flush_whole_cache
	178
	179	#ifndef CONFIG_CPU_DCACHE_DISABLE
	180	mcr p15, 0, ip, c7, c10, 4
	181	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	182	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	183	add r0, r0, #CACHE_DLINESIZE
	184	cmp r0, r1
	185	blo 1b
	186	#endif
	187	tst r2, #VM_EXEC
	188	#ifndef CONFIG_CPU_ICACHE_DISABLE
	189	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	190	#endif
	191	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	192	ret lr
1036b895	193	SYM_FUNC_END(arm1020_flush_user_cache_range)
1da177e4 LT	194
	195	/*
	196	* coherent_kern_range(start, end)
	197	*
	198	* Ensure coherency between the Icache and the Dcache in the
	199	* region described by start. If you have non-snooping
	200	* Harvard caches, you need to implement this function.
	201	*
	202	* - start - virtual start address
	203	* - end - virtual end address
	204	*/
1036b895	205	SYM_TYPED_FUNC_START(arm1020_coherent_kern_range)
7b749aad	206	#ifdef CONFIG_CFI_CLANG /* Fallthrough if !CFI */
1036b895	207	b arm1020_coherent_user_range
7b749aad	208	#endif
1036b895	209	SYM_FUNC_END(arm1020_coherent_kern_range)
1da177e4 LT	210
	211	/*
	212	* coherent_user_range(start, end)
	213	*
	214	* Ensure coherency between the Icache and the Dcache in the
	215	* region described by start. If you have non-snooping
	216	* Harvard caches, you need to implement this function.
	217	*
	218	* - start - virtual start address
	219	* - end - virtual end address
	220	*/
1036b895	221	SYM_TYPED_FUNC_START(arm1020_coherent_user_range)
1da177e4 LT	222	mov ip, #0
	223	bic r0, r0, #CACHE_DLINESIZE - 1
	224	mcr p15, 0, ip, c7, c10, 4
	225	1:
	226	#ifndef CONFIG_CPU_DCACHE_DISABLE
	227	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	228	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	229	#endif
	230	#ifndef CONFIG_CPU_ICACHE_DISABLE
	231	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
	232	#endif
	233	add r0, r0, #CACHE_DLINESIZE
	234	cmp r0, r1
	235	blo 1b
	236	mcr p15, 0, ip, c7, c10, 4 @ drain WB
c5102f59	237	mov r0, #0
6ebbf2ce	238	ret lr
1036b895	239	SYM_FUNC_END(arm1020_coherent_user_range)
1da177e4 LT	240
1da177e4 LT	241	/*
2c9b9c84	242	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	243	*
	244	* Ensure no D cache aliasing occurs, either with itself or
	245	* the I cache
	246	*
2c9b9c84 RK	247	* - addr - kernel address
2c9b9c84 RK	248	* - size - region size
1da177e4	249	*/
1036b895	250	SYM_TYPED_FUNC_START(arm1020_flush_kern_dcache_area)
1da177e4 LT	251	mov ip, #0
1da177e4 LT	252	#ifndef CONFIG_CPU_DCACHE_DISABLE
2c9b9c84	253	add r1, r0, r1
1da177e4 LT	254	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	255	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	256	add r0, r0, #CACHE_DLINESIZE
	257	cmp r0, r1
	258	blo 1b
	259	#endif
	260	mcr p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	261	ret lr
1036b895	262	SYM_FUNC_END(arm1020_flush_kern_dcache_area)
1da177e4 LT	263
	264	/*
	265	* dma_inv_range(start, end)
	266	*
	267	* Invalidate (discard) the specified virtual address range.
	268	* May not write back any entries. If 'start' or 'end'
	269	* are not cache line aligned, those lines must be written
	270	* back.
	271	*
	272	* - start - virtual start address
	273	* - end - virtual end address
	274	*
	275	* (same as v4wb)
	276	*/
702b94bf	277	arm1020_dma_inv_range:
1da177e4 LT	278	mov ip, #0
	279	#ifndef CONFIG_CPU_DCACHE_DISABLE
	280	tst r0, #CACHE_DLINESIZE - 1
	281	bic r0, r0, #CACHE_DLINESIZE - 1
	282	mcrne p15, 0, ip, c7, c10, 4
	283	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	284	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	285	tst r1, #CACHE_DLINESIZE - 1
	286	mcrne p15, 0, ip, c7, c10, 4
	287	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	288	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	289	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	290	add r0, r0, #CACHE_DLINESIZE
	291	cmp r0, r1
	292	blo 1b
	293	#endif
	294	mcr p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	295	ret lr
1da177e4 LT	296
	297	/*
	298	* dma_clean_range(start, end)
	299	*
	300	* Clean the specified virtual address range.
	301	*
	302	* - start - virtual start address
	303	* - end - virtual end address
	304	*
	305	* (same as v4wb)
	306	*/
702b94bf	307	arm1020_dma_clean_range:
1da177e4 LT	308	mov ip, #0
	309	#ifndef CONFIG_CPU_DCACHE_DISABLE
	310	bic r0, r0, #CACHE_DLINESIZE - 1
	311	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	312	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	313	add r0, r0, #CACHE_DLINESIZE
	314	cmp r0, r1
	315	blo 1b
	316	#endif
	317	mcr p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	318	ret lr
1da177e4 LT	319
	320	/*
	321	* dma_flush_range(start, end)
	322	*
	323	* Clean and invalidate the specified virtual address range.
	324	*
	325	* - start - virtual start address
	326	* - end - virtual end address
	327	*/
1036b895	328	SYM_TYPED_FUNC_START(arm1020_dma_flush_range)
1da177e4 LT	329	mov ip, #0
	330	#ifndef CONFIG_CPU_DCACHE_DISABLE
	331	bic r0, r0, #CACHE_DLINESIZE - 1
	332	mcr p15, 0, ip, c7, c10, 4
	333	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	334	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	335	add r0, r0, #CACHE_DLINESIZE
	336	cmp r0, r1
	337	blo 1b
	338	#endif
	339	mcr p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	340	ret lr
1036b895	341	SYM_FUNC_END(arm1020_dma_flush_range)
1da177e4	342
a9c9147e RK	343	/*
	344	* dma_map_area(start, size, dir)
	345	* - start - kernel virtual start address
	346	* - size - size of region
	347	* - dir - DMA direction
	348	*/
1036b895	349	SYM_TYPED_FUNC_START(arm1020_dma_map_area)
a9c9147e RK	350	add r1, r1, r0
	351	cmp r2, #DMA_TO_DEVICE
	352	beq arm1020_dma_clean_range
	353	bcs arm1020_dma_inv_range
	354	b arm1020_dma_flush_range
1036b895	355	SYM_FUNC_END(arm1020_dma_map_area)
a9c9147e RK	356
	357	/*
	358	* dma_unmap_area(start, size, dir)
	359	* - start - kernel virtual start address
	360	* - size - size of region
	361	* - dir - DMA direction
	362	*/
1036b895	363	SYM_TYPED_FUNC_START(arm1020_dma_unmap_area)
6ebbf2ce	364	ret lr
1036b895	365	SYM_FUNC_END(arm1020_dma_unmap_area)
a9c9147e	366
1da177e4	367	.align 5
51db13aa	368	SYM_TYPED_FUNC_START(cpu_arm1020_dcache_clean_area)
1da177e4 LT	369	#ifndef CONFIG_CPU_DCACHE_DISABLE
	370	mov ip, #0
	371	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	372	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	373	add r0, r0, #CACHE_DLINESIZE
	374	subs r1, r1, #CACHE_DLINESIZE
	375	bhi 1b
	376	#endif
6ebbf2ce	377	ret lr
51db13aa	378	SYM_FUNC_END(cpu_arm1020_dcache_clean_area)
1da177e4 LT	379
	380	/* =============================== PageTable ============================== */
	381
	382	/*
	383	* cpu_arm1020_switch_mm(pgd)
	384	*
	385	* Set the translation base pointer to be as described by pgd.
	386	*
	387	* pgd: new page tables
	388	*/
	389	.align 5
51db13aa	390	SYM_TYPED_FUNC_START(cpu_arm1020_switch_mm)
d090ddda	391	#ifdef CONFIG_MMU
1da177e4 LT	392	#ifndef CONFIG_CPU_DCACHE_DISABLE
	393	mcr p15, 0, r3, c7, c10, 4
	394	mov r1, #0xF @ 16 segments
	395	1: mov r3, #0x3F @ 64 entries
	396	2: mov ip, r3, LSL #26 @ shift up entry
	397	orr ip, ip, r1, LSL #5 @ shift in/up index
	398	mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
	399	mov ip, #0
	400	mcr p15, 0, ip, c7, c10, 4
	401	subs r3, r3, #1
	402	cmp r3, #0
	403	bge 2b @ entries 3F to 0
	404	subs r1, r1, #1
	405	cmp r1, #0
	406	bge 1b @ segments 15 to 0
	407
	408	#endif
	409	mov r1, #0
	410	#ifndef CONFIG_CPU_ICACHE_DISABLE
	411	mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
	412	#endif
	413	mcr p15, 0, r1, c7, c10, 4 @ drain WB
	414	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	415	mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	416	#endif /* CONFIG_MMU */
6ebbf2ce	417	ret lr
51db13aa LW	418	SYM_FUNC_END(cpu_arm1020_switch_mm)
51db13aa LW	419
1da177e4 LT	420	/*
	421	* cpu_arm1020_set_pte(ptep, pte)
	422	*
	423	* Set a PTE and flush it out
	424	*/
	425	.align 5
51db13aa	426	SYM_TYPED_FUNC_START(cpu_arm1020_set_pte_ext)
d090ddda	427	#ifdef CONFIG_MMU
da091653	428	armv3_set_pte_ext
1da177e4 LT	429	mov r0, r0
	430	#ifndef CONFIG_CPU_DCACHE_DISABLE
	431	mcr p15, 0, r0, c7, c10, 4
	432	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	433	#endif
	434	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	435	#endif /* CONFIG_MMU */
6ebbf2ce	436	ret lr
51db13aa	437	SYM_FUNC_END(cpu_arm1020_set_pte_ext)
1da177e4	438
1da177e4 LT	439	.type __arm1020_setup, #function
	440	__arm1020_setup:
	441	mov r0, #0
	442	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	443	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	444	#ifdef CONFIG_MMU
1da177e4	445	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	446	#endif
22b19086 RK	447
	448	adr r5, arm1020_crval
	449	ldmia r5, {r5, r6}
1da177e4	450	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	451	bic r0, r0, r5
22b19086	452	orr r0, r0, r6
1da177e4 LT	453	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	454	orr r0, r0, #0x4000 @ .R.. .... .... ....
	455	#endif
6ebbf2ce	456	ret lr
1da177e4 LT	457	.size __arm1020_setup, . - __arm1020_setup
	458
	459	/*
	460	* R
	461	* .RVI ZFRS BLDP WCAM
abaf48a0	462	* .011 1001 ..11 0101
1da177e4	463	*/
22b19086 RK	464	.type arm1020_crval, #object
	465	arm1020_crval:
	466	crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
1da177e4 LT	467
1da177e4 LT	468	__INITDATA
56d91650 DM	469	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
56d91650 DM	470	define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort
1da177e4	471
1da177e4 LT	472
	473	.section ".rodata"
	474
56d91650 DM	475	string cpu_arch_name, "armv5t"
56d91650 DM	476	string cpu_elf_name, "v5"
1da177e4 LT	477
	478	.type cpu_arm1020_name, #object
	479	cpu_arm1020_name:
	480	.ascii "ARM1020"
	481	#ifndef CONFIG_CPU_ICACHE_DISABLE
	482	.ascii "i"
	483	#endif
	484	#ifndef CONFIG_CPU_DCACHE_DISABLE
	485	.ascii "d"
	486	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	487	.ascii "(wt)"
	488	#else
	489	.ascii "(wb)"
	490	#endif
	491	#endif
	492	#ifndef CONFIG_CPU_BPREDICT_DISABLE
	493	.ascii "B"
	494	#endif
	495	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	496	.ascii "RR"
	497	#endif
	498	.ascii "\0"
	499	.size cpu_arm1020_name, . - cpu_arm1020_name
	500
	501	.align
	502
790756c7	503	.section ".proc.info.init", "a"
1da177e4 LT	504
	505	.type __arm1020_proc_info,#object
	506	__arm1020_proc_info:
	507	.long 0x4104a200 @ ARM 1020T (Architecture v5T)
	508	.long 0xff0ffff0
8799ee9f RK	509	.long PMD_TYPE_SECT \| \
	510	PMD_SECT_AP_WRITE \| \
	511	PMD_SECT_AP_READ
1da177e4 LT	512	.long PMD_TYPE_SECT \| \
	513	PMD_SECT_AP_WRITE \| \
	514	PMD_SECT_AP_READ
bf35706f	515	initfn __arm1020_setup, __arm1020_proc_info
1da177e4 LT	516	.long cpu_arch_name
	517	.long cpu_elf_name
	518	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB
	519	.long cpu_arm1020_name
	520	.long arm1020_processor_functions
	521	.long v4wbi_tlb_fns
	522	.long v4wb_user_fns
	523	.long arm1020_cache_fns
	524	.size __arm1020_proc_info, . - __arm1020_proc_info