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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020 | |
3 | * | |
4 | * Copyright (C) 2000 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
d090ddda | 6 | * hacked for non-paged-MM by Hyok S. Choi, 2003. |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | * | |
23 | * These are the low level assembler for performing cache and TLB | |
24 | * functions on the arm1020. | |
1da177e4 LT |
25 | */ |
26 | #include <linux/linkage.h> | |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <asm/assembler.h> | |
e6ae744d | 29 | #include <asm/asm-offsets.h> |
5ec9407d | 30 | #include <asm/hwcap.h> |
74945c86 | 31 | #include <asm/pgtable-hwdef.h> |
1da177e4 | 32 | #include <asm/pgtable.h> |
1da177e4 | 33 | #include <asm/ptrace.h> |
1da177e4 | 34 | |
00eb0f6b RK |
35 | #include "proc-macros.S" |
36 | ||
1da177e4 LT |
37 | /* |
38 | * This is the maximum size of an area which will be invalidated | |
39 | * using the single invalidate entry instructions. Anything larger | |
40 | * than this, and we go for the whole cache. | |
41 | * | |
42 | * This value should be chosen such that we choose the cheapest | |
43 | * alternative. | |
44 | */ | |
45 | #define MAX_AREA_SIZE 32768 | |
46 | ||
47 | /* | |
48 | * The size of one data cache line. | |
49 | */ | |
50 | #define CACHE_DLINESIZE 32 | |
51 | ||
52 | /* | |
53 | * The number of data cache segments. | |
54 | */ | |
55 | #define CACHE_DSEGMENTS 16 | |
56 | ||
57 | /* | |
58 | * The number of lines in a cache segment. | |
59 | */ | |
60 | #define CACHE_DENTRIES 64 | |
61 | ||
62 | /* | |
63 | * This is the size at which it becomes more efficient to | |
64 | * clean the whole cache, rather than using the individual | |
25985edc | 65 | * cache line maintenance instructions. |
1da177e4 LT |
66 | */ |
67 | #define CACHE_DLIMIT 32768 | |
68 | ||
69 | .text | |
70 | /* | |
71 | * cpu_arm1020_proc_init() | |
72 | */ | |
73 | ENTRY(cpu_arm1020_proc_init) | |
6ebbf2ce | 74 | ret lr |
1da177e4 LT |
75 | |
76 | /* | |
77 | * cpu_arm1020_proc_fin() | |
78 | */ | |
79 | ENTRY(cpu_arm1020_proc_fin) | |
1da177e4 LT |
80 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
81 | bic r0, r0, #0x1000 @ ...i............ | |
82 | bic r0, r0, #0x000e @ ............wca. | |
83 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
6ebbf2ce | 84 | ret lr |
1da177e4 LT |
85 | |
86 | /* | |
87 | * cpu_arm1020_reset(loc) | |
88 | * | |
89 | * Perform a soft reset of the system. Put the CPU into the | |
90 | * same state as it would be if it had been reset, and branch | |
91 | * to what would be the reset vector. | |
92 | * | |
93 | * loc: location to jump to for soft reset | |
94 | */ | |
95 | .align 5 | |
1a4baafa | 96 | .pushsection .idmap.text, "ax" |
1da177e4 LT |
97 | ENTRY(cpu_arm1020_reset) |
98 | mov ip, #0 | |
99 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | |
100 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
d090ddda | 101 | #ifdef CONFIG_MMU |
1da177e4 | 102 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
d090ddda | 103 | #endif |
1da177e4 LT |
104 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register |
105 | bic ip, ip, #0x000f @ ............wcam | |
106 | bic ip, ip, #0x1100 @ ...i...s........ | |
107 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | |
6ebbf2ce | 108 | ret r0 |
1a4baafa WD |
109 | ENDPROC(cpu_arm1020_reset) |
110 | .popsection | |
1da177e4 LT |
111 | |
112 | /* | |
113 | * cpu_arm1020_do_idle() | |
114 | */ | |
115 | .align 5 | |
116 | ENTRY(cpu_arm1020_do_idle) | |
117 | mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt | |
6ebbf2ce | 118 | ret lr |
1da177e4 LT |
119 | |
120 | /* ================================= CACHE ================================ */ | |
121 | ||
122 | .align 5 | |
c8c90860 MW |
123 | |
124 | /* | |
125 | * flush_icache_all() | |
126 | * | |
127 | * Unconditionally clean and invalidate the entire icache. | |
128 | */ | |
129 | ENTRY(arm1020_flush_icache_all) | |
130 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
131 | mov r0, #0 | |
132 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
133 | #endif | |
6ebbf2ce | 134 | ret lr |
c8c90860 MW |
135 | ENDPROC(arm1020_flush_icache_all) |
136 | ||
1da177e4 LT |
137 | /* |
138 | * flush_user_cache_all() | |
139 | * | |
140 | * Invalidate all cache entries in a particular address | |
141 | * space. | |
142 | */ | |
143 | ENTRY(arm1020_flush_user_cache_all) | |
144 | /* FALLTHROUGH */ | |
145 | /* | |
146 | * flush_kern_cache_all() | |
147 | * | |
148 | * Clean and invalidate the entire cache. | |
149 | */ | |
150 | ENTRY(arm1020_flush_kern_cache_all) | |
151 | mov r2, #VM_EXEC | |
152 | mov ip, #0 | |
153 | __flush_whole_cache: | |
154 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
155 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
156 | mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments | |
157 | 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries | |
158 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index | |
159 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
160 | subs r3, r3, #1 << 26 | |
161 | bcs 2b @ entries 63 to 0 | |
162 | subs r1, r1, #1 << 5 | |
163 | bcs 1b @ segments 15 to 0 | |
164 | #endif | |
165 | tst r2, #VM_EXEC | |
166 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
167 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
168 | #endif | |
169 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
6ebbf2ce | 170 | ret lr |
1da177e4 LT |
171 | |
172 | /* | |
173 | * flush_user_cache_range(start, end, flags) | |
174 | * | |
175 | * Invalidate a range of cache entries in the specified | |
176 | * address space. | |
177 | * | |
178 | * - start - start address (inclusive) | |
179 | * - end - end address (exclusive) | |
180 | * - flags - vm_flags for this space | |
181 | */ | |
182 | ENTRY(arm1020_flush_user_cache_range) | |
183 | mov ip, #0 | |
184 | sub r3, r1, r0 @ calculate total size | |
185 | cmp r3, #CACHE_DLIMIT | |
186 | bhs __flush_whole_cache | |
187 | ||
188 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
189 | mcr p15, 0, ip, c7, c10, 4 | |
190 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | |
191 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
192 | add r0, r0, #CACHE_DLINESIZE | |
193 | cmp r0, r1 | |
194 | blo 1b | |
195 | #endif | |
196 | tst r2, #VM_EXEC | |
197 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
198 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
199 | #endif | |
200 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
6ebbf2ce | 201 | ret lr |
1da177e4 LT |
202 | |
203 | /* | |
204 | * coherent_kern_range(start, end) | |
205 | * | |
206 | * Ensure coherency between the Icache and the Dcache in the | |
207 | * region described by start. If you have non-snooping | |
208 | * Harvard caches, you need to implement this function. | |
209 | * | |
210 | * - start - virtual start address | |
211 | * - end - virtual end address | |
212 | */ | |
213 | ENTRY(arm1020_coherent_kern_range) | |
214 | /* FALLTRHOUGH */ | |
215 | ||
216 | /* | |
217 | * coherent_user_range(start, end) | |
218 | * | |
219 | * Ensure coherency between the Icache and the Dcache in the | |
220 | * region described by start. If you have non-snooping | |
221 | * Harvard caches, you need to implement this function. | |
222 | * | |
223 | * - start - virtual start address | |
224 | * - end - virtual end address | |
225 | */ | |
226 | ENTRY(arm1020_coherent_user_range) | |
227 | mov ip, #0 | |
228 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
229 | mcr p15, 0, ip, c7, c10, 4 | |
230 | 1: | |
231 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
232 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
233 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
234 | #endif | |
235 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
236 | mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
237 | #endif | |
238 | add r0, r0, #CACHE_DLINESIZE | |
239 | cmp r0, r1 | |
240 | blo 1b | |
241 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
c5102f59 | 242 | mov r0, #0 |
6ebbf2ce | 243 | ret lr |
1da177e4 LT |
244 | |
245 | /* | |
2c9b9c84 | 246 | * flush_kern_dcache_area(void *addr, size_t size) |
1da177e4 LT |
247 | * |
248 | * Ensure no D cache aliasing occurs, either with itself or | |
249 | * the I cache | |
250 | * | |
2c9b9c84 RK |
251 | * - addr - kernel address |
252 | * - size - region size | |
1da177e4 | 253 | */ |
2c9b9c84 | 254 | ENTRY(arm1020_flush_kern_dcache_area) |
1da177e4 LT |
255 | mov ip, #0 |
256 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
2c9b9c84 | 257 | add r1, r0, r1 |
1da177e4 LT |
258 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
259 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
260 | add r0, r0, #CACHE_DLINESIZE | |
261 | cmp r0, r1 | |
262 | blo 1b | |
263 | #endif | |
264 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
6ebbf2ce | 265 | ret lr |
1da177e4 LT |
266 | |
267 | /* | |
268 | * dma_inv_range(start, end) | |
269 | * | |
270 | * Invalidate (discard) the specified virtual address range. | |
271 | * May not write back any entries. If 'start' or 'end' | |
272 | * are not cache line aligned, those lines must be written | |
273 | * back. | |
274 | * | |
275 | * - start - virtual start address | |
276 | * - end - virtual end address | |
277 | * | |
278 | * (same as v4wb) | |
279 | */ | |
702b94bf | 280 | arm1020_dma_inv_range: |
1da177e4 LT |
281 | mov ip, #0 |
282 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
283 | tst r0, #CACHE_DLINESIZE - 1 | |
284 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
285 | mcrne p15, 0, ip, c7, c10, 4 | |
286 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | |
287 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
288 | tst r1, #CACHE_DLINESIZE - 1 | |
289 | mcrne p15, 0, ip, c7, c10, 4 | |
290 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry | |
291 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
292 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | |
293 | add r0, r0, #CACHE_DLINESIZE | |
294 | cmp r0, r1 | |
295 | blo 1b | |
296 | #endif | |
297 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
6ebbf2ce | 298 | ret lr |
1da177e4 LT |
299 | |
300 | /* | |
301 | * dma_clean_range(start, end) | |
302 | * | |
303 | * Clean the specified virtual address range. | |
304 | * | |
305 | * - start - virtual start address | |
306 | * - end - virtual end address | |
307 | * | |
308 | * (same as v4wb) | |
309 | */ | |
702b94bf | 310 | arm1020_dma_clean_range: |
1da177e4 LT |
311 | mov ip, #0 |
312 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
313 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
314 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
315 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
316 | add r0, r0, #CACHE_DLINESIZE | |
317 | cmp r0, r1 | |
318 | blo 1b | |
319 | #endif | |
320 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
6ebbf2ce | 321 | ret lr |
1da177e4 LT |
322 | |
323 | /* | |
324 | * dma_flush_range(start, end) | |
325 | * | |
326 | * Clean and invalidate the specified virtual address range. | |
327 | * | |
328 | * - start - virtual start address | |
329 | * - end - virtual end address | |
330 | */ | |
331 | ENTRY(arm1020_dma_flush_range) | |
332 | mov ip, #0 | |
333 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
334 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
335 | mcr p15, 0, ip, c7, c10, 4 | |
336 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | |
337 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
338 | add r0, r0, #CACHE_DLINESIZE | |
339 | cmp r0, r1 | |
340 | blo 1b | |
341 | #endif | |
342 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
6ebbf2ce | 343 | ret lr |
1da177e4 | 344 | |
a9c9147e RK |
345 | /* |
346 | * dma_map_area(start, size, dir) | |
347 | * - start - kernel virtual start address | |
348 | * - size - size of region | |
349 | * - dir - DMA direction | |
350 | */ | |
351 | ENTRY(arm1020_dma_map_area) | |
352 | add r1, r1, r0 | |
353 | cmp r2, #DMA_TO_DEVICE | |
354 | beq arm1020_dma_clean_range | |
355 | bcs arm1020_dma_inv_range | |
356 | b arm1020_dma_flush_range | |
357 | ENDPROC(arm1020_dma_map_area) | |
358 | ||
359 | /* | |
360 | * dma_unmap_area(start, size, dir) | |
361 | * - start - kernel virtual start address | |
362 | * - size - size of region | |
363 | * - dir - DMA direction | |
364 | */ | |
365 | ENTRY(arm1020_dma_unmap_area) | |
6ebbf2ce | 366 | ret lr |
a9c9147e RK |
367 | ENDPROC(arm1020_dma_unmap_area) |
368 | ||
031bd879 LP |
369 | .globl arm1020_flush_kern_cache_louis |
370 | .equ arm1020_flush_kern_cache_louis, arm1020_flush_kern_cache_all | |
371 | ||
56d91650 DM |
372 | @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) |
373 | define_cache_functions arm1020 | |
1da177e4 LT |
374 | |
375 | .align 5 | |
376 | ENTRY(cpu_arm1020_dcache_clean_area) | |
377 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
378 | mov ip, #0 | |
379 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
380 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
381 | add r0, r0, #CACHE_DLINESIZE | |
382 | subs r1, r1, #CACHE_DLINESIZE | |
383 | bhi 1b | |
384 | #endif | |
6ebbf2ce | 385 | ret lr |
1da177e4 LT |
386 | |
387 | /* =============================== PageTable ============================== */ | |
388 | ||
389 | /* | |
390 | * cpu_arm1020_switch_mm(pgd) | |
391 | * | |
392 | * Set the translation base pointer to be as described by pgd. | |
393 | * | |
394 | * pgd: new page tables | |
395 | */ | |
396 | .align 5 | |
397 | ENTRY(cpu_arm1020_switch_mm) | |
d090ddda | 398 | #ifdef CONFIG_MMU |
1da177e4 LT |
399 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
400 | mcr p15, 0, r3, c7, c10, 4 | |
401 | mov r1, #0xF @ 16 segments | |
402 | 1: mov r3, #0x3F @ 64 entries | |
403 | 2: mov ip, r3, LSL #26 @ shift up entry | |
404 | orr ip, ip, r1, LSL #5 @ shift in/up index | |
405 | mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry | |
406 | mov ip, #0 | |
407 | mcr p15, 0, ip, c7, c10, 4 | |
408 | subs r3, r3, #1 | |
409 | cmp r3, #0 | |
410 | bge 2b @ entries 3F to 0 | |
411 | subs r1, r1, #1 | |
412 | cmp r1, #0 | |
413 | bge 1b @ segments 15 to 0 | |
414 | ||
415 | #endif | |
416 | mov r1, #0 | |
417 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
418 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache | |
419 | #endif | |
420 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
421 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer | |
422 | mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs | |
d090ddda | 423 | #endif /* CONFIG_MMU */ |
6ebbf2ce | 424 | ret lr |
1da177e4 LT |
425 | |
426 | /* | |
427 | * cpu_arm1020_set_pte(ptep, pte) | |
428 | * | |
429 | * Set a PTE and flush it out | |
430 | */ | |
431 | .align 5 | |
ad1ae2fe | 432 | ENTRY(cpu_arm1020_set_pte_ext) |
d090ddda | 433 | #ifdef CONFIG_MMU |
da091653 | 434 | armv3_set_pte_ext |
1da177e4 LT |
435 | mov r0, r0 |
436 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
437 | mcr p15, 0, r0, c7, c10, 4 | |
438 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
439 | #endif | |
440 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
d090ddda | 441 | #endif /* CONFIG_MMU */ |
6ebbf2ce | 442 | ret lr |
1da177e4 | 443 | |
1da177e4 LT |
444 | .type __arm1020_setup, #function |
445 | __arm1020_setup: | |
446 | mov r0, #0 | |
447 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 | |
448 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 | |
d090ddda | 449 | #ifdef CONFIG_MMU |
1da177e4 | 450 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 |
d090ddda | 451 | #endif |
22b19086 RK |
452 | |
453 | adr r5, arm1020_crval | |
454 | ldmia r5, {r5, r6} | |
1da177e4 | 455 | mrc p15, 0, r0, c1, c0 @ get control register v4 |
1da177e4 | 456 | bic r0, r0, r5 |
22b19086 | 457 | orr r0, r0, r6 |
1da177e4 LT |
458 | #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN |
459 | orr r0, r0, #0x4000 @ .R.. .... .... .... | |
460 | #endif | |
6ebbf2ce | 461 | ret lr |
1da177e4 LT |
462 | .size __arm1020_setup, . - __arm1020_setup |
463 | ||
464 | /* | |
465 | * R | |
466 | * .RVI ZFRS BLDP WCAM | |
abaf48a0 | 467 | * .011 1001 ..11 0101 |
1da177e4 | 468 | */ |
22b19086 RK |
469 | .type arm1020_crval, #object |
470 | arm1020_crval: | |
471 | crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930 | |
1da177e4 LT |
472 | |
473 | __INITDATA | |
56d91650 DM |
474 | @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
475 | define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort | |
1da177e4 | 476 | |
1da177e4 LT |
477 | |
478 | .section ".rodata" | |
479 | ||
56d91650 DM |
480 | string cpu_arch_name, "armv5t" |
481 | string cpu_elf_name, "v5" | |
1da177e4 LT |
482 | |
483 | .type cpu_arm1020_name, #object | |
484 | cpu_arm1020_name: | |
485 | .ascii "ARM1020" | |
486 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
487 | .ascii "i" | |
488 | #endif | |
489 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
490 | .ascii "d" | |
491 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
492 | .ascii "(wt)" | |
493 | #else | |
494 | .ascii "(wb)" | |
495 | #endif | |
496 | #endif | |
497 | #ifndef CONFIG_CPU_BPREDICT_DISABLE | |
498 | .ascii "B" | |
499 | #endif | |
500 | #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN | |
501 | .ascii "RR" | |
502 | #endif | |
503 | .ascii "\0" | |
504 | .size cpu_arm1020_name, . - cpu_arm1020_name | |
505 | ||
506 | .align | |
507 | ||
bf35706f | 508 | .section ".proc.info.init", #alloc |
1da177e4 LT |
509 | |
510 | .type __arm1020_proc_info,#object | |
511 | __arm1020_proc_info: | |
512 | .long 0x4104a200 @ ARM 1020T (Architecture v5T) | |
513 | .long 0xff0ffff0 | |
8799ee9f RK |
514 | .long PMD_TYPE_SECT | \ |
515 | PMD_SECT_AP_WRITE | \ | |
516 | PMD_SECT_AP_READ | |
1da177e4 LT |
517 | .long PMD_TYPE_SECT | \ |
518 | PMD_SECT_AP_WRITE | \ | |
519 | PMD_SECT_AP_READ | |
bf35706f | 520 | initfn __arm1020_setup, __arm1020_proc_info |
1da177e4 LT |
521 | .long cpu_arch_name |
522 | .long cpu_elf_name | |
523 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | |
524 | .long cpu_arm1020_name | |
525 | .long arm1020_processor_functions | |
526 | .long v4wbi_tlb_fns | |
527 | .long v4wb_user_fns | |
528 | .long arm1020_cache_fns | |
529 | .size __arm1020_proc_info, . - __arm1020_proc_info |