[linux-2.6-block.git] / arch / arm / mm / nommu.c

/*
 *  linux/arch/arm/mm/nommu.c
 *
 * ARM uCLinux supporting functions.
 */
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/pagemap.h>
#include <linux/io.h>
#include <linux/memblock.h>
#include <linux/kernel.h>

#include <asm/cacheflush.h>
#include <asm/sections.h>
#include <asm/page.h>
#include <asm/setup.h>
#include <asm/traps.h>
#include <asm/mach/arch.h>
#include <asm/cputype.h>
#include <asm/mpu.h>
#include <asm/procinfo.h>

#include "mm.h"

#ifdef CONFIG_ARM_MPU
struct mpu_rgn_info mpu_rgn_info;

/* Region number */
static void rgnr_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c2, 0" : : "r" (v));
}

/* Data-side / unified region attributes */

/* Region access control register */
static void dracr_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c1, 4" : : "r" (v));
}

/* Region size register */
static void drsr_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c1, 2" : : "r" (v));
}

/* Region base address register */
static void drbar_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c1, 0" : : "r" (v));
}

static u32 drbar_read(void)
{
	u32 v;
	asm("mrc        p15, 0, %0, c6, c1, 0" : "=r" (v));
	return v;
}
/* Optional instruction-side region attributes */

/* I-side Region access control register */
static void iracr_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c1, 5" : : "r" (v));
}

/* I-side Region size register */
static void irsr_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c1, 3" : : "r" (v));
}

/* I-side Region base address register */
static void irbar_write(u32 v)
{
	asm("mcr        p15, 0, %0, c6, c1, 1" : : "r" (v));
}

static unsigned long irbar_read(void)
{
	unsigned long v;
	asm("mrc        p15, 0, %0, c6, c1, 1" : "=r" (v));
	return v;
}

/* MPU initialisation functions */
void __init sanity_check_meminfo_mpu(void)
{
	int i;
	phys_addr_t phys_offset = PHYS_OFFSET;
	phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
	struct memblock_region *reg;
	bool first = true;
	phys_addr_t mem_start;
	phys_addr_t mem_end;

	for_each_memblock(memory, reg) {
		if (first) {
			/*
			 * Initially only use memory continuous from
			 * PHYS_OFFSET */
			if (reg->base != phys_offset)
				panic("First memory bank must be contiguous from PHYS_OFFSET");

			mem_start = reg->base;
			mem_end = reg->base + reg->size;
			specified_mem_size = reg->size;
			first = false;
		} else {
			/*
			 * memblock auto merges contiguous blocks, remove
			 * all blocks afterwards
			 */
			pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
				  &mem_start, &reg->base);
			memblock_remove(reg->base, reg->size);
		}
	}

	/*
	 * MPU has curious alignment requirements: Size must be power of 2, and
	 * region start must be aligned to the region size
	 */
	if (phys_offset != 0)
		pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");

	/*
	 * Maximum aligned region might overflow phys_addr_t if phys_offset is
	 * 0. Hence we keep everything below 4G until we take the smaller of
	 * the aligned_region_size and rounded_mem_size, one of which is
	 * guaranteed to be smaller than the maximum physical address.
	 */
	aligned_region_size = (phys_offset - 1) ^ (phys_offset);
	/* Find the max power-of-two sized region that fits inside our bank */
	rounded_mem_size = (1 <<  __fls(specified_mem_size)) - 1;

	/* The actual region size is the smaller of the two */
	aligned_region_size = aligned_region_size < rounded_mem_size
				? aligned_region_size + 1
				: rounded_mem_size + 1;

	if (aligned_region_size != specified_mem_size) {
		pr_warn("Truncating memory from %pa to %pa (MPU region constraints)",
				&specified_mem_size, &aligned_region_size);
		memblock_remove(mem_start + aligned_region_size,
				specified_mem_size - aligned_round_size);

		mem_end = mem_start + aligned_region_size;
	}

	pr_debug("MPU Region from %pa size %pa (end %pa))\n",
		&phys_offset, &aligned_region_size, &mem_end);

}

static int mpu_present(void)
{
	return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
}

static int mpu_max_regions(void)
{
	/*
	 * We don't support a different number of I/D side regions so if we
	 * have separate instruction and data memory maps then return
	 * whichever side has a smaller number of supported regions.
	 */
	u32 dregions, iregions, mpuir;
	mpuir = read_cpuid(CPUID_MPUIR);

	dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;

	/* Check for separate d-side and i-side memory maps */
	if (mpuir & MPUIR_nU)
		iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;

	/* Use the smallest of the two maxima */
	return min(dregions, iregions);
}

static int mpu_iside_independent(void)
{
	/* MPUIR.nU specifies whether there is *not* a unified memory map */
	return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
}

static int mpu_min_region_order(void)
{
	u32 drbar_result, irbar_result;
	/* We've kept a region free for this probing */
	rgnr_write(MPU_PROBE_REGION);
	isb();
	/*
	 * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
	 * region order
	*/
	drbar_write(0xFFFFFFFC);
	drbar_result = irbar_result = drbar_read();
	drbar_write(0x0);
	/* If the MPU is non-unified, we use the larger of the two minima*/
	if (mpu_iside_independent()) {
		irbar_write(0xFFFFFFFC);
		irbar_result = irbar_read();
		irbar_write(0x0);
	}
	isb(); /* Ensure that MPU region operations have completed */
	/* Return whichever result is larger */
	return __ffs(max(drbar_result, irbar_result));
}

static int mpu_setup_region(unsigned int number, phys_addr_t start,
			unsigned int size_order, unsigned int properties)
{
	u32 size_data;

	/* We kept a region free for probing resolution of MPU regions*/
	if (number > mpu_max_regions() || number == MPU_PROBE_REGION)
		return -ENOENT;

	if (size_order > 32)
		return -ENOMEM;

	if (size_order < mpu_min_region_order())
		return -ENOMEM;

	/* Writing N to bits 5:1 (RSR_SZ)  specifies region size 2^N+1 */
	size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN;

	dsb(); /* Ensure all previous data accesses occur with old mappings */
	rgnr_write(number);
	isb();
	drbar_write(start);
	dracr_write(properties);
	isb(); /* Propagate properties before enabling region */
	drsr_write(size_data);

	/* Check for independent I-side registers */
	if (mpu_iside_independent()) {
		irbar_write(start);
		iracr_write(properties);
		isb();
		irsr_write(size_data);
	}
	isb();

	/* Store region info (we treat i/d side the same, so only store d) */
	mpu_rgn_info.rgns[number].dracr = properties;
	mpu_rgn_info.rgns[number].drbar = start;
	mpu_rgn_info.rgns[number].drsr = size_data;
	return 0;
}

/*
* Set up default MPU regions, doing nothing if there is no MPU
*/
void __init mpu_setup(void)
{
	int region_err;
	if (!mpu_present())
		return;

	region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
					ilog2(meminfo.bank[0].size),
					MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
	if (region_err) {
		panic("MPU region initialization failure! %d", region_err);
	} else {
		pr_info("Using ARMv7 PMSA Compliant MPU. "
			 "Region independence: %s, Max regions: %d\n",
			mpu_iside_independent() ? "Yes" : "No",
			mpu_max_regions());
	}
}
#else
static void sanity_check_meminfo_mpu(void) {}
static void __init mpu_setup(void) {}
#endif /* CONFIG_ARM_MPU */

void __init arm_mm_memblock_reserve(void)
{
#ifndef CONFIG_CPU_V7M
	/*
	 * Register the exception vector page.
	 * some architectures which the DRAM is the exception vector to trap,
	 * alloc_page breaks with error, although it is not NULL, but "0."
	 */
	memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
#else /* ifndef CONFIG_CPU_V7M */
	/*
	 * There is no dedicated vector page on V7-M. So nothing needs to be
	 * reserved here.
	 */
#endif
}

void __init sanity_check_meminfo(void)
{
	phys_addr_t end;
	sanity_check_meminfo_mpu();
	end = memblock_end_of_DRAM();
	high_memory = __va(end - 1) + 1;
	memblock_set_current_limit(end);
}

/*
 * early_paging_init() recreates boot time page table setup, allowing machines
 * to switch over to a high (>4G) address space on LPAE systems
 */
void __init early_paging_init(const struct machine_desc *mdesc,
			      struct proc_info_list *procinfo)
{
}

/*
 * paging_init() sets up the page tables, initialises the zone memory
 * maps, and sets up the zero page, bad page and bad page tables.
 */
void __init paging_init(const struct machine_desc *mdesc)
{
	early_trap_init((void *)CONFIG_VECTORS_BASE);
	mpu_setup();
	bootmem_init();
}

/*
 * We don't need to do anything here for nommu machines.
 */
void setup_mm_for_reboot(void)
{
}

void flush_dcache_page(struct page *page)
{
	__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
}
EXPORT_SYMBOL(flush_dcache_page);

void flush_kernel_dcache_page(struct page *page)
{
	__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
}
EXPORT_SYMBOL(flush_kernel_dcache_page);

void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
		       unsigned long uaddr, void *dst, const void *src,
		       unsigned long len)
{
	memcpy(dst, src, len);
	if (vma->vm_flags & VM_EXEC)
		__cpuc_coherent_user_range(uaddr, uaddr + len);
}

void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
				size_t size, unsigned int mtype)
{
	if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
		return NULL;
	return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
}
EXPORT_SYMBOL(__arm_ioremap_pfn);

void __iomem *__arm_ioremap_pfn_caller(unsigned long pfn, unsigned long offset,
			   size_t size, unsigned int mtype, void *caller)
{
	return __arm_ioremap_pfn(pfn, offset, size, mtype);
}

void __iomem *__arm_ioremap(phys_addr_t phys_addr, size_t size,
			    unsigned int mtype)
{
	return (void __iomem *)phys_addr;
}
EXPORT_SYMBOL(__arm_ioremap);

void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);

void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
				   unsigned int mtype, void *caller)
{
	return __arm_ioremap(phys_addr, size, mtype);
}

void (*arch_iounmap)(volatile void __iomem *);

void __arm_iounmap(volatile void __iomem *addr)
{
}
EXPORT_SYMBOL(__arm_iounmap);
Commit	Line	Data
5924486d RK	1	/*
	2	* linux/arch/arm/mm/nommu.c
	3	*
	4	* ARM uCLinux supporting functions.
	5	*/
	6	#include <linux/module.h>
e6b1b38c RK	7	#include <linux/mm.h>
e6b1b38c RK	8	#include <linux/pagemap.h>
fced80c7	9	#include <linux/io.h>
2778f620	10	#include <linux/memblock.h>
5ad7dcbe	11	#include <linux/kernel.h>
5924486d	12
e6b1b38c	13	#include <asm/cacheflush.h>
37efe642	14	#include <asm/sections.h>
5924486d	15	#include <asm/page.h>
b32f3afe	16	#include <asm/setup.h>
6b8e5c91	17	#include <asm/traps.h>
3ff1559e	18	#include <asm/mach/arch.h>
5ad7dcbe JA	19	#include <asm/cputype.h>
5ad7dcbe JA	20	#include <asm/mpu.h>
83651bb9	21	#include <asm/procinfo.h>
5924486d	22
d111e8f9 RK	23	#include "mm.h"
d111e8f9 RK	24
5ad7dcbe JA	25	#ifdef CONFIG_ARM_MPU
	26	struct mpu_rgn_info mpu_rgn_info;
	27
	28	/* Region number */
	29	static void rgnr_write(u32 v)
	30	{
	31	asm("mcr p15, 0, %0, c6, c2, 0" : : "r" (v));
	32	}
	33
	34	/* Data-side / unified region attributes */
	35
	36	/* Region access control register */
	37	static void dracr_write(u32 v)
	38	{
	39	asm("mcr p15, 0, %0, c6, c1, 4" : : "r" (v));
	40	}
	41
	42	/* Region size register */
	43	static void drsr_write(u32 v)
	44	{
	45	asm("mcr p15, 0, %0, c6, c1, 2" : : "r" (v));
	46	}
	47
	48	/* Region base address register */
	49	static void drbar_write(u32 v)
	50	{
	51	asm("mcr p15, 0, %0, c6, c1, 0" : : "r" (v));
	52	}
	53
	54	static u32 drbar_read(void)
	55	{
	56	u32 v;
	57	asm("mrc p15, 0, %0, c6, c1, 0" : "=r" (v));
	58	return v;
	59	}
	60	/* Optional instruction-side region attributes */
	61
	62	/* I-side Region access control register */
	63	static void iracr_write(u32 v)
	64	{
	65	asm("mcr p15, 0, %0, c6, c1, 5" : : "r" (v));
	66	}
	67
	68	/* I-side Region size register */
	69	static void irsr_write(u32 v)
	70	{
	71	asm("mcr p15, 0, %0, c6, c1, 3" : : "r" (v));
	72	}
	73
	74	/* I-side Region base address register */
	75	static void irbar_write(u32 v)
	76	{
	77	asm("mcr p15, 0, %0, c6, c1, 1" : : "r" (v));
	78	}
	79
	80	static unsigned long irbar_read(void)
	81	{
	82	unsigned long v;
	83	asm("mrc p15, 0, %0, c6, c1, 1" : "=r" (v));
	84	return v;
	85	}
	86
	87	/* MPU initialisation functions */
	88	void __init sanity_check_meminfo_mpu(void)
89	{
90	int i;
5ad7dcbe JA	91	phys_addr_t phys_offset = PHYS_OFFSET;
5ad7dcbe JA	92	phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
1c2f87c2 LA	93	struct memblock_region *reg;
	94	bool first = true;
	95	phys_addr_t mem_start;
	96	phys_addr_t mem_end;
	97
	98	for_each_memblock(memory, reg) {
	99	if (first) {
	100	/*
	101	* Initially only use memory continuous from
	102	* PHYS_OFFSET */
	103	if (reg->base != phys_offset)
	104	panic("First memory bank must be contiguous from PHYS_OFFSET");
	105
	106	mem_start = reg->base;
	107	mem_end = reg->base + reg->size;
	108	specified_mem_size = reg->size;
	109	first = false;
5ad7dcbe	110	} else {
1c2f87c2 LA	111	/*
	112	* memblock auto merges contiguous blocks, remove
	113	* all blocks afterwards
	114	*/
	115	pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
	116	&mem_start, &reg->base);
	117	memblock_remove(reg->base, reg->size);
5ad7dcbe JA	118	}
5ad7dcbe JA	119	}
5ad7dcbe JA	120
	121	/*
	122	* MPU has curious alignment requirements: Size must be power of 2, and
	123	* region start must be aligned to the region size
	124	*/
	125	if (phys_offset != 0)
	126	pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
	127
	128	/*
	129	* Maximum aligned region might overflow phys_addr_t if phys_offset is
	130	* 0. Hence we keep everything below 4G until we take the smaller of
	131	* the aligned_region_size and rounded_mem_size, one of which is
	132	* guaranteed to be smaller than the maximum physical address.
	133	*/
	134	aligned_region_size = (phys_offset - 1) ^ (phys_offset);
	135	/* Find the max power-of-two sized region that fits inside our bank */
1c2f87c2	136	rounded_mem_size = (1 << __fls(specified_mem_size)) - 1;
5ad7dcbe JA	137
	138	/* The actual region size is the smaller of the two */
	139	aligned_region_size = aligned_region_size < rounded_mem_size
	140	? aligned_region_size + 1
	141	: rounded_mem_size + 1;
	142
1c2f87c2 LA	143	if (aligned_region_size != specified_mem_size) {
	144	pr_warn("Truncating memory from %pa to %pa (MPU region constraints)",
	145	&specified_mem_size, &aligned_region_size);
	146	memblock_remove(mem_start + aligned_region_size,
	147	specified_mem_size - aligned_round_size);
	148
	149	mem_end = mem_start + aligned_region_size;
	150	}
5ad7dcbe	151
1c2f87c2 LA	152	pr_debug("MPU Region from %pa size %pa (end %pa))\n",
1c2f87c2 LA	153	&phys_offset, &aligned_region_size, &mem_end);
5ad7dcbe JA	154
	155	}
	156
	157	static int mpu_present(void)
	158	{
	159	return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
	160	}
	161
	162	static int mpu_max_regions(void)
	163	{
	164	/*
	165	* We don't support a different number of I/D side regions so if we
	166	* have separate instruction and data memory maps then return
	167	* whichever side has a smaller number of supported regions.
	168	*/
	169	u32 dregions, iregions, mpuir;
	170	mpuir = read_cpuid(CPUID_MPUIR);
	171
	172	dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
	173
	174	/* Check for separate d-side and i-side memory maps */
	175	if (mpuir & MPUIR_nU)
	176	iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
	177
	178	/* Use the smallest of the two maxima */
	179	return min(dregions, iregions);
	180	}
	181
	182	static int mpu_iside_independent(void)
	183	{
	184	/* MPUIR.nU specifies whether there is not a unified memory map */
	185	return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
	186	}
	187
	188	static int mpu_min_region_order(void)
	189	{
	190	u32 drbar_result, irbar_result;
	191	/* We've kept a region free for this probing */
	192	rgnr_write(MPU_PROBE_REGION);
	193	isb();
	194	/*
	195	* As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
	196	* region order
	197	*/
	198	drbar_write(0xFFFFFFFC);
	199	drbar_result = irbar_result = drbar_read();
	200	drbar_write(0x0);
	201	/* If the MPU is non-unified, we use the larger of the two minima*/
	202	if (mpu_iside_independent()) {
	203	irbar_write(0xFFFFFFFC);
	204	irbar_result = irbar_read();
	205	irbar_write(0x0);
	206	}
	207	isb(); /* Ensure that MPU region operations have completed */
	208	/* Return whichever result is larger */
	209	return __ffs(max(drbar_result, irbar_result));
	210	}
	211
	212	static int mpu_setup_region(unsigned int number, phys_addr_t start,
	213	unsigned int size_order, unsigned int properties)
	214	{
	215	u32 size_data;
	216
	217	/* We kept a region free for probing resolution of MPU regions*/
218	if (number > mpu_max_regions() \|\| number == MPU_PROBE_REGION)
219	return -ENOENT;
220
221	if (size_order > 32)
222	return -ENOMEM;
223
224	if (size_order < mpu_min_region_order())
225	return -ENOMEM;
226
227	/* Writing N to bits 5:1 (RSR_SZ) specifies region size 2^N+1 */
228	size_data = ((size_order - 1) << MPU_RSR_SZ) \| 1 << MPU_RSR_EN;
229
230	dsb(); /* Ensure all previous data accesses occur with old mappings */
231	rgnr_write(number);
232	isb();
233	drbar_write(start);
234	dracr_write(properties);
235	isb(); /* Propagate properties before enabling region */
236	drsr_write(size_data);
237
238	/* Check for independent I-side registers */
239	if (mpu_iside_independent()) {
240	irbar_write(start);
241	iracr_write(properties);
242	isb();
243	irsr_write(size_data);
244	}
245	isb();
246
247	/* Store region info (we treat i/d side the same, so only store d) */
248	mpu_rgn_info.rgns[number].dracr = properties;
249	mpu_rgn_info.rgns[number].drbar = start;
250	mpu_rgn_info.rgns[number].drsr = size_data;
251	return 0;
252	}
253
254	/*
255	* Set up default MPU regions, doing nothing if there is no MPU
256	*/
257	void __init mpu_setup(void)
258	{
259	int region_err;
260	if (!mpu_present())
261	return;
262
263	region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
264	ilog2(meminfo.bank[0].size),
265	MPU_AP_PL1RW_PL0RW \| MPU_RGN_NORMAL);
266	if (region_err) {
267	panic("MPU region initialization failure! %d", region_err);
268	} else {
269	pr_info("Using ARMv7 PMSA Compliant MPU. "
270	"Region independence: %s, Max regions: %d\n",
271	mpu_iside_independent() ? "Yes" : "No",
272	mpu_max_regions());
273	}
274	}
9a271567 JA	275	#else
	276	static void sanity_check_meminfo_mpu(void) {}
	277	static void __init mpu_setup(void) {}
5ad7dcbe JA	278	#endif /* CONFIG_ARM_MPU */
5ad7dcbe JA	279
2778f620	280	void __init arm_mm_memblock_reserve(void)
d111e8f9	281	{
55bdd694	282	#ifndef CONFIG_CPU_V7M
d111e8f9 RK	283	/*
	284	* Register the exception vector page.
	285	* some architectures which the DRAM is the exception vector to trap,
	286	* alloc_page breaks with error, although it is not NULL, but "0."
	287	*/
2778f620	288	memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
55bdd694 CM	289	#else /* ifndef CONFIG_CPU_V7M */
	290	/*
	291	* There is no dedicated vector page on V7-M. So nothing needs to be
	292	* reserved here.
	293	*/
	294	#endif
d111e8f9 RK	295	}
d111e8f9 RK	296
0371d3f7 RK	297	void __init sanity_check_meminfo(void)
0371d3f7 RK	298	{
9a271567 JA	299	phys_addr_t end;
9a271567 JA	300	sanity_check_meminfo_mpu();
1c2f87c2	301	end = memblock_end_of_DRAM();
55a8173c	302	high_memory = __va(end - 1) + 1;
6980c3e2	303	memblock_set_current_limit(end);
0371d3f7 RK	304	}
0371d3f7 RK	305
70d42126 TR	306	/*
	307	* early_paging_init() recreates boot time page table setup, allowing machines
	308	* to switch over to a high (>4G) address space on LPAE systems
	309	*/
	310	void __init early_paging_init(const struct machine_desc *mdesc,
	311	struct proc_info_list *procinfo)
	312	{
	313	}
	314
d111e8f9 RK	315	/*
	316	* paging_init() sets up the page tables, initialises the zone memory
	317	* maps, and sets up the zero page, bad page and bad page tables.
	318	*/
ff69a4c8	319	void __init paging_init(const struct machine_desc *mdesc)
d111e8f9	320	{
6b8e5c91	321	early_trap_init((void *)CONFIG_VECTORS_BASE);
9a271567	322	mpu_setup();
8d717a52	323	bootmem_init();
d111e8f9 RK	324	}
d111e8f9 RK	325
80878d6c RK	326	/*
	327	* We don't need to do anything here for nommu machines.
	328	*/
5aafec15	329	void setup_mm_for_reboot(void)
80878d6c RK	330	{
	331	}
	332
e6b1b38c RK	333	void flush_dcache_page(struct page *page)
e6b1b38c RK	334	{
2c9b9c84	335	__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
e6b1b38c	336	}
3e361225	337	EXPORT_SYMBOL(flush_dcache_page);
e6b1b38c	338
63384fd0 SB	339	void flush_kernel_dcache_page(struct page *page)
	340	{
	341	__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
	342	}
	343	EXPORT_SYMBOL(flush_kernel_dcache_page);
	344
b5a07faa CM	345	void copy_to_user_page(struct vm_area_struct vma, struct page page,
	346	unsigned long uaddr, void dst, const void src,
	347	unsigned long len)
	348	{
	349	memcpy(dst, src, len);
	350	if (vma->vm_flags & VM_EXEC)
	351	__cpuc_coherent_user_range(uaddr, uaddr + len);
	352	}
	353
3603ab2b RK	354	void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
3603ab2b RK	355	size_t size, unsigned int mtype)
5924486d RK	356	{
	357	if (pfn >= (0x100000000ULL >> PAGE_SHIFT))
	358	return NULL;
	359	return (void __iomem *) (offset + (pfn << PAGE_SHIFT));
	360	}
3603ab2b	361	EXPORT_SYMBOL(__arm_ioremap_pfn);
5924486d	362
31aa8fd6 RK	363	void __iomem *__arm_ioremap_pfn_caller(unsigned long pfn, unsigned long offset,
	364	size_t size, unsigned int mtype, void *caller)
	365	{
	366	return __arm_ioremap_pfn(pfn, offset, size, mtype);
	367	}
	368
9b97173e	369	void __iomem *__arm_ioremap(phys_addr_t phys_addr, size_t size,
3603ab2b	370	unsigned int mtype)
5924486d RK	371	{
	372	return (void __iomem *)phys_addr;
	373	}
3603ab2b	374	EXPORT_SYMBOL(__arm_ioremap);
5924486d	375
9b97173e	376	void __iomem * (arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void );
8a2b6255	377
9b97173e	378	void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
b1a9ceb2	379	unsigned int mtype, void *caller)
31aa8fd6 RK	380	{
	381	return __arm_ioremap(phys_addr, size, mtype);
	382	}
	383
8a2b6255 RH	384	void (arch_iounmap)(volatile void __iomem );
	385
	386	void __arm_iounmap(volatile void __iomem *addr)
5924486d RK	387	{
5924486d RK	388	}
8a2b6255	389	EXPORT_SYMBOL(__arm_iounmap);