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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d111e8f9 RK |
2 | /* |
3 | * linux/arch/arm/mm/mmu.c | |
4 | * | |
5 | * Copyright (C) 1995-2005 Russell King | |
d111e8f9 | 6 | */ |
ae8f1541 | 7 | #include <linux/module.h> |
d111e8f9 RK |
8 | #include <linux/kernel.h> |
9 | #include <linux/errno.h> | |
10 | #include <linux/init.h> | |
d111e8f9 RK |
11 | #include <linux/mman.h> |
12 | #include <linux/nodemask.h> | |
2778f620 | 13 | #include <linux/memblock.h> |
d907387c | 14 | #include <linux/fs.h> |
0536bdf3 | 15 | #include <linux/vmalloc.h> |
158e8bfe | 16 | #include <linux/sizes.h> |
d111e8f9 | 17 | |
15d07dc9 | 18 | #include <asm/cp15.h> |
0ba8b9b2 | 19 | #include <asm/cputype.h> |
3f973e22 | 20 | #include <asm/cachetype.h> |
ebd4922e | 21 | #include <asm/sections.h> |
d111e8f9 | 22 | #include <asm/setup.h> |
e616c591 | 23 | #include <asm/smp_plat.h> |
aecc83e5 | 24 | #include <asm/tcm.h> |
d111e8f9 | 25 | #include <asm/tlb.h> |
d73cd428 | 26 | #include <asm/highmem.h> |
9f97da78 | 27 | #include <asm/system_info.h> |
247055aa | 28 | #include <asm/traps.h> |
a77e0c7b | 29 | #include <asm/procinfo.h> |
a9ff6961 | 30 | #include <asm/page.h> |
ca15ca40 | 31 | #include <asm/pgalloc.h> |
c12366ba | 32 | #include <asm/kasan_def.h> |
d111e8f9 RK |
33 | |
34 | #include <asm/mach/arch.h> | |
35 | #include <asm/mach/map.h> | |
c2794437 | 36 | #include <asm/mach/pci.h> |
a05e54c1 | 37 | #include <asm/fixmap.h> |
d111e8f9 | 38 | |
9254970c | 39 | #include "fault.h" |
d111e8f9 RK |
40 | #include "mm.h" |
41 | ||
7a1be318 AB |
42 | extern unsigned long __atags_pointer; |
43 | ||
d111e8f9 RK |
44 | /* |
45 | * empty_zero_page is a special page that is used for | |
46 | * zero-initialized data and COW. | |
47 | */ | |
48 | struct page *empty_zero_page; | |
3653f3ab | 49 | EXPORT_SYMBOL(empty_zero_page); |
d111e8f9 RK |
50 | |
51 | /* | |
52 | * The pmd table for the upper-most set of pages. | |
53 | */ | |
54 | pmd_t *top_pmd; | |
55 | ||
1d4d3715 JL |
56 | pmdval_t user_pmd_table = _PAGE_USER_TABLE; |
57 | ||
ae8f1541 RK |
58 | #define CPOLICY_UNCACHED 0 |
59 | #define CPOLICY_BUFFERED 1 | |
60 | #define CPOLICY_WRITETHROUGH 2 | |
61 | #define CPOLICY_WRITEBACK 3 | |
62 | #define CPOLICY_WRITEALLOC 4 | |
63 | ||
64 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; | |
65 | static unsigned int ecc_mask __initdata = 0; | |
44b18693 | 66 | pgprot_t pgprot_user; |
ae8f1541 RK |
67 | pgprot_t pgprot_kernel; |
68 | ||
44b18693 | 69 | EXPORT_SYMBOL(pgprot_user); |
ae8f1541 RK |
70 | EXPORT_SYMBOL(pgprot_kernel); |
71 | ||
72 | struct cachepolicy { | |
73 | const char policy[16]; | |
74 | unsigned int cr_mask; | |
442e70c0 | 75 | pmdval_t pmd; |
f6e3354d | 76 | pteval_t pte; |
ae8f1541 RK |
77 | }; |
78 | ||
79 | static struct cachepolicy cache_policies[] __initdata = { | |
80 | { | |
81 | .policy = "uncached", | |
82 | .cr_mask = CR_W|CR_C, | |
83 | .pmd = PMD_SECT_UNCACHED, | |
bb30f36f | 84 | .pte = L_PTE_MT_UNCACHED, |
ae8f1541 RK |
85 | }, { |
86 | .policy = "buffered", | |
87 | .cr_mask = CR_C, | |
88 | .pmd = PMD_SECT_BUFFERED, | |
bb30f36f | 89 | .pte = L_PTE_MT_BUFFERABLE, |
ae8f1541 RK |
90 | }, { |
91 | .policy = "writethrough", | |
92 | .cr_mask = 0, | |
93 | .pmd = PMD_SECT_WT, | |
bb30f36f | 94 | .pte = L_PTE_MT_WRITETHROUGH, |
ae8f1541 RK |
95 | }, { |
96 | .policy = "writeback", | |
97 | .cr_mask = 0, | |
98 | .pmd = PMD_SECT_WB, | |
bb30f36f | 99 | .pte = L_PTE_MT_WRITEBACK, |
ae8f1541 RK |
100 | }, { |
101 | .policy = "writealloc", | |
102 | .cr_mask = 0, | |
103 | .pmd = PMD_SECT_WBWA, | |
bb30f36f | 104 | .pte = L_PTE_MT_WRITEALLOC, |
ae8f1541 RK |
105 | } |
106 | }; | |
107 | ||
b849a60e | 108 | #ifdef CONFIG_CPU_CP15 |
20e7e364 RK |
109 | static unsigned long initial_pmd_value __initdata = 0; |
110 | ||
ae8f1541 | 111 | /* |
ca8f0b0a RK |
112 | * Initialise the cache_policy variable with the initial state specified |
113 | * via the "pmd" value. This is used to ensure that on ARMv6 and later, | |
114 | * the C code sets the page tables up with the same policy as the head | |
115 | * assembly code, which avoids an illegal state where the TLBs can get | |
116 | * confused. See comments in early_cachepolicy() for more information. | |
ae8f1541 | 117 | */ |
ca8f0b0a | 118 | void __init init_default_cache_policy(unsigned long pmd) |
ae8f1541 RK |
119 | { |
120 | int i; | |
121 | ||
20e7e364 RK |
122 | initial_pmd_value = pmd; |
123 | ||
6b3142b2 | 124 | pmd &= PMD_SECT_CACHE_MASK; |
ca8f0b0a RK |
125 | |
126 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) | |
127 | if (cache_policies[i].pmd == pmd) { | |
128 | cachepolicy = i; | |
129 | break; | |
130 | } | |
131 | ||
132 | if (i == ARRAY_SIZE(cache_policies)) | |
133 | pr_err("ERROR: could not find cache policy\n"); | |
134 | } | |
135 | ||
136 | /* | |
137 | * These are useful for identifying cache coherency problems by allowing | |
138 | * the cache or the cache and writebuffer to be turned off. (Note: the | |
139 | * write buffer should not be on and the cache off). | |
140 | */ | |
141 | static int __init early_cachepolicy(char *p) | |
142 | { | |
143 | int i, selected = -1; | |
144 | ||
ae8f1541 RK |
145 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { |
146 | int len = strlen(cache_policies[i].policy); | |
147 | ||
2b0d8c25 | 148 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
ca8f0b0a | 149 | selected = i; |
ae8f1541 RK |
150 | break; |
151 | } | |
152 | } | |
ca8f0b0a RK |
153 | |
154 | if (selected == -1) | |
155 | pr_err("ERROR: unknown or unsupported cache policy\n"); | |
156 | ||
4b46d641 RK |
157 | /* |
158 | * This restriction is partly to do with the way we boot; it is | |
159 | * unpredictable to have memory mapped using two different sets of | |
160 | * memory attributes (shared, type, and cache attribs). We can not | |
161 | * change these attributes once the initial assembly has setup the | |
162 | * page tables. | |
163 | */ | |
ca8f0b0a RK |
164 | if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) { |
165 | pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n", | |
166 | cache_policies[cachepolicy].policy); | |
167 | return 0; | |
168 | } | |
169 | ||
170 | if (selected != cachepolicy) { | |
171 | unsigned long cr = __clear_cr(cache_policies[selected].cr_mask); | |
172 | cachepolicy = selected; | |
173 | flush_cache_all(); | |
174 | set_cr(cr); | |
11179d8c | 175 | } |
2b0d8c25 | 176 | return 0; |
ae8f1541 | 177 | } |
2b0d8c25 | 178 | early_param("cachepolicy", early_cachepolicy); |
ae8f1541 | 179 | |
2b0d8c25 | 180 | static int __init early_nocache(char *__unused) |
ae8f1541 RK |
181 | { |
182 | char *p = "buffered"; | |
4ed89f22 | 183 | pr_warn("nocache is deprecated; use cachepolicy=%s\n", p); |
2b0d8c25 JK |
184 | early_cachepolicy(p); |
185 | return 0; | |
ae8f1541 | 186 | } |
2b0d8c25 | 187 | early_param("nocache", early_nocache); |
ae8f1541 | 188 | |
2b0d8c25 | 189 | static int __init early_nowrite(char *__unused) |
ae8f1541 RK |
190 | { |
191 | char *p = "uncached"; | |
4ed89f22 | 192 | pr_warn("nowb is deprecated; use cachepolicy=%s\n", p); |
2b0d8c25 JK |
193 | early_cachepolicy(p); |
194 | return 0; | |
ae8f1541 | 195 | } |
2b0d8c25 | 196 | early_param("nowb", early_nowrite); |
ae8f1541 | 197 | |
1b6ba46b | 198 | #ifndef CONFIG_ARM_LPAE |
2b0d8c25 | 199 | static int __init early_ecc(char *p) |
ae8f1541 | 200 | { |
2b0d8c25 | 201 | if (memcmp(p, "on", 2) == 0) |
ae8f1541 | 202 | ecc_mask = PMD_PROTECTION; |
2b0d8c25 | 203 | else if (memcmp(p, "off", 3) == 0) |
ae8f1541 | 204 | ecc_mask = 0; |
2b0d8c25 | 205 | return 0; |
ae8f1541 | 206 | } |
2b0d8c25 | 207 | early_param("ecc", early_ecc); |
1b6ba46b | 208 | #endif |
ae8f1541 | 209 | |
b849a60e UKK |
210 | #else /* ifdef CONFIG_CPU_CP15 */ |
211 | ||
212 | static int __init early_cachepolicy(char *p) | |
213 | { | |
8b521cb2 | 214 | pr_warn("cachepolicy kernel parameter not supported without cp15\n"); |
7b83299e | 215 | return 0; |
b849a60e UKK |
216 | } |
217 | early_param("cachepolicy", early_cachepolicy); | |
218 | ||
219 | static int __init noalign_setup(char *__unused) | |
220 | { | |
8b521cb2 | 221 | pr_warn("noalign kernel parameter not supported without cp15\n"); |
7b83299e | 222 | return 1; |
b849a60e UKK |
223 | } |
224 | __setup("noalign", noalign_setup); | |
225 | ||
226 | #endif /* ifdef CONFIG_CPU_CP15 / else */ | |
227 | ||
36bb94ba | 228 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN |
4d9c5b89 | 229 | #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE |
b1cce6b1 | 230 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
0af92bef | 231 | |
7619751f | 232 | static struct mem_type mem_types[] __ro_after_init = { |
0af92bef | 233 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
bb30f36f RK |
234 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
235 | L_PTE_SHARED, | |
0af92bef | 236 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 237 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
0af92bef RK |
238 | .domain = DOMAIN_IO, |
239 | }, | |
240 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ | |
bb30f36f | 241 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
0af92bef | 242 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 243 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef RK |
244 | .domain = DOMAIN_IO, |
245 | }, | |
6a22d824 | 246 | [MT_DEVICE_CACHED] = { /* ioremap_cache */ |
bb30f36f | 247 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
0af92bef RK |
248 | .prot_l1 = PMD_TYPE_TABLE, |
249 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, | |
250 | .domain = DOMAIN_IO, | |
c2794437 | 251 | }, |
1ad77a87 | 252 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
bb30f36f | 253 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
0af92bef | 254 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 255 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef | 256 | .domain = DOMAIN_IO, |
ae8f1541 | 257 | }, |
ebb4c658 RK |
258 | [MT_UNCACHED] = { |
259 | .prot_pte = PROT_PTE_DEVICE, | |
260 | .prot_l1 = PMD_TYPE_TABLE, | |
261 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
262 | .domain = DOMAIN_IO, | |
263 | }, | |
ae8f1541 | 264 | [MT_CACHECLEAN] = { |
9ef79635 | 265 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
ae8f1541 RK |
266 | .domain = DOMAIN_KERNEL, |
267 | }, | |
1b6ba46b | 268 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 | 269 | [MT_MINICLEAN] = { |
9ef79635 | 270 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
ae8f1541 RK |
271 | .domain = DOMAIN_KERNEL, |
272 | }, | |
1b6ba46b | 273 | #endif |
ae8f1541 RK |
274 | [MT_LOW_VECTORS] = { |
275 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 276 | L_PTE_RDONLY, |
ae8f1541 | 277 | .prot_l1 = PMD_TYPE_TABLE, |
a02d8dfd | 278 | .domain = DOMAIN_VECTORS, |
ae8f1541 RK |
279 | }, |
280 | [MT_HIGH_VECTORS] = { | |
281 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 282 | L_PTE_USER | L_PTE_RDONLY, |
ae8f1541 | 283 | .prot_l1 = PMD_TYPE_TABLE, |
a02d8dfd | 284 | .domain = DOMAIN_VECTORS, |
ae8f1541 | 285 | }, |
2e2c9de2 | 286 | [MT_MEMORY_RWX] = { |
36bb94ba | 287 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
f1a2481c | 288 | .prot_l1 = PMD_TYPE_TABLE, |
9ef79635 | 289 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
ae8f1541 RK |
290 | .domain = DOMAIN_KERNEL, |
291 | }, | |
ebd4922e RK |
292 | [MT_MEMORY_RW] = { |
293 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
294 | L_PTE_XN, | |
295 | .prot_l1 = PMD_TYPE_TABLE, | |
296 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, | |
297 | .domain = DOMAIN_KERNEL, | |
298 | }, | |
598f0a99 ZL |
299 | [MT_MEMORY_RO] = { |
300 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
301 | L_PTE_XN | L_PTE_RDONLY, | |
302 | .prot_l1 = PMD_TYPE_TABLE, | |
14ca1a46 WK |
303 | #ifdef CONFIG_ARM_LPAE |
304 | .prot_sect = PMD_TYPE_SECT | L_PMD_SECT_RDONLY | PMD_SECT_AP2, | |
305 | #else | |
598f0a99 | 306 | .prot_sect = PMD_TYPE_SECT, |
14ca1a46 | 307 | #endif |
598f0a99 ZL |
308 | .domain = DOMAIN_KERNEL, |
309 | }, | |
ae8f1541 | 310 | [MT_ROM] = { |
9ef79635 | 311 | .prot_sect = PMD_TYPE_SECT, |
ae8f1541 RK |
312 | .domain = DOMAIN_KERNEL, |
313 | }, | |
2e2c9de2 | 314 | [MT_MEMORY_RWX_NONCACHED] = { |
f1a2481c | 315 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 316 | L_PTE_MT_BUFFERABLE, |
f1a2481c | 317 | .prot_l1 = PMD_TYPE_TABLE, |
e4707dd3 PW |
318 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
319 | .domain = DOMAIN_KERNEL, | |
320 | }, | |
2e2c9de2 | 321 | [MT_MEMORY_RW_DTCM] = { |
f444fce3 | 322 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 323 | L_PTE_XN, |
f444fce3 LW |
324 | .prot_l1 = PMD_TYPE_TABLE, |
325 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
326 | .domain = DOMAIN_KERNEL, | |
cb9d7707 | 327 | }, |
2e2c9de2 | 328 | [MT_MEMORY_RWX_ITCM] = { |
36bb94ba | 329 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
cb9d7707 | 330 | .prot_l1 = PMD_TYPE_TABLE, |
f444fce3 | 331 | .domain = DOMAIN_KERNEL, |
cb9d7707 | 332 | }, |
2e2c9de2 | 333 | [MT_MEMORY_RW_SO] = { |
8fb54284 | 334 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
93d5bf07 | 335 | L_PTE_MT_UNCACHED | L_PTE_XN, |
8fb54284 SS |
336 | .prot_l1 = PMD_TYPE_TABLE, |
337 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | | |
338 | PMD_SECT_UNCACHED | PMD_SECT_XN, | |
339 | .domain = DOMAIN_KERNEL, | |
340 | }, | |
c7909509 | 341 | [MT_MEMORY_DMA_READY] = { |
71b55663 RK |
342 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
343 | L_PTE_XN, | |
c7909509 MS |
344 | .prot_l1 = PMD_TYPE_TABLE, |
345 | .domain = DOMAIN_KERNEL, | |
346 | }, | |
ae8f1541 RK |
347 | }; |
348 | ||
b29e9f5e RK |
349 | const struct mem_type *get_mem_type(unsigned int type) |
350 | { | |
351 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; | |
352 | } | |
69d3a84a | 353 | EXPORT_SYMBOL(get_mem_type); |
b29e9f5e | 354 | |
a5f4c561 SA |
355 | static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr); |
356 | ||
357 | static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS] | |
358 | __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata; | |
359 | ||
360 | static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr) | |
361 | { | |
362 | return &bm_pte[pte_index(addr)]; | |
363 | } | |
364 | ||
365 | static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr) | |
366 | { | |
367 | return pte_offset_kernel(dir, addr); | |
368 | } | |
369 | ||
370 | static inline pmd_t * __init fixmap_pmd(unsigned long addr) | |
371 | { | |
e05c7b1f | 372 | return pmd_off_k(addr); |
a5f4c561 SA |
373 | } |
374 | ||
375 | void __init early_fixmap_init(void) | |
376 | { | |
377 | pmd_t *pmd; | |
378 | ||
379 | /* | |
380 | * The early fixmap range spans multiple pmds, for which | |
381 | * we are not prepared: | |
382 | */ | |
2937367b | 383 | BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT) |
a5f4c561 SA |
384 | != FIXADDR_TOP >> PMD_SHIFT); |
385 | ||
386 | pmd = fixmap_pmd(FIXADDR_TOP); | |
387 | pmd_populate_kernel(&init_mm, pmd, bm_pte); | |
388 | ||
389 | pte_offset_fixmap = pte_offset_early_fixmap; | |
390 | } | |
391 | ||
99b4ac9a KC |
392 | /* |
393 | * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range(). | |
394 | * As a result, this can only be called with preemption disabled, as under | |
395 | * stop_machine(). | |
396 | */ | |
397 | void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) | |
398 | { | |
399 | unsigned long vaddr = __fix_to_virt(idx); | |
a5f4c561 | 400 | pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr); |
99b4ac9a KC |
401 | |
402 | /* Make sure fixmap region does not exceed available allocation. */ | |
d624833f | 403 | BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses) < FIXADDR_START); |
99b4ac9a KC |
404 | BUG_ON(idx >= __end_of_fixed_addresses); |
405 | ||
0d08e7bf | 406 | /* We support only device mappings before pgprot_kernel is set. */ |
b089c31c | 407 | if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) && |
0d08e7bf | 408 | pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0)) |
b089c31c JM |
409 | return; |
410 | ||
99b4ac9a KC |
411 | if (pgprot_val(prot)) |
412 | set_pte_at(NULL, vaddr, pte, | |
413 | pfn_pte(phys >> PAGE_SHIFT, prot)); | |
414 | else | |
415 | pte_clear(NULL, vaddr, pte); | |
416 | local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE); | |
417 | } | |
418 | ||
ca26f936 AK |
419 | static pgprot_t protection_map[16] __ro_after_init = { |
420 | [VM_NONE] = __PAGE_NONE, | |
421 | [VM_READ] = __PAGE_READONLY, | |
422 | [VM_WRITE] = __PAGE_COPY, | |
423 | [VM_WRITE | VM_READ] = __PAGE_COPY, | |
424 | [VM_EXEC] = __PAGE_READONLY_EXEC, | |
425 | [VM_EXEC | VM_READ] = __PAGE_READONLY_EXEC, | |
426 | [VM_EXEC | VM_WRITE] = __PAGE_COPY_EXEC, | |
427 | [VM_EXEC | VM_WRITE | VM_READ] = __PAGE_COPY_EXEC, | |
428 | [VM_SHARED] = __PAGE_NONE, | |
429 | [VM_SHARED | VM_READ] = __PAGE_READONLY, | |
430 | [VM_SHARED | VM_WRITE] = __PAGE_SHARED, | |
431 | [VM_SHARED | VM_WRITE | VM_READ] = __PAGE_SHARED, | |
432 | [VM_SHARED | VM_EXEC] = __PAGE_READONLY_EXEC, | |
433 | [VM_SHARED | VM_EXEC | VM_READ] = __PAGE_READONLY_EXEC, | |
434 | [VM_SHARED | VM_EXEC | VM_WRITE] = __PAGE_SHARED_EXEC, | |
435 | [VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = __PAGE_SHARED_EXEC | |
436 | }; | |
437 | DECLARE_VM_GET_PAGE_PROT | |
438 | ||
ae8f1541 RK |
439 | /* |
440 | * Adjust the PMD section entries according to the CPU in use. | |
441 | */ | |
442 | static void __init build_mem_type_table(void) | |
443 | { | |
444 | struct cachepolicy *cp; | |
445 | unsigned int cr = get_cr(); | |
442e70c0 | 446 | pteval_t user_pgprot, kern_pgprot, vecs_pgprot; |
ae8f1541 RK |
447 | int cpu_arch = cpu_architecture(); |
448 | int i; | |
449 | ||
11179d8c | 450 | if (cpu_arch < CPU_ARCH_ARMv6) { |
ae8f1541 | 451 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
11179d8c CM |
452 | if (cachepolicy > CPOLICY_BUFFERED) |
453 | cachepolicy = CPOLICY_BUFFERED; | |
ae8f1541 | 454 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
11179d8c CM |
455 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
456 | cachepolicy = CPOLICY_WRITETHROUGH; | |
ae8f1541 | 457 | #endif |
11179d8c | 458 | } |
ae8f1541 RK |
459 | if (cpu_arch < CPU_ARCH_ARMv5) { |
460 | if (cachepolicy >= CPOLICY_WRITEALLOC) | |
461 | cachepolicy = CPOLICY_WRITEBACK; | |
462 | ecc_mask = 0; | |
463 | } | |
ca8f0b0a | 464 | |
20e7e364 RK |
465 | if (is_smp()) { |
466 | if (cachepolicy != CPOLICY_WRITEALLOC) { | |
467 | pr_warn("Forcing write-allocate cache policy for SMP\n"); | |
468 | cachepolicy = CPOLICY_WRITEALLOC; | |
469 | } | |
470 | if (!(initial_pmd_value & PMD_SECT_S)) { | |
471 | pr_warn("Forcing shared mappings for SMP\n"); | |
472 | initial_pmd_value |= PMD_SECT_S; | |
473 | } | |
ca8f0b0a | 474 | } |
ae8f1541 | 475 | |
1ad77a87 | 476 | /* |
b1cce6b1 RK |
477 | * Strip out features not present on earlier architectures. |
478 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those | |
479 | * without extended page tables don't have the 'Shared' bit. | |
1ad77a87 | 480 | */ |
b1cce6b1 RK |
481 | if (cpu_arch < CPU_ARCH_ARMv5) |
482 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
483 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); | |
484 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) | |
485 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
486 | mem_types[i].prot_sect &= ~PMD_SECT_S; | |
ae8f1541 RK |
487 | |
488 | /* | |
b1cce6b1 RK |
489 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
490 | * "update-able on write" bit on ARM610). However, Xscale and | |
491 | * Xscale3 require this bit to be cleared. | |
ae8f1541 | 492 | */ |
d33c43ac | 493 | if (cpu_is_xscale_family()) { |
9ef79635 | 494 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
ae8f1541 | 495 | mem_types[i].prot_sect &= ~PMD_BIT4; |
9ef79635 RK |
496 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
497 | } | |
498 | } else if (cpu_arch < CPU_ARCH_ARMv6) { | |
499 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 RK |
500 | if (mem_types[i].prot_l1) |
501 | mem_types[i].prot_l1 |= PMD_BIT4; | |
9ef79635 RK |
502 | if (mem_types[i].prot_sect) |
503 | mem_types[i].prot_sect |= PMD_BIT4; | |
504 | } | |
505 | } | |
ae8f1541 | 506 | |
b1cce6b1 RK |
507 | /* |
508 | * Mark the device areas according to the CPU/architecture. | |
509 | */ | |
510 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { | |
511 | if (!cpu_is_xsc3()) { | |
512 | /* | |
513 | * Mark device regions on ARMv6+ as execute-never | |
514 | * to prevent speculative instruction fetches. | |
515 | */ | |
516 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; | |
517 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; | |
518 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; | |
519 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; | |
ebd4922e RK |
520 | |
521 | /* Also setup NX memory mapping */ | |
522 | mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN; | |
598f0a99 | 523 | mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_XN; |
b1cce6b1 RK |
524 | } |
525 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
526 | /* | |
527 | * For ARMv7 with TEX remapping, | |
528 | * - shared device is SXCB=1100 | |
529 | * - nonshared device is SXCB=0100 | |
530 | * - write combine device mem is SXCB=0001 | |
531 | * (Uncached Normal memory) | |
532 | */ | |
533 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); | |
534 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); | |
535 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
536 | } else if (cpu_is_xsc3()) { | |
537 | /* | |
538 | * For Xscale3, | |
539 | * - shared device is TEXCB=00101 | |
540 | * - nonshared device is TEXCB=01000 | |
541 | * - write combine device mem is TEXCB=00100 | |
542 | * (Inner/Outer Uncacheable in xsc3 parlance) | |
543 | */ | |
544 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; | |
545 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
546 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
547 | } else { | |
548 | /* | |
549 | * For ARMv6 and ARMv7 without TEX remapping, | |
550 | * - shared device is TEXCB=00001 | |
551 | * - nonshared device is TEXCB=01000 | |
552 | * - write combine device mem is TEXCB=00100 | |
553 | * (Uncached Normal in ARMv6 parlance). | |
554 | */ | |
555 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; | |
556 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
557 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
558 | } | |
559 | } else { | |
560 | /* | |
561 | * On others, write combining is "Uncached/Buffered" | |
562 | */ | |
563 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
564 | } | |
565 | ||
566 | /* | |
567 | * Now deal with the memory-type mappings | |
568 | */ | |
ae8f1541 | 569 | cp = &cache_policies[cachepolicy]; |
bb30f36f RK |
570 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
571 | ||
1d4d3715 | 572 | #ifndef CONFIG_ARM_LPAE |
b6ccb980 WD |
573 | /* |
574 | * We don't use domains on ARMv6 (since this causes problems with | |
575 | * v6/v7 kernels), so we must use a separate memory type for user | |
576 | * r/o, kernel r/w to map the vectors page. | |
577 | */ | |
b6ccb980 WD |
578 | if (cpu_arch == CPU_ARCH_ARMv6) |
579 | vecs_pgprot |= L_PTE_MT_VECTORS; | |
1d4d3715 JL |
580 | |
581 | /* | |
582 | * Check is it with support for the PXN bit | |
583 | * in the Short-descriptor translation table format descriptors. | |
584 | */ | |
585 | if (cpu_arch == CPU_ARCH_ARMv7 && | |
ad84f56b | 586 | (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) { |
1d4d3715 JL |
587 | user_pmd_table |= PMD_PXNTABLE; |
588 | } | |
b6ccb980 | 589 | #endif |
bb30f36f | 590 | |
ae8f1541 RK |
591 | /* |
592 | * ARMv6 and above have extended page tables. | |
593 | */ | |
594 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { | |
1b6ba46b | 595 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
596 | /* |
597 | * Mark cache clean areas and XIP ROM read only | |
598 | * from SVC mode and no access from userspace. | |
599 | */ | |
600 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
601 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
602 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
598f0a99 | 603 | mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; |
1b6ba46b | 604 | #endif |
ae8f1541 | 605 | |
20e7e364 RK |
606 | /* |
607 | * If the initial page tables were created with the S bit | |
608 | * set, then we need to do the same here for the same | |
609 | * reasons given in early_cachepolicy(). | |
610 | */ | |
611 | if (initial_pmd_value & PMD_SECT_S) { | |
f00ec48f RK |
612 | user_pgprot |= L_PTE_SHARED; |
613 | kern_pgprot |= L_PTE_SHARED; | |
614 | vecs_pgprot |= L_PTE_SHARED; | |
615 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; | |
616 | mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; | |
617 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; | |
618 | mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; | |
2e2c9de2 RK |
619 | mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S; |
620 | mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED; | |
ebd4922e RK |
621 | mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S; |
622 | mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED; | |
598f0a99 ZL |
623 | mem_types[MT_MEMORY_RO].prot_sect |= PMD_SECT_S; |
624 | mem_types[MT_MEMORY_RO].prot_pte |= L_PTE_SHARED; | |
c7909509 | 625 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; |
2e2c9de2 RK |
626 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S; |
627 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED; | |
f00ec48f | 628 | } |
ae8f1541 RK |
629 | } |
630 | ||
e4707dd3 PW |
631 | /* |
632 | * Non-cacheable Normal - intended for memory areas that must | |
633 | * not cause dirty cache line writebacks when used | |
634 | */ | |
635 | if (cpu_arch >= CPU_ARCH_ARMv6) { | |
636 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
637 | /* Non-cacheable Normal is XCB = 001 */ | |
2e2c9de2 | 638 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= |
e4707dd3 PW |
639 | PMD_SECT_BUFFERED; |
640 | } else { | |
641 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | |
2e2c9de2 | 642 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= |
e4707dd3 PW |
643 | PMD_SECT_TEX(1); |
644 | } | |
645 | } else { | |
2e2c9de2 | 646 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; |
e4707dd3 PW |
647 | } |
648 | ||
1b6ba46b CM |
649 | #ifdef CONFIG_ARM_LPAE |
650 | /* | |
651 | * Do not generate access flag faults for the kernel mappings. | |
652 | */ | |
653 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
654 | mem_types[i].prot_pte |= PTE_EXT_AF; | |
1a3abcf4 VA |
655 | if (mem_types[i].prot_sect) |
656 | mem_types[i].prot_sect |= PMD_SECT_AF; | |
1b6ba46b CM |
657 | } |
658 | kern_pgprot |= PTE_EXT_AF; | |
659 | vecs_pgprot |= PTE_EXT_AF; | |
1d4d3715 JL |
660 | |
661 | /* | |
662 | * Set PXN for user mappings | |
663 | */ | |
664 | user_pgprot |= PTE_EXT_PXN; | |
1b6ba46b CM |
665 | #endif |
666 | ||
ae8f1541 | 667 | for (i = 0; i < 16; i++) { |
864aa04c | 668 | pteval_t v = pgprot_val(protection_map[i]); |
bb30f36f | 669 | protection_map[i] = __pgprot(v | user_pgprot); |
ae8f1541 RK |
670 | } |
671 | ||
bb30f36f RK |
672 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
673 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; | |
ae8f1541 | 674 | |
44b18693 | 675 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
ae8f1541 | 676 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
36bb94ba | 677 | L_PTE_DIRTY | kern_pgprot); |
ae8f1541 RK |
678 | |
679 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | |
680 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | |
2e2c9de2 RK |
681 | mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd; |
682 | mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; | |
ebd4922e RK |
683 | mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; |
684 | mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; | |
598f0a99 ZL |
685 | mem_types[MT_MEMORY_RO].prot_sect |= ecc_mask | cp->pmd; |
686 | mem_types[MT_MEMORY_RO].prot_pte |= kern_pgprot; | |
c7909509 | 687 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; |
2e2c9de2 | 688 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; |
ae8f1541 RK |
689 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
690 | ||
691 | switch (cp->pmd) { | |
692 | case PMD_SECT_WT: | |
693 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; | |
694 | break; | |
695 | case PMD_SECT_WB: | |
696 | case PMD_SECT_WBWA: | |
697 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; | |
698 | break; | |
699 | } | |
905b5797 MS |
700 | pr_info("Memory policy: %sData cache %s\n", |
701 | ecc_mask ? "ECC enabled, " : "", cp->policy); | |
2497f0a8 RK |
702 | |
703 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
704 | struct mem_type *t = &mem_types[i]; | |
705 | if (t->prot_l1) | |
706 | t->prot_l1 |= PMD_DOMAIN(t->domain); | |
707 | if (t->prot_sect) | |
708 | t->prot_sect |= PMD_DOMAIN(t->domain); | |
709 | } | |
ae8f1541 RK |
710 | } |
711 | ||
d907387c CM |
712 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE |
713 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
714 | unsigned long size, pgprot_t vma_prot) | |
715 | { | |
716 | if (!pfn_valid(pfn)) | |
717 | return pgprot_noncached(vma_prot); | |
718 | else if (file->f_flags & O_SYNC) | |
719 | return pgprot_writecombine(vma_prot); | |
720 | return vma_prot; | |
721 | } | |
722 | EXPORT_SYMBOL(phys_mem_access_prot); | |
723 | #endif | |
724 | ||
ae8f1541 RK |
725 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
726 | ||
0536bdf3 NP |
727 | static void __init *early_alloc(unsigned long sz) |
728 | { | |
8a7f97b9 MR |
729 | void *ptr = memblock_alloc(sz, sz); |
730 | ||
731 | if (!ptr) | |
732 | panic("%s: Failed to allocate %lu bytes align=0x%lx\n", | |
733 | __func__, sz, sz); | |
734 | ||
735 | return ptr; | |
0536bdf3 NP |
736 | } |
737 | ||
c7936206 AB |
738 | static void *__init late_alloc(unsigned long sz) |
739 | { | |
358d1c39 VMO |
740 | void *ptdesc = pagetable_alloc(GFP_PGTABLE_KERNEL & ~__GFP_HIGHMEM, |
741 | get_order(sz)); | |
c7936206 | 742 | |
358d1c39 | 743 | if (!ptdesc || !pagetable_pte_ctor(ptdesc)) |
61444cde | 744 | BUG(); |
358d1c39 | 745 | return ptdesc_to_virt(ptdesc); |
c7936206 AB |
746 | } |
747 | ||
3ed3a4f0 | 748 | static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr, |
f579b2b1 AB |
749 | unsigned long prot, |
750 | void *(*alloc)(unsigned long sz)) | |
ae8f1541 | 751 | { |
24e6c699 | 752 | if (pmd_none(*pmd)) { |
f579b2b1 | 753 | pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); |
97092e0c | 754 | __pmd_populate(pmd, __pa(pte), prot); |
24e6c699 | 755 | } |
4bb2e27d RK |
756 | BUG_ON(pmd_bad(*pmd)); |
757 | return pte_offset_kernel(pmd, addr); | |
758 | } | |
ae8f1541 | 759 | |
f579b2b1 AB |
760 | static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, |
761 | unsigned long prot) | |
762 | { | |
3ed3a4f0 | 763 | return arm_pte_alloc(pmd, addr, prot, early_alloc); |
f579b2b1 AB |
764 | } |
765 | ||
4bb2e27d RK |
766 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
767 | unsigned long end, unsigned long pfn, | |
f579b2b1 | 768 | const struct mem_type *type, |
b430e55b AB |
769 | void *(*alloc)(unsigned long sz), |
770 | bool ng) | |
4bb2e27d | 771 | { |
3ed3a4f0 | 772 | pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc); |
24e6c699 | 773 | do { |
b430e55b AB |
774 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), |
775 | ng ? PTE_EXT_NG : 0); | |
24e6c699 RK |
776 | pfn++; |
777 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
ae8f1541 RK |
778 | } |
779 | ||
37468b30 | 780 | static void __init __map_init_section(pmd_t *pmd, unsigned long addr, |
e651eab0 | 781 | unsigned long end, phys_addr_t phys, |
b430e55b | 782 | const struct mem_type *type, bool ng) |
ae8f1541 | 783 | { |
37468b30 PYC |
784 | pmd_t *p = pmd; |
785 | ||
e651eab0 | 786 | #ifndef CONFIG_ARM_LPAE |
24e6c699 | 787 | /* |
e651eab0 S |
788 | * In classic MMU format, puds and pmds are folded in to |
789 | * the pgds. pmd_offset gives the PGD entry. PGDs refer to a | |
790 | * group of L1 entries making up one logical pointer to | |
791 | * an L2 table (2MB), where as PMDs refer to the individual | |
792 | * L1 entries (1MB). Hence increment to get the correct | |
793 | * offset for odd 1MB sections. | |
794 | * (See arch/arm/include/asm/pgtable-2level.h) | |
24e6c699 | 795 | */ |
e651eab0 S |
796 | if (addr & SECTION_SIZE) |
797 | pmd++; | |
1b6ba46b | 798 | #endif |
e651eab0 | 799 | do { |
b430e55b | 800 | *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0)); |
e651eab0 S |
801 | phys += SECTION_SIZE; |
802 | } while (pmd++, addr += SECTION_SIZE, addr != end); | |
24e6c699 | 803 | |
37468b30 | 804 | flush_pmd_entry(p); |
e651eab0 | 805 | } |
ae8f1541 | 806 | |
e651eab0 S |
807 | static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, |
808 | unsigned long end, phys_addr_t phys, | |
f579b2b1 | 809 | const struct mem_type *type, |
b430e55b | 810 | void *(*alloc)(unsigned long sz), bool ng) |
e651eab0 S |
811 | { |
812 | pmd_t *pmd = pmd_offset(pud, addr); | |
813 | unsigned long next; | |
814 | ||
815 | do { | |
24e6c699 | 816 | /* |
e651eab0 S |
817 | * With LPAE, we must loop over to map |
818 | * all the pmds for the given range. | |
24e6c699 | 819 | */ |
e651eab0 S |
820 | next = pmd_addr_end(addr, end); |
821 | ||
822 | /* | |
823 | * Try a section mapping - addr, next and phys must all be | |
824 | * aligned to a section boundary. | |
825 | */ | |
826 | if (type->prot_sect && | |
827 | ((addr | next | phys) & ~SECTION_MASK) == 0) { | |
b430e55b | 828 | __map_init_section(pmd, addr, next, phys, type, ng); |
e651eab0 S |
829 | } else { |
830 | alloc_init_pte(pmd, addr, next, | |
b430e55b | 831 | __phys_to_pfn(phys), type, alloc, ng); |
e651eab0 S |
832 | } |
833 | ||
834 | phys += next - addr; | |
835 | ||
836 | } while (pmd++, addr = next, addr != end); | |
ae8f1541 RK |
837 | } |
838 | ||
84e6ffb2 | 839 | static void __init alloc_init_pud(p4d_t *p4d, unsigned long addr, |
20d6956d | 840 | unsigned long end, phys_addr_t phys, |
f579b2b1 | 841 | const struct mem_type *type, |
b430e55b | 842 | void *(*alloc)(unsigned long sz), bool ng) |
516295e5 | 843 | { |
84e6ffb2 | 844 | pud_t *pud = pud_offset(p4d, addr); |
516295e5 RK |
845 | unsigned long next; |
846 | ||
847 | do { | |
848 | next = pud_addr_end(addr, end); | |
b430e55b | 849 | alloc_init_pmd(pud, addr, next, phys, type, alloc, ng); |
516295e5 RK |
850 | phys += next - addr; |
851 | } while (pud++, addr = next, addr != end); | |
852 | } | |
853 | ||
84e6ffb2 MR |
854 | static void __init alloc_init_p4d(pgd_t *pgd, unsigned long addr, |
855 | unsigned long end, phys_addr_t phys, | |
856 | const struct mem_type *type, | |
857 | void *(*alloc)(unsigned long sz), bool ng) | |
858 | { | |
859 | p4d_t *p4d = p4d_offset(pgd, addr); | |
860 | unsigned long next; | |
861 | ||
862 | do { | |
863 | next = p4d_addr_end(addr, end); | |
864 | alloc_init_pud(p4d, addr, next, phys, type, alloc, ng); | |
865 | phys += next - addr; | |
866 | } while (p4d++, addr = next, addr != end); | |
867 | } | |
868 | ||
1b6ba46b | 869 | #ifndef CONFIG_ARM_LPAE |
1bdb2d4e AB |
870 | static void __init create_36bit_mapping(struct mm_struct *mm, |
871 | struct map_desc *md, | |
b430e55b AB |
872 | const struct mem_type *type, |
873 | bool ng) | |
4a56c1e4 | 874 | { |
97092e0c RK |
875 | unsigned long addr, length, end; |
876 | phys_addr_t phys; | |
4a56c1e4 RK |
877 | pgd_t *pgd; |
878 | ||
879 | addr = md->virtual; | |
cae6292b | 880 | phys = __pfn_to_phys(md->pfn); |
4a56c1e4 RK |
881 | length = PAGE_ALIGN(md->length); |
882 | ||
883 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { | |
4ed89f22 | 884 | pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n", |
29a38193 | 885 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
886 | return; |
887 | } | |
888 | ||
889 | /* N.B. ARMv6 supersections are only defined to work with domain 0. | |
890 | * Since domain assignments can in fact be arbitrary, the | |
891 | * 'domain == 0' check below is required to insure that ARMv6 | |
892 | * supersections are only allocated for domain 0 regardless | |
893 | * of the actual domain assignments in use. | |
894 | */ | |
895 | if (type->domain) { | |
4ed89f22 | 896 | pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n", |
29a38193 | 897 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
898 | return; |
899 | } | |
900 | ||
901 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { | |
4ed89f22 | 902 | pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n", |
29a38193 | 903 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
904 | return; |
905 | } | |
906 | ||
907 | /* | |
908 | * Shift bits [35:32] of address into bits [23:20] of PMD | |
909 | * (See ARMv6 spec). | |
910 | */ | |
911 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); | |
912 | ||
1bdb2d4e | 913 | pgd = pgd_offset(mm, addr); |
4a56c1e4 RK |
914 | end = addr + length; |
915 | do { | |
84e6ffb2 MR |
916 | p4d_t *p4d = p4d_offset(pgd, addr); |
917 | pud_t *pud = pud_offset(p4d, addr); | |
516295e5 | 918 | pmd_t *pmd = pmd_offset(pud, addr); |
4a56c1e4 RK |
919 | int i; |
920 | ||
921 | for (i = 0; i < 16; i++) | |
b430e55b AB |
922 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER | |
923 | (ng ? PMD_SECT_nG : 0)); | |
4a56c1e4 RK |
924 | |
925 | addr += SUPERSECTION_SIZE; | |
926 | phys += SUPERSECTION_SIZE; | |
927 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; | |
928 | } while (addr != end); | |
929 | } | |
1b6ba46b | 930 | #endif /* !CONFIG_ARM_LPAE */ |
4a56c1e4 | 931 | |
f579b2b1 | 932 | static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md, |
b430e55b AB |
933 | void *(*alloc)(unsigned long sz), |
934 | bool ng) | |
ae8f1541 | 935 | { |
cae6292b WD |
936 | unsigned long addr, length, end; |
937 | phys_addr_t phys; | |
d5c98176 | 938 | const struct mem_type *type; |
24e6c699 | 939 | pgd_t *pgd; |
ae8f1541 | 940 | |
d5c98176 | 941 | type = &mem_types[md->type]; |
ae8f1541 | 942 | |
1b6ba46b | 943 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
944 | /* |
945 | * Catch 36-bit addresses | |
946 | */ | |
4a56c1e4 | 947 | if (md->pfn >= 0x100000) { |
b430e55b | 948 | create_36bit_mapping(mm, md, type, ng); |
4a56c1e4 | 949 | return; |
ae8f1541 | 950 | } |
1b6ba46b | 951 | #endif |
ae8f1541 | 952 | |
7b9c7b4d | 953 | addr = md->virtual & PAGE_MASK; |
cae6292b | 954 | phys = __pfn_to_phys(md->pfn); |
7b9c7b4d | 955 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
ae8f1541 | 956 | |
24e6c699 | 957 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
4ed89f22 RK |
958 | pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n", |
959 | (long long)__pfn_to_phys(md->pfn), addr); | |
ae8f1541 RK |
960 | return; |
961 | } | |
962 | ||
1bdb2d4e | 963 | pgd = pgd_offset(mm, addr); |
24e6c699 RK |
964 | end = addr + length; |
965 | do { | |
966 | unsigned long next = pgd_addr_end(addr, end); | |
ae8f1541 | 967 | |
84e6ffb2 | 968 | alloc_init_p4d(pgd, addr, next, phys, type, alloc, ng); |
ae8f1541 | 969 | |
24e6c699 RK |
970 | phys += next - addr; |
971 | addr = next; | |
972 | } while (pgd++, addr != end); | |
ae8f1541 RK |
973 | } |
974 | ||
1bdb2d4e AB |
975 | /* |
976 | * Create the page directory entries and any necessary | |
977 | * page tables for the mapping specified by `md'. We | |
978 | * are able to cope here with varying sizes and address | |
979 | * offsets, and we take full advantage of sections and | |
980 | * supersections. | |
981 | */ | |
982 | static void __init create_mapping(struct map_desc *md) | |
983 | { | |
984 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { | |
985 | pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n", | |
986 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
987 | return; | |
988 | } | |
989 | ||
7a1be318 | 990 | if (md->type == MT_DEVICE && |
1bdb2d4e AB |
991 | md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START && |
992 | (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { | |
993 | pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n", | |
994 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
995 | } | |
996 | ||
b430e55b | 997 | __create_mapping(&init_mm, md, early_alloc, false); |
1bdb2d4e AB |
998 | } |
999 | ||
c7936206 AB |
1000 | void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md, |
1001 | bool ng) | |
1002 | { | |
1003 | #ifdef CONFIG_ARM_LPAE | |
84e6ffb2 MR |
1004 | p4d_t *p4d; |
1005 | pud_t *pud; | |
1006 | ||
1007 | p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual); | |
5c6360ee | 1008 | if (WARN_ON(!p4d)) |
84e6ffb2 MR |
1009 | return; |
1010 | pud = pud_alloc(mm, p4d, md->virtual); | |
c7936206 AB |
1011 | if (WARN_ON(!pud)) |
1012 | return; | |
1013 | pmd_alloc(mm, pud, 0); | |
1014 | #endif | |
1015 | __create_mapping(mm, md, late_alloc, ng); | |
1016 | } | |
1017 | ||
ae8f1541 RK |
1018 | /* |
1019 | * Create the architecture specific mappings | |
1020 | */ | |
1021 | void __init iotable_init(struct map_desc *io_desc, int nr) | |
1022 | { | |
0536bdf3 NP |
1023 | struct map_desc *md; |
1024 | struct vm_struct *vm; | |
101eeda3 | 1025 | struct static_vm *svm; |
0536bdf3 NP |
1026 | |
1027 | if (!nr) | |
1028 | return; | |
ae8f1541 | 1029 | |
c2938eeb | 1030 | svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm)); |
8a7f97b9 MR |
1031 | if (!svm) |
1032 | panic("%s: Failed to allocate %zu bytes align=0x%zx\n", | |
1033 | __func__, sizeof(*svm) * nr, __alignof__(*svm)); | |
0536bdf3 NP |
1034 | |
1035 | for (md = io_desc; nr; md++, nr--) { | |
1036 | create_mapping(md); | |
101eeda3 JK |
1037 | |
1038 | vm = &svm->vm; | |
0536bdf3 NP |
1039 | vm->addr = (void *)(md->virtual & PAGE_MASK); |
1040 | vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); | |
c2794437 RH |
1041 | vm->phys_addr = __pfn_to_phys(md->pfn); |
1042 | vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; | |
576d2f25 | 1043 | vm->flags |= VM_ARM_MTYPE(md->type); |
0536bdf3 | 1044 | vm->caller = iotable_init; |
101eeda3 | 1045 | add_static_vm_early(svm++); |
0536bdf3 | 1046 | } |
ae8f1541 RK |
1047 | } |
1048 | ||
c2794437 RH |
1049 | void __init vm_reserve_area_early(unsigned long addr, unsigned long size, |
1050 | void *caller) | |
1051 | { | |
1052 | struct vm_struct *vm; | |
101eeda3 JK |
1053 | struct static_vm *svm; |
1054 | ||
c2938eeb | 1055 | svm = memblock_alloc(sizeof(*svm), __alignof__(*svm)); |
8a7f97b9 MR |
1056 | if (!svm) |
1057 | panic("%s: Failed to allocate %zu bytes align=0x%zx\n", | |
1058 | __func__, sizeof(*svm), __alignof__(*svm)); | |
c2794437 | 1059 | |
101eeda3 | 1060 | vm = &svm->vm; |
c2794437 RH |
1061 | vm->addr = (void *)addr; |
1062 | vm->size = size; | |
863e99a8 | 1063 | vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; |
c2794437 | 1064 | vm->caller = caller; |
101eeda3 | 1065 | add_static_vm_early(svm); |
c2794437 RH |
1066 | } |
1067 | ||
19b52abe NP |
1068 | #ifndef CONFIG_ARM_LPAE |
1069 | ||
1070 | /* | |
1071 | * The Linux PMD is made of two consecutive section entries covering 2MB | |
1072 | * (see definition in include/asm/pgtable-2level.h). However a call to | |
1073 | * create_mapping() may optimize static mappings by using individual | |
1074 | * 1MB section mappings. This leaves the actual PMD potentially half | |
1075 | * initialized if the top or bottom section entry isn't used, leaving it | |
1076 | * open to problems if a subsequent ioremap() or vmalloc() tries to use | |
1077 | * the virtual space left free by that unused section entry. | |
1078 | * | |
1079 | * Let's avoid the issue by inserting dummy vm entries covering the unused | |
1080 | * PMD halves once the static mappings are in place. | |
1081 | */ | |
1082 | ||
1083 | static void __init pmd_empty_section_gap(unsigned long addr) | |
1084 | { | |
c2794437 | 1085 | vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); |
19b52abe NP |
1086 | } |
1087 | ||
1088 | static void __init fill_pmd_gaps(void) | |
1089 | { | |
101eeda3 | 1090 | struct static_vm *svm; |
19b52abe NP |
1091 | struct vm_struct *vm; |
1092 | unsigned long addr, next = 0; | |
1093 | pmd_t *pmd; | |
1094 | ||
101eeda3 JK |
1095 | list_for_each_entry(svm, &static_vmlist, list) { |
1096 | vm = &svm->vm; | |
19b52abe NP |
1097 | addr = (unsigned long)vm->addr; |
1098 | if (addr < next) | |
1099 | continue; | |
1100 | ||
1101 | /* | |
1102 | * Check if this vm starts on an odd section boundary. | |
1103 | * If so and the first section entry for this PMD is free | |
1104 | * then we block the corresponding virtual address. | |
1105 | */ | |
1106 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
1107 | pmd = pmd_off_k(addr); | |
1108 | if (pmd_none(*pmd)) | |
1109 | pmd_empty_section_gap(addr & PMD_MASK); | |
1110 | } | |
1111 | ||
1112 | /* | |
1113 | * Then check if this vm ends on an odd section boundary. | |
1114 | * If so and the second section entry for this PMD is empty | |
1115 | * then we block the corresponding virtual address. | |
1116 | */ | |
1117 | addr += vm->size; | |
1118 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
1119 | pmd = pmd_off_k(addr) + 1; | |
1120 | if (pmd_none(*pmd)) | |
1121 | pmd_empty_section_gap(addr); | |
1122 | } | |
1123 | ||
1124 | /* no need to look at any vm entry until we hit the next PMD */ | |
1125 | next = (addr + PMD_SIZE - 1) & PMD_MASK; | |
1126 | } | |
1127 | } | |
1128 | ||
1129 | #else | |
1130 | #define fill_pmd_gaps() do { } while (0) | |
1131 | #endif | |
1132 | ||
c2794437 RH |
1133 | #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) |
1134 | static void __init pci_reserve_io(void) | |
1135 | { | |
101eeda3 | 1136 | struct static_vm *svm; |
c2794437 | 1137 | |
101eeda3 JK |
1138 | svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); |
1139 | if (svm) | |
1140 | return; | |
c2794437 | 1141 | |
c2794437 RH |
1142 | vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); |
1143 | } | |
1144 | #else | |
1145 | #define pci_reserve_io() do { } while (0) | |
1146 | #endif | |
1147 | ||
e5c5f2ad RH |
1148 | #ifdef CONFIG_DEBUG_LL |
1149 | void __init debug_ll_io_init(void) | |
1150 | { | |
1151 | struct map_desc map; | |
1152 | ||
1153 | debug_ll_addr(&map.pfn, &map.virtual); | |
1154 | if (!map.pfn || !map.virtual) | |
1155 | return; | |
1156 | map.pfn = __phys_to_pfn(map.pfn); | |
1157 | map.virtual &= PAGE_MASK; | |
1158 | map.length = PAGE_SIZE; | |
1159 | map.type = MT_DEVICE; | |
ee4de5d9 | 1160 | iotable_init(&map, 1); |
e5c5f2ad RH |
1161 | } |
1162 | #endif | |
1163 | ||
08b84240 | 1164 | static unsigned long __initdata vmalloc_size = 240 * SZ_1M; |
6c5da7ac RK |
1165 | |
1166 | /* | |
1167 | * vmalloc=size forces the vmalloc area to be exactly 'size' | |
1168 | * bytes. This can be used to increase (or decrease) the vmalloc | |
c01914ef | 1169 | * area - the default is 240MiB. |
6c5da7ac | 1170 | */ |
2b0d8c25 | 1171 | static int __init early_vmalloc(char *arg) |
6c5da7ac | 1172 | { |
79612395 | 1173 | unsigned long vmalloc_reserve = memparse(arg, NULL); |
4f706b07 | 1174 | unsigned long vmalloc_max; |
6c5da7ac RK |
1175 | |
1176 | if (vmalloc_reserve < SZ_16M) { | |
1177 | vmalloc_reserve = SZ_16M; | |
c01914ef | 1178 | pr_warn("vmalloc area is too small, limiting to %luMiB\n", |
6c5da7ac RK |
1179 | vmalloc_reserve >> 20); |
1180 | } | |
9210807c | 1181 | |
f572f5cb | 1182 | vmalloc_max = VMALLOC_END - (PAGE_OFFSET + SZ_32M + VMALLOC_OFFSET); |
4f706b07 RKO |
1183 | if (vmalloc_reserve > vmalloc_max) { |
1184 | vmalloc_reserve = vmalloc_max; | |
c01914ef | 1185 | pr_warn("vmalloc area is too big, limiting to %luMiB\n", |
9210807c NP |
1186 | vmalloc_reserve >> 20); |
1187 | } | |
79612395 | 1188 | |
4c1b7a76 | 1189 | vmalloc_size = vmalloc_reserve; |
2b0d8c25 | 1190 | return 0; |
6c5da7ac | 1191 | } |
2b0d8c25 | 1192 | early_param("vmalloc", early_vmalloc); |
6c5da7ac | 1193 | |
c7909509 | 1194 | phys_addr_t arm_lowmem_limit __initdata = 0; |
8df65168 | 1195 | |
374d446d | 1196 | void __init adjust_lowmem_bounds(void) |
60296c71 | 1197 | { |
b10d6bca MR |
1198 | phys_addr_t block_start, block_end, memblock_limit = 0; |
1199 | u64 vmalloc_limit, i; | |
98562656 | 1200 | phys_addr_t lowmem_limit = 0; |
60296c71 | 1201 | |
b9a01989 NP |
1202 | /* |
1203 | * Let's use our own (unoptimized) equivalent of __pa() that is | |
1204 | * not affected by wrap-arounds when sizeof(phys_addr_t) == 4. | |
1205 | * The result is used as the upper bound on physical memory address | |
1206 | * and may itself be outside the valid range for which phys_addr_t | |
1207 | * and therefore __pa() is defined. | |
1208 | */ | |
4c1b7a76 | 1209 | vmalloc_limit = (u64)VMALLOC_END - vmalloc_size - VMALLOC_OFFSET - |
f572f5cb | 1210 | PAGE_OFFSET + PHYS_OFFSET; |
b9a01989 | 1211 | |
00d2ec1e MR |
1212 | /* |
1213 | * The first usable region must be PMD aligned. Mark its start | |
1214 | * as MEMBLOCK_NOMAP if it isn't | |
1215 | */ | |
b10d6bca MR |
1216 | for_each_mem_range(i, &block_start, &block_end) { |
1217 | if (!IS_ALIGNED(block_start, PMD_SIZE)) { | |
1218 | phys_addr_t len; | |
00d2ec1e | 1219 | |
b10d6bca MR |
1220 | len = round_up(block_start, PMD_SIZE) - block_start; |
1221 | memblock_mark_nomap(block_start, len); | |
00d2ec1e | 1222 | } |
b10d6bca | 1223 | break; |
00d2ec1e MR |
1224 | } |
1225 | ||
b10d6bca MR |
1226 | for_each_mem_range(i, &block_start, &block_end) { |
1227 | if (block_start < vmalloc_limit) { | |
98562656 | 1228 | if (block_end > lowmem_limit) |
374d446d LA |
1229 | /* |
1230 | * Compare as u64 to ensure vmalloc_limit does | |
1231 | * not get truncated. block_end should always | |
1232 | * fit in phys_addr_t so there should be no | |
1233 | * issue with assignment. | |
1234 | */ | |
98562656 | 1235 | lowmem_limit = min_t(u64, |
374d446d LA |
1236 | vmalloc_limit, |
1237 | block_end); | |
c65b7e98 RK |
1238 | |
1239 | /* | |
965278dc | 1240 | * Find the first non-pmd-aligned page, and point |
c65b7e98 | 1241 | * memblock_limit at it. This relies on rounding the |
965278dc MR |
1242 | * limit down to be pmd-aligned, which happens at the |
1243 | * end of this function. | |
c65b7e98 RK |
1244 | * |
1245 | * With this algorithm, the start or end of almost any | |
965278dc MR |
1246 | * bank can be non-pmd-aligned. The only exception is |
1247 | * that the start of the bank 0 must be section- | |
c65b7e98 RK |
1248 | * aligned, since otherwise memory would need to be |
1249 | * allocated when mapping the start of bank 0, which | |
1250 | * occurs before any free memory is mapped. | |
1251 | */ | |
1252 | if (!memblock_limit) { | |
965278dc | 1253 | if (!IS_ALIGNED(block_start, PMD_SIZE)) |
1c2f87c2 | 1254 | memblock_limit = block_start; |
965278dc | 1255 | else if (!IS_ALIGNED(block_end, PMD_SIZE)) |
98562656 | 1256 | memblock_limit = lowmem_limit; |
c65b7e98 | 1257 | } |
e616c591 | 1258 | |
e616c591 RK |
1259 | } |
1260 | } | |
1c2f87c2 | 1261 | |
98562656 LA |
1262 | arm_lowmem_limit = lowmem_limit; |
1263 | ||
c7909509 | 1264 | high_memory = __va(arm_lowmem_limit - 1) + 1; |
c65b7e98 | 1265 | |
9e25ebfe DB |
1266 | if (!memblock_limit) |
1267 | memblock_limit = arm_lowmem_limit; | |
1268 | ||
c65b7e98 | 1269 | /* |
965278dc | 1270 | * Round the memblock limit down to a pmd size. This |
c65b7e98 | 1271 | * helps to ensure that we will allocate memory from the |
965278dc | 1272 | * last full pmd, which should be mapped. |
c65b7e98 | 1273 | */ |
9e25ebfe | 1274 | memblock_limit = round_down(memblock_limit, PMD_SIZE); |
c65b7e98 | 1275 | |
374d446d LA |
1276 | if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) { |
1277 | if (memblock_end_of_DRAM() > arm_lowmem_limit) { | |
1278 | phys_addr_t end = memblock_end_of_DRAM(); | |
1279 | ||
1280 | pr_notice("Ignoring RAM at %pa-%pa\n", | |
1281 | &memblock_limit, &end); | |
1282 | pr_notice("Consider using a HIGHMEM enabled kernel.\n"); | |
1283 | ||
1284 | memblock_remove(memblock_limit, end - memblock_limit); | |
1285 | } | |
1286 | } | |
1287 | ||
c65b7e98 | 1288 | memblock_set_current_limit(memblock_limit); |
60296c71 LB |
1289 | } |
1290 | ||
ae7ba761 | 1291 | static __init void prepare_page_table(void) |
d111e8f9 RK |
1292 | { |
1293 | unsigned long addr; | |
8df65168 | 1294 | phys_addr_t end; |
d111e8f9 RK |
1295 | |
1296 | /* | |
1297 | * Clear out all the mappings below the kernel image. | |
1298 | */ | |
c12366ba LW |
1299 | #ifdef CONFIG_KASAN |
1300 | /* | |
1301 | * KASan's shadow memory inserts itself between the TASK_SIZE | |
1302 | * and MODULES_VADDR. Do not clear the KASan shadow memory mappings. | |
1303 | */ | |
1304 | for (addr = 0; addr < KASAN_SHADOW_START; addr += PMD_SIZE) | |
1305 | pmd_clear(pmd_off_k(addr)); | |
1306 | /* | |
1307 | * Skip over the KASan shadow area. KASAN_SHADOW_END is sometimes | |
1308 | * equal to MODULES_VADDR and then we exit the pmd clearing. If we | |
1309 | * are using a thumb-compiled kernel, there there will be 8MB more | |
1310 | * to clear as KASan always offset to 16 MB below MODULES_VADDR. | |
1311 | */ | |
1312 | for (addr = KASAN_SHADOW_END; addr < MODULES_VADDR; addr += PMD_SIZE) | |
1313 | pmd_clear(pmd_off_k(addr)); | |
1314 | #else | |
e73fc88e | 1315 | for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) |
d111e8f9 | 1316 | pmd_clear(pmd_off_k(addr)); |
c12366ba | 1317 | #endif |
d111e8f9 RK |
1318 | |
1319 | #ifdef CONFIG_XIP_KERNEL | |
1320 | /* The XIP kernel is mapped in the module area -- skip over it */ | |
02afa9a8 | 1321 | addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK; |
d111e8f9 | 1322 | #endif |
e73fc88e | 1323 | for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) |
d111e8f9 RK |
1324 | pmd_clear(pmd_off_k(addr)); |
1325 | ||
8df65168 RK |
1326 | /* |
1327 | * Find the end of the first block of lowmem. | |
1328 | */ | |
1329 | end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; | |
c7909509 MS |
1330 | if (end >= arm_lowmem_limit) |
1331 | end = arm_lowmem_limit; | |
8df65168 | 1332 | |
d111e8f9 RK |
1333 | /* |
1334 | * Clear out all the kernel space mappings, except for the first | |
0536bdf3 | 1335 | * memory bank, up to the vmalloc region. |
d111e8f9 | 1336 | */ |
8df65168 | 1337 | for (addr = __phys_to_virt(end); |
0536bdf3 | 1338 | addr < VMALLOC_START; addr += PMD_SIZE) |
d111e8f9 RK |
1339 | pmd_clear(pmd_off_k(addr)); |
1340 | } | |
1341 | ||
1b6ba46b CM |
1342 | #ifdef CONFIG_ARM_LPAE |
1343 | /* the first page is reserved for pgd */ | |
1344 | #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ | |
1345 | PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) | |
1346 | #else | |
e73fc88e | 1347 | #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) |
1b6ba46b | 1348 | #endif |
e73fc88e | 1349 | |
d111e8f9 | 1350 | /* |
2778f620 | 1351 | * Reserve the special regions of memory |
d111e8f9 | 1352 | */ |
2778f620 | 1353 | void __init arm_mm_memblock_reserve(void) |
d111e8f9 | 1354 | { |
d111e8f9 RK |
1355 | /* |
1356 | * Reserve the page tables. These are already in use, | |
1357 | * and can only be in node 0. | |
1358 | */ | |
e73fc88e | 1359 | memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); |
d111e8f9 | 1360 | |
d111e8f9 RK |
1361 | #ifdef CONFIG_SA1111 |
1362 | /* | |
1363 | * Because of the SA1111 DMA bug, we want to preserve our | |
1364 | * precious DMA-able memory... | |
1365 | */ | |
2778f620 | 1366 | memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
d111e8f9 | 1367 | #endif |
d111e8f9 RK |
1368 | } |
1369 | ||
1370 | /* | |
0536bdf3 | 1371 | * Set up the device mappings. Since we clear out the page tables for all |
a5f4c561 SA |
1372 | * mappings above VMALLOC_START, except early fixmap, we might remove debug |
1373 | * device mappings. This means earlycon can be used to debug this function | |
1374 | * Any other function or debugging method which may touch any device _will_ | |
1375 | * crash the kernel. | |
d111e8f9 | 1376 | */ |
ff69a4c8 | 1377 | static void __init devicemaps_init(const struct machine_desc *mdesc) |
d111e8f9 RK |
1378 | { |
1379 | struct map_desc map; | |
1380 | unsigned long addr; | |
94e5a85b | 1381 | void *vectors; |
d111e8f9 RK |
1382 | |
1383 | /* | |
1384 | * Allocate the vector page early. | |
1385 | */ | |
19accfd3 | 1386 | vectors = early_alloc(PAGE_SIZE * 2); |
94e5a85b RK |
1387 | |
1388 | early_trap_init(vectors); | |
d111e8f9 | 1389 | |
a5f4c561 SA |
1390 | /* |
1391 | * Clear page table except top pmd used by early fixmaps | |
1392 | */ | |
1393 | for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE) | |
d111e8f9 RK |
1394 | pmd_clear(pmd_off_k(addr)); |
1395 | ||
7a1be318 AB |
1396 | if (__atags_pointer) { |
1397 | /* create a read-only mapping of the device tree */ | |
1398 | map.pfn = __phys_to_pfn(__atags_pointer & SECTION_MASK); | |
1399 | map.virtual = FDT_FIXED_BASE; | |
1400 | map.length = FDT_FIXED_SIZE; | |
598f0a99 | 1401 | map.type = MT_MEMORY_RO; |
7a1be318 AB |
1402 | create_mapping(&map); |
1403 | } | |
1404 | ||
d111e8f9 RK |
1405 | /* |
1406 | * Map the kernel if it is XIP. | |
1407 | * It is always first in the modulearea. | |
1408 | */ | |
1409 | #ifdef CONFIG_XIP_KERNEL | |
1410 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); | |
ab4f2ee1 | 1411 | map.virtual = MODULES_VADDR; |
02afa9a8 | 1412 | map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
d111e8f9 RK |
1413 | map.type = MT_ROM; |
1414 | create_mapping(&map); | |
1415 | #endif | |
1416 | ||
1417 | /* | |
1418 | * Map the cache flushing regions. | |
1419 | */ | |
1420 | #ifdef FLUSH_BASE | |
1421 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); | |
1422 | map.virtual = FLUSH_BASE; | |
1423 | map.length = SZ_1M; | |
1424 | map.type = MT_CACHECLEAN; | |
1425 | create_mapping(&map); | |
1426 | #endif | |
1427 | #ifdef FLUSH_BASE_MINICACHE | |
1428 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); | |
1429 | map.virtual = FLUSH_BASE_MINICACHE; | |
1430 | map.length = SZ_1M; | |
1431 | map.type = MT_MINICLEAN; | |
1432 | create_mapping(&map); | |
1433 | #endif | |
1434 | ||
1435 | /* | |
1436 | * Create a mapping for the machine vectors at the high-vectors | |
1437 | * location (0xffff0000). If we aren't using high-vectors, also | |
1438 | * create a mapping at the low-vectors virtual address. | |
1439 | */ | |
94e5a85b | 1440 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); |
d111e8f9 RK |
1441 | map.virtual = 0xffff0000; |
1442 | map.length = PAGE_SIZE; | |
a5463cd3 | 1443 | #ifdef CONFIG_KUSER_HELPERS |
d111e8f9 | 1444 | map.type = MT_HIGH_VECTORS; |
a5463cd3 RK |
1445 | #else |
1446 | map.type = MT_LOW_VECTORS; | |
1447 | #endif | |
d111e8f9 RK |
1448 | create_mapping(&map); |
1449 | ||
1450 | if (!vectors_high()) { | |
1451 | map.virtual = 0; | |
19accfd3 | 1452 | map.length = PAGE_SIZE * 2; |
d111e8f9 RK |
1453 | map.type = MT_LOW_VECTORS; |
1454 | create_mapping(&map); | |
1455 | } | |
1456 | ||
19accfd3 RK |
1457 | /* Now create a kernel read-only mapping */ |
1458 | map.pfn += 1; | |
1459 | map.virtual = 0xffff0000 + PAGE_SIZE; | |
1460 | map.length = PAGE_SIZE; | |
1461 | map.type = MT_LOW_VECTORS; | |
1462 | create_mapping(&map); | |
1463 | ||
d111e8f9 RK |
1464 | /* |
1465 | * Ask the machine support to map in the statically mapped devices. | |
1466 | */ | |
1467 | if (mdesc->map_io) | |
1468 | mdesc->map_io(); | |
bc37324e MR |
1469 | else |
1470 | debug_ll_io_init(); | |
19b52abe | 1471 | fill_pmd_gaps(); |
d111e8f9 | 1472 | |
c2794437 RH |
1473 | /* Reserve fixed i/o space in VMALLOC region */ |
1474 | pci_reserve_io(); | |
1475 | ||
d111e8f9 RK |
1476 | /* |
1477 | * Finally flush the caches and tlb to ensure that we're in a | |
1478 | * consistent state wrt the writebuffer. This also ensures that | |
1479 | * any write-allocated cache lines in the vector page are written | |
1480 | * back. After this point, we can start to touch devices again. | |
1481 | */ | |
1482 | local_flush_tlb_all(); | |
1483 | flush_cache_all(); | |
bbeb9209 LS |
1484 | |
1485 | /* Enable asynchronous aborts */ | |
9254970c | 1486 | early_abt_enable(); |
d111e8f9 RK |
1487 | } |
1488 | ||
d73cd428 NP |
1489 | static void __init kmap_init(void) |
1490 | { | |
1491 | #ifdef CONFIG_HIGHMEM | |
4bb2e27d RK |
1492 | pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), |
1493 | PKMAP_BASE, _PAGE_KERNEL_TABLE); | |
d73cd428 | 1494 | #endif |
836a2418 RH |
1495 | |
1496 | early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START, | |
1497 | _PAGE_KERNEL_TABLE); | |
d73cd428 NP |
1498 | } |
1499 | ||
a2227120 RK |
1500 | static void __init map_lowmem(void) |
1501 | { | |
b10d6bca MR |
1502 | phys_addr_t start, end; |
1503 | u64 i; | |
a2227120 RK |
1504 | |
1505 | /* Map all the lowmem memory banks. */ | |
b10d6bca | 1506 | for_each_mem_range(i, &start, &end) { |
8df65168 RK |
1507 | struct map_desc map; |
1508 | ||
6e121df1 LW |
1509 | pr_debug("map lowmem start: 0x%08llx, end: 0x%08llx\n", |
1510 | (long long)start, (long long)end); | |
c7909509 MS |
1511 | if (end > arm_lowmem_limit) |
1512 | end = arm_lowmem_limit; | |
8df65168 RK |
1513 | if (start >= end) |
1514 | break; | |
1515 | ||
6e121df1 LW |
1516 | /* |
1517 | * If our kernel image is in the VMALLOC area we need to remove | |
1518 | * the kernel physical memory from lowmem since the kernel will | |
1519 | * be mapped separately. | |
1520 | * | |
1521 | * The kernel will typically be at the very start of lowmem, | |
1522 | * but any placement relative to memory ranges is possible. | |
1523 | * | |
1524 | * If the memblock contains the kernel, we have to chisel out | |
1525 | * the kernel memory from it and map each part separately. We | |
1526 | * get 6 different theoretical cases: | |
1527 | * | |
1528 | * +--------+ +--------+ | |
1529 | * +-- start --+ +--------+ | Kernel | | Kernel | | |
1530 | * | | | Kernel | | case 2 | | case 5 | | |
1531 | * | | | case 1 | +--------+ | | +--------+ | |
1532 | * | Memory | +--------+ | | | Kernel | | |
1533 | * | range | +--------+ | | | case 6 | | |
1534 | * | | | Kernel | +--------+ | | +--------+ | |
1535 | * | | | case 3 | | Kernel | | | | |
1536 | * +-- end ----+ +--------+ | case 4 | | | | |
1537 | * +--------+ +--------+ | |
1538 | */ | |
a2227120 | 1539 | |
6e121df1 LW |
1540 | /* Case 5: kernel covers range, don't map anything, should be rare */ |
1541 | if ((start > kernel_sec_start) && (end < kernel_sec_end)) | |
1542 | break; | |
1e6b4811 | 1543 | |
6e121df1 LW |
1544 | /* Cases where the kernel is starting inside the range */ |
1545 | if ((kernel_sec_start >= start) && (kernel_sec_start <= end)) { | |
1546 | /* Case 6: kernel is embedded in the range, we need two mappings */ | |
1547 | if ((start < kernel_sec_start) && (end > kernel_sec_end)) { | |
1548 | /* Map memory below the kernel */ | |
ebd4922e RK |
1549 | map.pfn = __phys_to_pfn(start); |
1550 | map.virtual = __phys_to_virt(start); | |
6e121df1 | 1551 | map.length = kernel_sec_start - start; |
ebd4922e | 1552 | map.type = MT_MEMORY_RW; |
ebd4922e | 1553 | create_mapping(&map); |
6e121df1 LW |
1554 | /* Map memory above the kernel */ |
1555 | map.pfn = __phys_to_pfn(kernel_sec_end); | |
1556 | map.virtual = __phys_to_virt(kernel_sec_end); | |
1557 | map.length = end - kernel_sec_end; | |
ebd4922e | 1558 | map.type = MT_MEMORY_RW; |
ebd4922e | 1559 | create_mapping(&map); |
6e121df1 | 1560 | break; |
ebd4922e | 1561 | } |
6e121df1 LW |
1562 | /* Case 1: kernel and range start at the same address, should be common */ |
1563 | if (kernel_sec_start == start) | |
1564 | start = kernel_sec_end; | |
1565 | /* Case 3: kernel and range end at the same address, should be rare */ | |
1566 | if (kernel_sec_end == end) | |
1567 | end = kernel_sec_start; | |
1568 | } else if ((kernel_sec_start < start) && (kernel_sec_end > start) && (kernel_sec_end < end)) { | |
1569 | /* Case 2: kernel ends inside range, starts below it */ | |
1570 | start = kernel_sec_end; | |
1571 | } else if ((kernel_sec_start > start) && (kernel_sec_start < end) && (kernel_sec_end > end)) { | |
1572 | /* Case 4: kernel starts inside range, ends above it */ | |
1573 | end = kernel_sec_start; | |
ebd4922e | 1574 | } |
6e121df1 LW |
1575 | map.pfn = __phys_to_pfn(start); |
1576 | map.virtual = __phys_to_virt(start); | |
1577 | map.length = end - start; | |
1578 | map.type = MT_MEMORY_RW; | |
1579 | create_mapping(&map); | |
a2227120 RK |
1580 | } |
1581 | } | |
1582 | ||
6e121df1 LW |
1583 | static void __init map_kernel(void) |
1584 | { | |
1585 | /* | |
1586 | * We use the well known kernel section start and end and split the area in the | |
1587 | * middle like this: | |
1588 | * . . | |
1589 | * | RW memory | | |
1590 | * +----------------+ kernel_x_start | |
1591 | * | Executable | | |
1592 | * | kernel memory | | |
1593 | * +----------------+ kernel_x_end / kernel_nx_start | |
1594 | * | Non-executable | | |
1595 | * | kernel memory | | |
1596 | * +----------------+ kernel_nx_end | |
1597 | * | RW memory | | |
1598 | * . . | |
1599 | * | |
1600 | * Notice that we are dealing with section sized mappings here so all of this | |
1601 | * will be bumped to the closest section boundary. This means that some of the | |
1602 | * non-executable part of the kernel memory is actually mapped as executable. | |
1603 | * This will only persist until we turn on proper memory management later on | |
1604 | * and we remap the whole kernel with page granularity. | |
1605 | */ | |
1606 | phys_addr_t kernel_x_start = kernel_sec_start; | |
1607 | phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); | |
1608 | phys_addr_t kernel_nx_start = kernel_x_end; | |
1609 | phys_addr_t kernel_nx_end = kernel_sec_end; | |
1610 | struct map_desc map; | |
1611 | ||
1612 | map.pfn = __phys_to_pfn(kernel_x_start); | |
1613 | map.virtual = __phys_to_virt(kernel_x_start); | |
1614 | map.length = kernel_x_end - kernel_x_start; | |
1615 | map.type = MT_MEMORY_RWX; | |
1616 | create_mapping(&map); | |
1617 | ||
1618 | /* If the nx part is small it may end up covered by the tail of the RWX section */ | |
1619 | if (kernel_x_end == kernel_nx_end) | |
1620 | return; | |
1621 | ||
1622 | map.pfn = __phys_to_pfn(kernel_nx_start); | |
1623 | map.virtual = __phys_to_virt(kernel_nx_start); | |
1624 | map.length = kernel_nx_end - kernel_nx_start; | |
1625 | map.type = MT_MEMORY_RW; | |
1626 | create_mapping(&map); | |
1627 | } | |
1628 | ||
d8dc7fbd | 1629 | #ifdef CONFIG_ARM_PV_FIXUP |
7a1be318 | 1630 | typedef void pgtables_remap(long long offset, unsigned long pgd); |
d8dc7fbd RK |
1631 | pgtables_remap lpae_pgtables_remap_asm; |
1632 | ||
a77e0c7b SS |
1633 | /* |
1634 | * early_paging_init() recreates boot time page table setup, allowing machines | |
1635 | * to switch over to a high (>4G) address space on LPAE systems | |
1636 | */ | |
b089c31c | 1637 | static void __init early_paging_init(const struct machine_desc *mdesc) |
a77e0c7b | 1638 | { |
d8dc7fbd RK |
1639 | pgtables_remap *lpae_pgtables_remap; |
1640 | unsigned long pa_pgd; | |
727ac9ec | 1641 | u32 cr, ttbcr, tmp; |
c8ca2b4b | 1642 | long long offset; |
a77e0c7b | 1643 | |
c0b759d8 | 1644 | if (!mdesc->pv_fixup) |
a77e0c7b SS |
1645 | return; |
1646 | ||
c0b759d8 | 1647 | offset = mdesc->pv_fixup(); |
c8ca2b4b RK |
1648 | if (offset == 0) |
1649 | return; | |
a77e0c7b | 1650 | |
463dbba4 LW |
1651 | /* |
1652 | * Offset the kernel section physical offsets so that the kernel | |
1653 | * mapping will work out later on. | |
1654 | */ | |
1655 | kernel_sec_start += offset; | |
1656 | kernel_sec_end += offset; | |
1657 | ||
d8dc7fbd RK |
1658 | /* |
1659 | * Get the address of the remap function in the 1:1 identity | |
1660 | * mapping setup by the early page table assembly code. We | |
1661 | * must get this prior to the pv update. The following barrier | |
1662 | * ensures that this is complete before we fixup any P:V offsets. | |
1663 | */ | |
1664 | lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm); | |
1665 | pa_pgd = __pa(swapper_pg_dir); | |
d8dc7fbd | 1666 | barrier(); |
a77e0c7b | 1667 | |
39b74fe8 RK |
1668 | pr_info("Switching physical address space to 0x%08llx\n", |
1669 | (u64)PHYS_OFFSET + offset); | |
a77e0c7b | 1670 | |
c8ca2b4b RK |
1671 | /* Re-set the phys pfn offset, and the pv offset */ |
1672 | __pv_offset += offset; | |
1673 | __pv_phys_pfn_offset += PFN_DOWN(offset); | |
a77e0c7b SS |
1674 | |
1675 | /* Run the patch stub to update the constants */ | |
1676 | fixup_pv_table(&__pv_table_begin, | |
1677 | (&__pv_table_end - &__pv_table_begin) << 2); | |
1678 | ||
1679 | /* | |
d8dc7fbd RK |
1680 | * We changing not only the virtual to physical mapping, but also |
1681 | * the physical addresses used to access memory. We need to flush | |
1682 | * all levels of cache in the system with caching disabled to | |
1683 | * ensure that all data is written back, and nothing is prefetched | |
1684 | * into the caches. We also need to prevent the TLB walkers | |
1685 | * allocating into the caches too. Note that this is ARMv7 LPAE | |
1686 | * specific. | |
3bb70de6 | 1687 | */ |
d8dc7fbd RK |
1688 | cr = get_cr(); |
1689 | set_cr(cr & ~(CR_I | CR_C)); | |
66abdd3b | 1690 | ttbcr = cpu_get_ttbcr(); |
727ac9ec LW |
1691 | /* Disable all kind of caching of the translation table */ |
1692 | tmp = ttbcr & ~(TTBCR_ORGN0_MASK | TTBCR_IRGN0_MASK); | |
1693 | cpu_set_ttbcr(tmp); | |
a77e0c7b | 1694 | flush_cache_all(); |
3bb70de6 RK |
1695 | |
1696 | /* | |
d8dc7fbd RK |
1697 | * Fixup the page tables - this must be in the idmap region as |
1698 | * we need to disable the MMU to do this safely, and hence it | |
1699 | * needs to be assembly. It's fairly simple, as we're using the | |
1700 | * temporary tables setup by the initial assembly code. | |
3bb70de6 | 1701 | */ |
7a1be318 | 1702 | lpae_pgtables_remap(offset, pa_pgd); |
3bb70de6 | 1703 | |
d8dc7fbd | 1704 | /* Re-enable the caches and cacheable TLB walks */ |
66abdd3b | 1705 | cpu_set_ttbcr(ttbcr); |
d8dc7fbd | 1706 | set_cr(cr); |
a77e0c7b SS |
1707 | } |
1708 | ||
1709 | #else | |
1710 | ||
b089c31c | 1711 | static void __init early_paging_init(const struct machine_desc *mdesc) |
a77e0c7b | 1712 | { |
c8ca2b4b RK |
1713 | long long offset; |
1714 | ||
c0b759d8 | 1715 | if (!mdesc->pv_fixup) |
c8ca2b4b RK |
1716 | return; |
1717 | ||
c0b759d8 | 1718 | offset = mdesc->pv_fixup(); |
c8ca2b4b RK |
1719 | if (offset == 0) |
1720 | return; | |
1721 | ||
1722 | pr_crit("Physical address space modification is only to support Keystone2.\n"); | |
1723 | pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n"); | |
1724 | pr_crit("feature. Your kernel may crash now, have a good day.\n"); | |
1725 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); | |
a77e0c7b SS |
1726 | } |
1727 | ||
1728 | #endif | |
1729 | ||
a5f4c561 SA |
1730 | static void __init early_fixmap_shutdown(void) |
1731 | { | |
1732 | int i; | |
1733 | unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1); | |
1734 | ||
1735 | pte_offset_fixmap = pte_offset_late_fixmap; | |
1736 | pmd_clear(fixmap_pmd(va)); | |
1737 | local_flush_tlb_kernel_page(va); | |
1738 | ||
1739 | for (i = 0; i < __end_of_permanent_fixed_addresses; i++) { | |
1740 | pte_t *pte; | |
1741 | struct map_desc map; | |
1742 | ||
1743 | map.virtual = fix_to_virt(i); | |
1744 | pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual); | |
1745 | ||
1746 | /* Only i/o device mappings are supported ATM */ | |
1747 | if (pte_none(*pte) || | |
1748 | (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED) | |
1749 | continue; | |
1750 | ||
1751 | map.pfn = pte_pfn(*pte); | |
1752 | map.type = MT_DEVICE; | |
1753 | map.length = PAGE_SIZE; | |
1754 | ||
1755 | create_mapping(&map); | |
1756 | } | |
1757 | } | |
1758 | ||
d111e8f9 RK |
1759 | /* |
1760 | * paging_init() sets up the page tables, initialises the zone memory | |
1761 | * maps, and sets up the zero page, bad page and bad page tables. | |
1762 | */ | |
ff69a4c8 | 1763 | void __init paging_init(const struct machine_desc *mdesc) |
d111e8f9 RK |
1764 | { |
1765 | void *zero_page; | |
1766 | ||
463dbba4 | 1767 | pr_debug("physical kernel sections: 0x%08llx-0x%08llx\n", |
6e121df1 LW |
1768 | kernel_sec_start, kernel_sec_end); |
1769 | ||
4b5f32ce | 1770 | prepare_page_table(); |
a2227120 | 1771 | map_lowmem(); |
3de1f52a | 1772 | memblock_set_current_limit(arm_lowmem_limit); |
6e121df1 LW |
1773 | pr_debug("lowmem limit is %08llx\n", (long long)arm_lowmem_limit); |
1774 | /* | |
1775 | * After this point early_alloc(), i.e. the memblock allocator, can | |
1776 | * be used | |
1777 | */ | |
1778 | map_kernel(); | |
c7909509 | 1779 | dma_contiguous_remap(); |
a5f4c561 | 1780 | early_fixmap_shutdown(); |
d111e8f9 | 1781 | devicemaps_init(mdesc); |
d73cd428 | 1782 | kmap_init(); |
de40614e | 1783 | tcm_init(); |
d111e8f9 RK |
1784 | |
1785 | top_pmd = pmd_off_k(0xffff0000); | |
1786 | ||
3abe9d33 RK |
1787 | /* allocate the zero page. */ |
1788 | zero_page = early_alloc(PAGE_SIZE); | |
2778f620 | 1789 | |
8d717a52 | 1790 | bootmem_init(); |
2778f620 | 1791 | |
d111e8f9 | 1792 | empty_zero_page = virt_to_page(zero_page); |
8b5989f3 | 1793 | __flush_dcache_folio(NULL, page_folio(empty_zero_page)); |
d111e8f9 | 1794 | } |
b089c31c JM |
1795 | |
1796 | void __init early_mm_init(const struct machine_desc *mdesc) | |
1797 | { | |
1798 | build_mem_type_table(); | |
1799 | early_paging_init(mdesc); | |
1800 | } | |
78e7c5af | 1801 | |
8b5989f3 MWO |
1802 | void set_ptes(struct mm_struct *mm, unsigned long addr, |
1803 | pte_t *ptep, pte_t pteval, unsigned int nr) | |
78e7c5af AK |
1804 | { |
1805 | unsigned long ext = 0; | |
1806 | ||
1807 | if (addr < TASK_SIZE && pte_valid_user(pteval)) { | |
1808 | if (!pte_special(pteval)) | |
1809 | __sync_icache_dcache(pteval); | |
1810 | ext |= PTE_EXT_NG; | |
1811 | } | |
1812 | ||
8b5989f3 MWO |
1813 | for (;;) { |
1814 | set_pte_ext(ptep, pteval, ext); | |
1815 | if (--nr == 0) | |
1816 | break; | |
1817 | ptep++; | |
e5ea320a | 1818 | pteval = pte_next_pfn(pteval); |
8b5989f3 | 1819 | } |
78e7c5af | 1820 | } |