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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d111e8f9 RK |
2 | /* |
3 | * linux/arch/arm/mm/mmu.c | |
4 | * | |
5 | * Copyright (C) 1995-2005 Russell King | |
d111e8f9 | 6 | */ |
ae8f1541 | 7 | #include <linux/module.h> |
d111e8f9 RK |
8 | #include <linux/kernel.h> |
9 | #include <linux/errno.h> | |
10 | #include <linux/init.h> | |
d111e8f9 RK |
11 | #include <linux/mman.h> |
12 | #include <linux/nodemask.h> | |
2778f620 | 13 | #include <linux/memblock.h> |
d907387c | 14 | #include <linux/fs.h> |
0536bdf3 | 15 | #include <linux/vmalloc.h> |
158e8bfe | 16 | #include <linux/sizes.h> |
d111e8f9 | 17 | |
15d07dc9 | 18 | #include <asm/cp15.h> |
0ba8b9b2 | 19 | #include <asm/cputype.h> |
37efe642 | 20 | #include <asm/sections.h> |
3f973e22 | 21 | #include <asm/cachetype.h> |
99b4ac9a | 22 | #include <asm/fixmap.h> |
ebd4922e | 23 | #include <asm/sections.h> |
d111e8f9 | 24 | #include <asm/setup.h> |
e616c591 | 25 | #include <asm/smp_plat.h> |
d111e8f9 | 26 | #include <asm/tlb.h> |
d73cd428 | 27 | #include <asm/highmem.h> |
9f97da78 | 28 | #include <asm/system_info.h> |
247055aa | 29 | #include <asm/traps.h> |
a77e0c7b SS |
30 | #include <asm/procinfo.h> |
31 | #include <asm/memory.h> | |
d111e8f9 RK |
32 | |
33 | #include <asm/mach/arch.h> | |
34 | #include <asm/mach/map.h> | |
c2794437 | 35 | #include <asm/mach/pci.h> |
a05e54c1 | 36 | #include <asm/fixmap.h> |
d111e8f9 | 37 | |
9254970c | 38 | #include "fault.h" |
d111e8f9 | 39 | #include "mm.h" |
de40614e | 40 | #include "tcm.h" |
d111e8f9 | 41 | |
d111e8f9 RK |
42 | /* |
43 | * empty_zero_page is a special page that is used for | |
44 | * zero-initialized data and COW. | |
45 | */ | |
46 | struct page *empty_zero_page; | |
3653f3ab | 47 | EXPORT_SYMBOL(empty_zero_page); |
d111e8f9 RK |
48 | |
49 | /* | |
50 | * The pmd table for the upper-most set of pages. | |
51 | */ | |
52 | pmd_t *top_pmd; | |
53 | ||
1d4d3715 JL |
54 | pmdval_t user_pmd_table = _PAGE_USER_TABLE; |
55 | ||
ae8f1541 RK |
56 | #define CPOLICY_UNCACHED 0 |
57 | #define CPOLICY_BUFFERED 1 | |
58 | #define CPOLICY_WRITETHROUGH 2 | |
59 | #define CPOLICY_WRITEBACK 3 | |
60 | #define CPOLICY_WRITEALLOC 4 | |
61 | ||
62 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; | |
63 | static unsigned int ecc_mask __initdata = 0; | |
44b18693 | 64 | pgprot_t pgprot_user; |
ae8f1541 | 65 | pgprot_t pgprot_kernel; |
cc577c26 CD |
66 | pgprot_t pgprot_hyp_device; |
67 | pgprot_t pgprot_s2; | |
68 | pgprot_t pgprot_s2_device; | |
ae8f1541 | 69 | |
44b18693 | 70 | EXPORT_SYMBOL(pgprot_user); |
ae8f1541 RK |
71 | EXPORT_SYMBOL(pgprot_kernel); |
72 | ||
73 | struct cachepolicy { | |
74 | const char policy[16]; | |
75 | unsigned int cr_mask; | |
442e70c0 | 76 | pmdval_t pmd; |
f6e3354d | 77 | pteval_t pte; |
cc577c26 | 78 | pteval_t pte_s2; |
ae8f1541 RK |
79 | }; |
80 | ||
cc577c26 CD |
81 | #ifdef CONFIG_ARM_LPAE |
82 | #define s2_policy(policy) policy | |
83 | #else | |
84 | #define s2_policy(policy) 0 | |
85 | #endif | |
86 | ||
cf763e4e MZ |
87 | unsigned long kimage_voffset __ro_after_init; |
88 | ||
ae8f1541 RK |
89 | static struct cachepolicy cache_policies[] __initdata = { |
90 | { | |
91 | .policy = "uncached", | |
92 | .cr_mask = CR_W|CR_C, | |
93 | .pmd = PMD_SECT_UNCACHED, | |
bb30f36f | 94 | .pte = L_PTE_MT_UNCACHED, |
cc577c26 | 95 | .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), |
ae8f1541 RK |
96 | }, { |
97 | .policy = "buffered", | |
98 | .cr_mask = CR_C, | |
99 | .pmd = PMD_SECT_BUFFERED, | |
bb30f36f | 100 | .pte = L_PTE_MT_BUFFERABLE, |
cc577c26 | 101 | .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), |
ae8f1541 RK |
102 | }, { |
103 | .policy = "writethrough", | |
104 | .cr_mask = 0, | |
105 | .pmd = PMD_SECT_WT, | |
bb30f36f | 106 | .pte = L_PTE_MT_WRITETHROUGH, |
cc577c26 | 107 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH), |
ae8f1541 RK |
108 | }, { |
109 | .policy = "writeback", | |
110 | .cr_mask = 0, | |
111 | .pmd = PMD_SECT_WB, | |
bb30f36f | 112 | .pte = L_PTE_MT_WRITEBACK, |
cc577c26 | 113 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), |
ae8f1541 RK |
114 | }, { |
115 | .policy = "writealloc", | |
116 | .cr_mask = 0, | |
117 | .pmd = PMD_SECT_WBWA, | |
bb30f36f | 118 | .pte = L_PTE_MT_WRITEALLOC, |
cc577c26 | 119 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), |
ae8f1541 RK |
120 | } |
121 | }; | |
122 | ||
b849a60e | 123 | #ifdef CONFIG_CPU_CP15 |
20e7e364 RK |
124 | static unsigned long initial_pmd_value __initdata = 0; |
125 | ||
ae8f1541 | 126 | /* |
ca8f0b0a RK |
127 | * Initialise the cache_policy variable with the initial state specified |
128 | * via the "pmd" value. This is used to ensure that on ARMv6 and later, | |
129 | * the C code sets the page tables up with the same policy as the head | |
130 | * assembly code, which avoids an illegal state where the TLBs can get | |
131 | * confused. See comments in early_cachepolicy() for more information. | |
ae8f1541 | 132 | */ |
ca8f0b0a | 133 | void __init init_default_cache_policy(unsigned long pmd) |
ae8f1541 RK |
134 | { |
135 | int i; | |
136 | ||
20e7e364 RK |
137 | initial_pmd_value = pmd; |
138 | ||
6b3142b2 | 139 | pmd &= PMD_SECT_CACHE_MASK; |
ca8f0b0a RK |
140 | |
141 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) | |
142 | if (cache_policies[i].pmd == pmd) { | |
143 | cachepolicy = i; | |
144 | break; | |
145 | } | |
146 | ||
147 | if (i == ARRAY_SIZE(cache_policies)) | |
148 | pr_err("ERROR: could not find cache policy\n"); | |
149 | } | |
150 | ||
151 | /* | |
152 | * These are useful for identifying cache coherency problems by allowing | |
153 | * the cache or the cache and writebuffer to be turned off. (Note: the | |
154 | * write buffer should not be on and the cache off). | |
155 | */ | |
156 | static int __init early_cachepolicy(char *p) | |
157 | { | |
158 | int i, selected = -1; | |
159 | ||
ae8f1541 RK |
160 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { |
161 | int len = strlen(cache_policies[i].policy); | |
162 | ||
2b0d8c25 | 163 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
ca8f0b0a | 164 | selected = i; |
ae8f1541 RK |
165 | break; |
166 | } | |
167 | } | |
ca8f0b0a RK |
168 | |
169 | if (selected == -1) | |
170 | pr_err("ERROR: unknown or unsupported cache policy\n"); | |
171 | ||
4b46d641 RK |
172 | /* |
173 | * This restriction is partly to do with the way we boot; it is | |
174 | * unpredictable to have memory mapped using two different sets of | |
175 | * memory attributes (shared, type, and cache attribs). We can not | |
176 | * change these attributes once the initial assembly has setup the | |
177 | * page tables. | |
178 | */ | |
ca8f0b0a RK |
179 | if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) { |
180 | pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n", | |
181 | cache_policies[cachepolicy].policy); | |
182 | return 0; | |
183 | } | |
184 | ||
185 | if (selected != cachepolicy) { | |
186 | unsigned long cr = __clear_cr(cache_policies[selected].cr_mask); | |
187 | cachepolicy = selected; | |
188 | flush_cache_all(); | |
189 | set_cr(cr); | |
11179d8c | 190 | } |
2b0d8c25 | 191 | return 0; |
ae8f1541 | 192 | } |
2b0d8c25 | 193 | early_param("cachepolicy", early_cachepolicy); |
ae8f1541 | 194 | |
2b0d8c25 | 195 | static int __init early_nocache(char *__unused) |
ae8f1541 RK |
196 | { |
197 | char *p = "buffered"; | |
4ed89f22 | 198 | pr_warn("nocache is deprecated; use cachepolicy=%s\n", p); |
2b0d8c25 JK |
199 | early_cachepolicy(p); |
200 | return 0; | |
ae8f1541 | 201 | } |
2b0d8c25 | 202 | early_param("nocache", early_nocache); |
ae8f1541 | 203 | |
2b0d8c25 | 204 | static int __init early_nowrite(char *__unused) |
ae8f1541 RK |
205 | { |
206 | char *p = "uncached"; | |
4ed89f22 | 207 | pr_warn("nowb is deprecated; use cachepolicy=%s\n", p); |
2b0d8c25 JK |
208 | early_cachepolicy(p); |
209 | return 0; | |
ae8f1541 | 210 | } |
2b0d8c25 | 211 | early_param("nowb", early_nowrite); |
ae8f1541 | 212 | |
1b6ba46b | 213 | #ifndef CONFIG_ARM_LPAE |
2b0d8c25 | 214 | static int __init early_ecc(char *p) |
ae8f1541 | 215 | { |
2b0d8c25 | 216 | if (memcmp(p, "on", 2) == 0) |
ae8f1541 | 217 | ecc_mask = PMD_PROTECTION; |
2b0d8c25 | 218 | else if (memcmp(p, "off", 3) == 0) |
ae8f1541 | 219 | ecc_mask = 0; |
2b0d8c25 | 220 | return 0; |
ae8f1541 | 221 | } |
2b0d8c25 | 222 | early_param("ecc", early_ecc); |
1b6ba46b | 223 | #endif |
ae8f1541 | 224 | |
b849a60e UKK |
225 | #else /* ifdef CONFIG_CPU_CP15 */ |
226 | ||
227 | static int __init early_cachepolicy(char *p) | |
228 | { | |
8b521cb2 | 229 | pr_warn("cachepolicy kernel parameter not supported without cp15\n"); |
b849a60e UKK |
230 | } |
231 | early_param("cachepolicy", early_cachepolicy); | |
232 | ||
233 | static int __init noalign_setup(char *__unused) | |
234 | { | |
8b521cb2 | 235 | pr_warn("noalign kernel parameter not supported without cp15\n"); |
b849a60e UKK |
236 | } |
237 | __setup("noalign", noalign_setup); | |
238 | ||
239 | #endif /* ifdef CONFIG_CPU_CP15 / else */ | |
240 | ||
36bb94ba | 241 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN |
4d9c5b89 | 242 | #define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE |
b1cce6b1 | 243 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
0af92bef | 244 | |
7619751f | 245 | static struct mem_type mem_types[] __ro_after_init = { |
0af92bef | 246 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
bb30f36f RK |
247 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
248 | L_PTE_SHARED, | |
4d9c5b89 CD |
249 | .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) | |
250 | s2_policy(L_PTE_S2_MT_DEV_SHARED) | | |
251 | L_PTE_SHARED, | |
0af92bef | 252 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 253 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
0af92bef RK |
254 | .domain = DOMAIN_IO, |
255 | }, | |
256 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ | |
bb30f36f | 257 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
0af92bef | 258 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 259 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef RK |
260 | .domain = DOMAIN_IO, |
261 | }, | |
262 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ | |
bb30f36f | 263 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
0af92bef RK |
264 | .prot_l1 = PMD_TYPE_TABLE, |
265 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, | |
266 | .domain = DOMAIN_IO, | |
c2794437 | 267 | }, |
1ad77a87 | 268 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
bb30f36f | 269 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
0af92bef | 270 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 271 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef | 272 | .domain = DOMAIN_IO, |
ae8f1541 | 273 | }, |
ebb4c658 RK |
274 | [MT_UNCACHED] = { |
275 | .prot_pte = PROT_PTE_DEVICE, | |
276 | .prot_l1 = PMD_TYPE_TABLE, | |
277 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
278 | .domain = DOMAIN_IO, | |
279 | }, | |
ae8f1541 | 280 | [MT_CACHECLEAN] = { |
9ef79635 | 281 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
ae8f1541 RK |
282 | .domain = DOMAIN_KERNEL, |
283 | }, | |
1b6ba46b | 284 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 | 285 | [MT_MINICLEAN] = { |
9ef79635 | 286 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
ae8f1541 RK |
287 | .domain = DOMAIN_KERNEL, |
288 | }, | |
1b6ba46b | 289 | #endif |
ae8f1541 RK |
290 | [MT_LOW_VECTORS] = { |
291 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 292 | L_PTE_RDONLY, |
ae8f1541 | 293 | .prot_l1 = PMD_TYPE_TABLE, |
a02d8dfd | 294 | .domain = DOMAIN_VECTORS, |
ae8f1541 RK |
295 | }, |
296 | [MT_HIGH_VECTORS] = { | |
297 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 298 | L_PTE_USER | L_PTE_RDONLY, |
ae8f1541 | 299 | .prot_l1 = PMD_TYPE_TABLE, |
a02d8dfd | 300 | .domain = DOMAIN_VECTORS, |
ae8f1541 | 301 | }, |
2e2c9de2 | 302 | [MT_MEMORY_RWX] = { |
36bb94ba | 303 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
f1a2481c | 304 | .prot_l1 = PMD_TYPE_TABLE, |
9ef79635 | 305 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
ae8f1541 RK |
306 | .domain = DOMAIN_KERNEL, |
307 | }, | |
ebd4922e RK |
308 | [MT_MEMORY_RW] = { |
309 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
310 | L_PTE_XN, | |
311 | .prot_l1 = PMD_TYPE_TABLE, | |
312 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, | |
313 | .domain = DOMAIN_KERNEL, | |
314 | }, | |
ae8f1541 | 315 | [MT_ROM] = { |
9ef79635 | 316 | .prot_sect = PMD_TYPE_SECT, |
ae8f1541 RK |
317 | .domain = DOMAIN_KERNEL, |
318 | }, | |
2e2c9de2 | 319 | [MT_MEMORY_RWX_NONCACHED] = { |
f1a2481c | 320 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 321 | L_PTE_MT_BUFFERABLE, |
f1a2481c | 322 | .prot_l1 = PMD_TYPE_TABLE, |
e4707dd3 PW |
323 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
324 | .domain = DOMAIN_KERNEL, | |
325 | }, | |
2e2c9de2 | 326 | [MT_MEMORY_RW_DTCM] = { |
f444fce3 | 327 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 328 | L_PTE_XN, |
f444fce3 LW |
329 | .prot_l1 = PMD_TYPE_TABLE, |
330 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
331 | .domain = DOMAIN_KERNEL, | |
cb9d7707 | 332 | }, |
2e2c9de2 | 333 | [MT_MEMORY_RWX_ITCM] = { |
36bb94ba | 334 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
cb9d7707 | 335 | .prot_l1 = PMD_TYPE_TABLE, |
f444fce3 | 336 | .domain = DOMAIN_KERNEL, |
cb9d7707 | 337 | }, |
2e2c9de2 | 338 | [MT_MEMORY_RW_SO] = { |
8fb54284 | 339 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
93d5bf07 | 340 | L_PTE_MT_UNCACHED | L_PTE_XN, |
8fb54284 SS |
341 | .prot_l1 = PMD_TYPE_TABLE, |
342 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | | |
343 | PMD_SECT_UNCACHED | PMD_SECT_XN, | |
344 | .domain = DOMAIN_KERNEL, | |
345 | }, | |
c7909509 | 346 | [MT_MEMORY_DMA_READY] = { |
71b55663 RK |
347 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
348 | L_PTE_XN, | |
c7909509 MS |
349 | .prot_l1 = PMD_TYPE_TABLE, |
350 | .domain = DOMAIN_KERNEL, | |
351 | }, | |
ae8f1541 RK |
352 | }; |
353 | ||
b29e9f5e RK |
354 | const struct mem_type *get_mem_type(unsigned int type) |
355 | { | |
356 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; | |
357 | } | |
69d3a84a | 358 | EXPORT_SYMBOL(get_mem_type); |
b29e9f5e | 359 | |
a5f4c561 SA |
360 | static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr); |
361 | ||
362 | static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS] | |
363 | __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata; | |
364 | ||
365 | static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr) | |
366 | { | |
367 | return &bm_pte[pte_index(addr)]; | |
368 | } | |
369 | ||
370 | static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr) | |
371 | { | |
372 | return pte_offset_kernel(dir, addr); | |
373 | } | |
374 | ||
375 | static inline pmd_t * __init fixmap_pmd(unsigned long addr) | |
376 | { | |
377 | pgd_t *pgd = pgd_offset_k(addr); | |
378 | pud_t *pud = pud_offset(pgd, addr); | |
379 | pmd_t *pmd = pmd_offset(pud, addr); | |
380 | ||
381 | return pmd; | |
382 | } | |
383 | ||
384 | void __init early_fixmap_init(void) | |
385 | { | |
386 | pmd_t *pmd; | |
387 | ||
388 | /* | |
389 | * The early fixmap range spans multiple pmds, for which | |
390 | * we are not prepared: | |
391 | */ | |
2937367b | 392 | BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT) |
a5f4c561 SA |
393 | != FIXADDR_TOP >> PMD_SHIFT); |
394 | ||
395 | pmd = fixmap_pmd(FIXADDR_TOP); | |
396 | pmd_populate_kernel(&init_mm, pmd, bm_pte); | |
397 | ||
398 | pte_offset_fixmap = pte_offset_early_fixmap; | |
399 | } | |
400 | ||
99b4ac9a KC |
401 | /* |
402 | * To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range(). | |
403 | * As a result, this can only be called with preemption disabled, as under | |
404 | * stop_machine(). | |
405 | */ | |
406 | void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) | |
407 | { | |
408 | unsigned long vaddr = __fix_to_virt(idx); | |
a5f4c561 | 409 | pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr); |
99b4ac9a KC |
410 | |
411 | /* Make sure fixmap region does not exceed available allocation. */ | |
412 | BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) > | |
413 | FIXADDR_END); | |
414 | BUG_ON(idx >= __end_of_fixed_addresses); | |
415 | ||
b089c31c JM |
416 | /* we only support device mappings until pgprot_kernel has been set */ |
417 | if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) && | |
418 | pgprot_val(pgprot_kernel) == 0)) | |
419 | return; | |
420 | ||
99b4ac9a KC |
421 | if (pgprot_val(prot)) |
422 | set_pte_at(NULL, vaddr, pte, | |
423 | pfn_pte(phys >> PAGE_SHIFT, prot)); | |
424 | else | |
425 | pte_clear(NULL, vaddr, pte); | |
426 | local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE); | |
427 | } | |
428 | ||
ae8f1541 RK |
429 | /* |
430 | * Adjust the PMD section entries according to the CPU in use. | |
431 | */ | |
432 | static void __init build_mem_type_table(void) | |
433 | { | |
434 | struct cachepolicy *cp; | |
435 | unsigned int cr = get_cr(); | |
442e70c0 | 436 | pteval_t user_pgprot, kern_pgprot, vecs_pgprot; |
cc577c26 | 437 | pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot; |
ae8f1541 RK |
438 | int cpu_arch = cpu_architecture(); |
439 | int i; | |
440 | ||
11179d8c | 441 | if (cpu_arch < CPU_ARCH_ARMv6) { |
ae8f1541 | 442 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
11179d8c CM |
443 | if (cachepolicy > CPOLICY_BUFFERED) |
444 | cachepolicy = CPOLICY_BUFFERED; | |
ae8f1541 | 445 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
11179d8c CM |
446 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
447 | cachepolicy = CPOLICY_WRITETHROUGH; | |
ae8f1541 | 448 | #endif |
11179d8c | 449 | } |
ae8f1541 RK |
450 | if (cpu_arch < CPU_ARCH_ARMv5) { |
451 | if (cachepolicy >= CPOLICY_WRITEALLOC) | |
452 | cachepolicy = CPOLICY_WRITEBACK; | |
453 | ecc_mask = 0; | |
454 | } | |
ca8f0b0a | 455 | |
20e7e364 RK |
456 | if (is_smp()) { |
457 | if (cachepolicy != CPOLICY_WRITEALLOC) { | |
458 | pr_warn("Forcing write-allocate cache policy for SMP\n"); | |
459 | cachepolicy = CPOLICY_WRITEALLOC; | |
460 | } | |
461 | if (!(initial_pmd_value & PMD_SECT_S)) { | |
462 | pr_warn("Forcing shared mappings for SMP\n"); | |
463 | initial_pmd_value |= PMD_SECT_S; | |
464 | } | |
ca8f0b0a | 465 | } |
ae8f1541 | 466 | |
1ad77a87 | 467 | /* |
b1cce6b1 RK |
468 | * Strip out features not present on earlier architectures. |
469 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those | |
470 | * without extended page tables don't have the 'Shared' bit. | |
1ad77a87 | 471 | */ |
b1cce6b1 RK |
472 | if (cpu_arch < CPU_ARCH_ARMv5) |
473 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
474 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); | |
475 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) | |
476 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
477 | mem_types[i].prot_sect &= ~PMD_SECT_S; | |
ae8f1541 RK |
478 | |
479 | /* | |
b1cce6b1 RK |
480 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
481 | * "update-able on write" bit on ARM610). However, Xscale and | |
482 | * Xscale3 require this bit to be cleared. | |
ae8f1541 | 483 | */ |
d33c43ac | 484 | if (cpu_is_xscale_family()) { |
9ef79635 | 485 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
ae8f1541 | 486 | mem_types[i].prot_sect &= ~PMD_BIT4; |
9ef79635 RK |
487 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
488 | } | |
489 | } else if (cpu_arch < CPU_ARCH_ARMv6) { | |
490 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 RK |
491 | if (mem_types[i].prot_l1) |
492 | mem_types[i].prot_l1 |= PMD_BIT4; | |
9ef79635 RK |
493 | if (mem_types[i].prot_sect) |
494 | mem_types[i].prot_sect |= PMD_BIT4; | |
495 | } | |
496 | } | |
ae8f1541 | 497 | |
b1cce6b1 RK |
498 | /* |
499 | * Mark the device areas according to the CPU/architecture. | |
500 | */ | |
501 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { | |
502 | if (!cpu_is_xsc3()) { | |
503 | /* | |
504 | * Mark device regions on ARMv6+ as execute-never | |
505 | * to prevent speculative instruction fetches. | |
506 | */ | |
507 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; | |
508 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; | |
509 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; | |
510 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; | |
ebd4922e RK |
511 | |
512 | /* Also setup NX memory mapping */ | |
513 | mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN; | |
b1cce6b1 RK |
514 | } |
515 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
516 | /* | |
517 | * For ARMv7 with TEX remapping, | |
518 | * - shared device is SXCB=1100 | |
519 | * - nonshared device is SXCB=0100 | |
520 | * - write combine device mem is SXCB=0001 | |
521 | * (Uncached Normal memory) | |
522 | */ | |
523 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); | |
524 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); | |
525 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
526 | } else if (cpu_is_xsc3()) { | |
527 | /* | |
528 | * For Xscale3, | |
529 | * - shared device is TEXCB=00101 | |
530 | * - nonshared device is TEXCB=01000 | |
531 | * - write combine device mem is TEXCB=00100 | |
532 | * (Inner/Outer Uncacheable in xsc3 parlance) | |
533 | */ | |
534 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; | |
535 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
536 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
537 | } else { | |
538 | /* | |
539 | * For ARMv6 and ARMv7 without TEX remapping, | |
540 | * - shared device is TEXCB=00001 | |
541 | * - nonshared device is TEXCB=01000 | |
542 | * - write combine device mem is TEXCB=00100 | |
543 | * (Uncached Normal in ARMv6 parlance). | |
544 | */ | |
545 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; | |
546 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
547 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
548 | } | |
549 | } else { | |
550 | /* | |
551 | * On others, write combining is "Uncached/Buffered" | |
552 | */ | |
553 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
554 | } | |
555 | ||
556 | /* | |
557 | * Now deal with the memory-type mappings | |
558 | */ | |
ae8f1541 | 559 | cp = &cache_policies[cachepolicy]; |
bb30f36f | 560 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
cc577c26 | 561 | s2_pgprot = cp->pte_s2; |
4d9c5b89 CD |
562 | hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte; |
563 | s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2; | |
bb30f36f | 564 | |
1d4d3715 | 565 | #ifndef CONFIG_ARM_LPAE |
b6ccb980 WD |
566 | /* |
567 | * We don't use domains on ARMv6 (since this causes problems with | |
568 | * v6/v7 kernels), so we must use a separate memory type for user | |
569 | * r/o, kernel r/w to map the vectors page. | |
570 | */ | |
b6ccb980 WD |
571 | if (cpu_arch == CPU_ARCH_ARMv6) |
572 | vecs_pgprot |= L_PTE_MT_VECTORS; | |
1d4d3715 JL |
573 | |
574 | /* | |
575 | * Check is it with support for the PXN bit | |
576 | * in the Short-descriptor translation table format descriptors. | |
577 | */ | |
578 | if (cpu_arch == CPU_ARCH_ARMv7 && | |
ad84f56b | 579 | (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) { |
1d4d3715 JL |
580 | user_pmd_table |= PMD_PXNTABLE; |
581 | } | |
b6ccb980 | 582 | #endif |
bb30f36f | 583 | |
ae8f1541 RK |
584 | /* |
585 | * ARMv6 and above have extended page tables. | |
586 | */ | |
587 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { | |
1b6ba46b | 588 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
589 | /* |
590 | * Mark cache clean areas and XIP ROM read only | |
591 | * from SVC mode and no access from userspace. | |
592 | */ | |
593 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
594 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
595 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
1b6ba46b | 596 | #endif |
ae8f1541 | 597 | |
20e7e364 RK |
598 | /* |
599 | * If the initial page tables were created with the S bit | |
600 | * set, then we need to do the same here for the same | |
601 | * reasons given in early_cachepolicy(). | |
602 | */ | |
603 | if (initial_pmd_value & PMD_SECT_S) { | |
f00ec48f RK |
604 | user_pgprot |= L_PTE_SHARED; |
605 | kern_pgprot |= L_PTE_SHARED; | |
606 | vecs_pgprot |= L_PTE_SHARED; | |
cc577c26 | 607 | s2_pgprot |= L_PTE_SHARED; |
f00ec48f RK |
608 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; |
609 | mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; | |
610 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; | |
611 | mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; | |
2e2c9de2 RK |
612 | mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S; |
613 | mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED; | |
ebd4922e RK |
614 | mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S; |
615 | mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED; | |
c7909509 | 616 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; |
2e2c9de2 RK |
617 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S; |
618 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED; | |
f00ec48f | 619 | } |
ae8f1541 RK |
620 | } |
621 | ||
e4707dd3 PW |
622 | /* |
623 | * Non-cacheable Normal - intended for memory areas that must | |
624 | * not cause dirty cache line writebacks when used | |
625 | */ | |
626 | if (cpu_arch >= CPU_ARCH_ARMv6) { | |
627 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
628 | /* Non-cacheable Normal is XCB = 001 */ | |
2e2c9de2 | 629 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= |
e4707dd3 PW |
630 | PMD_SECT_BUFFERED; |
631 | } else { | |
632 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | |
2e2c9de2 | 633 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= |
e4707dd3 PW |
634 | PMD_SECT_TEX(1); |
635 | } | |
636 | } else { | |
2e2c9de2 | 637 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; |
e4707dd3 PW |
638 | } |
639 | ||
1b6ba46b CM |
640 | #ifdef CONFIG_ARM_LPAE |
641 | /* | |
642 | * Do not generate access flag faults for the kernel mappings. | |
643 | */ | |
644 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
645 | mem_types[i].prot_pte |= PTE_EXT_AF; | |
1a3abcf4 VA |
646 | if (mem_types[i].prot_sect) |
647 | mem_types[i].prot_sect |= PMD_SECT_AF; | |
1b6ba46b CM |
648 | } |
649 | kern_pgprot |= PTE_EXT_AF; | |
650 | vecs_pgprot |= PTE_EXT_AF; | |
1d4d3715 JL |
651 | |
652 | /* | |
653 | * Set PXN for user mappings | |
654 | */ | |
655 | user_pgprot |= PTE_EXT_PXN; | |
1b6ba46b CM |
656 | #endif |
657 | ||
ae8f1541 | 658 | for (i = 0; i < 16; i++) { |
864aa04c | 659 | pteval_t v = pgprot_val(protection_map[i]); |
bb30f36f | 660 | protection_map[i] = __pgprot(v | user_pgprot); |
ae8f1541 RK |
661 | } |
662 | ||
bb30f36f RK |
663 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
664 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; | |
ae8f1541 | 665 | |
44b18693 | 666 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
ae8f1541 | 667 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
36bb94ba | 668 | L_PTE_DIRTY | kern_pgprot); |
cc577c26 CD |
669 | pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot); |
670 | pgprot_s2_device = __pgprot(s2_device_pgprot); | |
671 | pgprot_hyp_device = __pgprot(hyp_device_pgprot); | |
ae8f1541 RK |
672 | |
673 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | |
674 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | |
2e2c9de2 RK |
675 | mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd; |
676 | mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; | |
ebd4922e RK |
677 | mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; |
678 | mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; | |
c7909509 | 679 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; |
2e2c9de2 | 680 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; |
ae8f1541 RK |
681 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
682 | ||
683 | switch (cp->pmd) { | |
684 | case PMD_SECT_WT: | |
685 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; | |
686 | break; | |
687 | case PMD_SECT_WB: | |
688 | case PMD_SECT_WBWA: | |
689 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; | |
690 | break; | |
691 | } | |
905b5797 MS |
692 | pr_info("Memory policy: %sData cache %s\n", |
693 | ecc_mask ? "ECC enabled, " : "", cp->policy); | |
2497f0a8 RK |
694 | |
695 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
696 | struct mem_type *t = &mem_types[i]; | |
697 | if (t->prot_l1) | |
698 | t->prot_l1 |= PMD_DOMAIN(t->domain); | |
699 | if (t->prot_sect) | |
700 | t->prot_sect |= PMD_DOMAIN(t->domain); | |
701 | } | |
ae8f1541 RK |
702 | } |
703 | ||
d907387c CM |
704 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE |
705 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
706 | unsigned long size, pgprot_t vma_prot) | |
707 | { | |
708 | if (!pfn_valid(pfn)) | |
709 | return pgprot_noncached(vma_prot); | |
710 | else if (file->f_flags & O_SYNC) | |
711 | return pgprot_writecombine(vma_prot); | |
712 | return vma_prot; | |
713 | } | |
714 | EXPORT_SYMBOL(phys_mem_access_prot); | |
715 | #endif | |
716 | ||
ae8f1541 RK |
717 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
718 | ||
0536bdf3 NP |
719 | static void __init *early_alloc(unsigned long sz) |
720 | { | |
8a7f97b9 MR |
721 | void *ptr = memblock_alloc(sz, sz); |
722 | ||
723 | if (!ptr) | |
724 | panic("%s: Failed to allocate %lu bytes align=0x%lx\n", | |
725 | __func__, sz, sz); | |
726 | ||
727 | return ptr; | |
0536bdf3 NP |
728 | } |
729 | ||
c7936206 AB |
730 | static void *__init late_alloc(unsigned long sz) |
731 | { | |
28bcf593 | 732 | void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz)); |
c7936206 | 733 | |
b4ed71f5 | 734 | if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr))) |
61444cde | 735 | BUG(); |
c7936206 AB |
736 | return ptr; |
737 | } | |
738 | ||
3ed3a4f0 | 739 | static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr, |
f579b2b1 AB |
740 | unsigned long prot, |
741 | void *(*alloc)(unsigned long sz)) | |
ae8f1541 | 742 | { |
24e6c699 | 743 | if (pmd_none(*pmd)) { |
f579b2b1 | 744 | pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); |
97092e0c | 745 | __pmd_populate(pmd, __pa(pte), prot); |
24e6c699 | 746 | } |
4bb2e27d RK |
747 | BUG_ON(pmd_bad(*pmd)); |
748 | return pte_offset_kernel(pmd, addr); | |
749 | } | |
ae8f1541 | 750 | |
f579b2b1 AB |
751 | static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, |
752 | unsigned long prot) | |
753 | { | |
3ed3a4f0 | 754 | return arm_pte_alloc(pmd, addr, prot, early_alloc); |
f579b2b1 AB |
755 | } |
756 | ||
4bb2e27d RK |
757 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
758 | unsigned long end, unsigned long pfn, | |
f579b2b1 | 759 | const struct mem_type *type, |
b430e55b AB |
760 | void *(*alloc)(unsigned long sz), |
761 | bool ng) | |
4bb2e27d | 762 | { |
3ed3a4f0 | 763 | pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc); |
24e6c699 | 764 | do { |
b430e55b AB |
765 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), |
766 | ng ? PTE_EXT_NG : 0); | |
24e6c699 RK |
767 | pfn++; |
768 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
ae8f1541 RK |
769 | } |
770 | ||
37468b30 | 771 | static void __init __map_init_section(pmd_t *pmd, unsigned long addr, |
e651eab0 | 772 | unsigned long end, phys_addr_t phys, |
b430e55b | 773 | const struct mem_type *type, bool ng) |
ae8f1541 | 774 | { |
37468b30 PYC |
775 | pmd_t *p = pmd; |
776 | ||
e651eab0 | 777 | #ifndef CONFIG_ARM_LPAE |
24e6c699 | 778 | /* |
e651eab0 S |
779 | * In classic MMU format, puds and pmds are folded in to |
780 | * the pgds. pmd_offset gives the PGD entry. PGDs refer to a | |
781 | * group of L1 entries making up one logical pointer to | |
782 | * an L2 table (2MB), where as PMDs refer to the individual | |
783 | * L1 entries (1MB). Hence increment to get the correct | |
784 | * offset for odd 1MB sections. | |
785 | * (See arch/arm/include/asm/pgtable-2level.h) | |
24e6c699 | 786 | */ |
e651eab0 S |
787 | if (addr & SECTION_SIZE) |
788 | pmd++; | |
1b6ba46b | 789 | #endif |
e651eab0 | 790 | do { |
b430e55b | 791 | *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0)); |
e651eab0 S |
792 | phys += SECTION_SIZE; |
793 | } while (pmd++, addr += SECTION_SIZE, addr != end); | |
24e6c699 | 794 | |
37468b30 | 795 | flush_pmd_entry(p); |
e651eab0 | 796 | } |
ae8f1541 | 797 | |
e651eab0 S |
798 | static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, |
799 | unsigned long end, phys_addr_t phys, | |
f579b2b1 | 800 | const struct mem_type *type, |
b430e55b | 801 | void *(*alloc)(unsigned long sz), bool ng) |
e651eab0 S |
802 | { |
803 | pmd_t *pmd = pmd_offset(pud, addr); | |
804 | unsigned long next; | |
805 | ||
806 | do { | |
24e6c699 | 807 | /* |
e651eab0 S |
808 | * With LPAE, we must loop over to map |
809 | * all the pmds for the given range. | |
24e6c699 | 810 | */ |
e651eab0 S |
811 | next = pmd_addr_end(addr, end); |
812 | ||
813 | /* | |
814 | * Try a section mapping - addr, next and phys must all be | |
815 | * aligned to a section boundary. | |
816 | */ | |
817 | if (type->prot_sect && | |
818 | ((addr | next | phys) & ~SECTION_MASK) == 0) { | |
b430e55b | 819 | __map_init_section(pmd, addr, next, phys, type, ng); |
e651eab0 S |
820 | } else { |
821 | alloc_init_pte(pmd, addr, next, | |
b430e55b | 822 | __phys_to_pfn(phys), type, alloc, ng); |
e651eab0 S |
823 | } |
824 | ||
825 | phys += next - addr; | |
826 | ||
827 | } while (pmd++, addr = next, addr != end); | |
ae8f1541 RK |
828 | } |
829 | ||
14904927 | 830 | static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, |
20d6956d | 831 | unsigned long end, phys_addr_t phys, |
f579b2b1 | 832 | const struct mem_type *type, |
b430e55b | 833 | void *(*alloc)(unsigned long sz), bool ng) |
516295e5 RK |
834 | { |
835 | pud_t *pud = pud_offset(pgd, addr); | |
836 | unsigned long next; | |
837 | ||
838 | do { | |
839 | next = pud_addr_end(addr, end); | |
b430e55b | 840 | alloc_init_pmd(pud, addr, next, phys, type, alloc, ng); |
516295e5 RK |
841 | phys += next - addr; |
842 | } while (pud++, addr = next, addr != end); | |
843 | } | |
844 | ||
1b6ba46b | 845 | #ifndef CONFIG_ARM_LPAE |
1bdb2d4e AB |
846 | static void __init create_36bit_mapping(struct mm_struct *mm, |
847 | struct map_desc *md, | |
b430e55b AB |
848 | const struct mem_type *type, |
849 | bool ng) | |
4a56c1e4 | 850 | { |
97092e0c RK |
851 | unsigned long addr, length, end; |
852 | phys_addr_t phys; | |
4a56c1e4 RK |
853 | pgd_t *pgd; |
854 | ||
855 | addr = md->virtual; | |
cae6292b | 856 | phys = __pfn_to_phys(md->pfn); |
4a56c1e4 RK |
857 | length = PAGE_ALIGN(md->length); |
858 | ||
859 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { | |
4ed89f22 | 860 | pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n", |
29a38193 | 861 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
862 | return; |
863 | } | |
864 | ||
865 | /* N.B. ARMv6 supersections are only defined to work with domain 0. | |
866 | * Since domain assignments can in fact be arbitrary, the | |
867 | * 'domain == 0' check below is required to insure that ARMv6 | |
868 | * supersections are only allocated for domain 0 regardless | |
869 | * of the actual domain assignments in use. | |
870 | */ | |
871 | if (type->domain) { | |
4ed89f22 | 872 | pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n", |
29a38193 | 873 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
874 | return; |
875 | } | |
876 | ||
877 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { | |
4ed89f22 | 878 | pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n", |
29a38193 | 879 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
880 | return; |
881 | } | |
882 | ||
883 | /* | |
884 | * Shift bits [35:32] of address into bits [23:20] of PMD | |
885 | * (See ARMv6 spec). | |
886 | */ | |
887 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); | |
888 | ||
1bdb2d4e | 889 | pgd = pgd_offset(mm, addr); |
4a56c1e4 RK |
890 | end = addr + length; |
891 | do { | |
516295e5 RK |
892 | pud_t *pud = pud_offset(pgd, addr); |
893 | pmd_t *pmd = pmd_offset(pud, addr); | |
4a56c1e4 RK |
894 | int i; |
895 | ||
896 | for (i = 0; i < 16; i++) | |
b430e55b AB |
897 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER | |
898 | (ng ? PMD_SECT_nG : 0)); | |
4a56c1e4 RK |
899 | |
900 | addr += SUPERSECTION_SIZE; | |
901 | phys += SUPERSECTION_SIZE; | |
902 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; | |
903 | } while (addr != end); | |
904 | } | |
1b6ba46b | 905 | #endif /* !CONFIG_ARM_LPAE */ |
4a56c1e4 | 906 | |
f579b2b1 | 907 | static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md, |
b430e55b AB |
908 | void *(*alloc)(unsigned long sz), |
909 | bool ng) | |
ae8f1541 | 910 | { |
cae6292b WD |
911 | unsigned long addr, length, end; |
912 | phys_addr_t phys; | |
d5c98176 | 913 | const struct mem_type *type; |
24e6c699 | 914 | pgd_t *pgd; |
ae8f1541 | 915 | |
d5c98176 | 916 | type = &mem_types[md->type]; |
ae8f1541 | 917 | |
1b6ba46b | 918 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
919 | /* |
920 | * Catch 36-bit addresses | |
921 | */ | |
4a56c1e4 | 922 | if (md->pfn >= 0x100000) { |
b430e55b | 923 | create_36bit_mapping(mm, md, type, ng); |
4a56c1e4 | 924 | return; |
ae8f1541 | 925 | } |
1b6ba46b | 926 | #endif |
ae8f1541 | 927 | |
7b9c7b4d | 928 | addr = md->virtual & PAGE_MASK; |
cae6292b | 929 | phys = __pfn_to_phys(md->pfn); |
7b9c7b4d | 930 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
ae8f1541 | 931 | |
24e6c699 | 932 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
4ed89f22 RK |
933 | pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n", |
934 | (long long)__pfn_to_phys(md->pfn), addr); | |
ae8f1541 RK |
935 | return; |
936 | } | |
937 | ||
1bdb2d4e | 938 | pgd = pgd_offset(mm, addr); |
24e6c699 RK |
939 | end = addr + length; |
940 | do { | |
941 | unsigned long next = pgd_addr_end(addr, end); | |
ae8f1541 | 942 | |
b430e55b | 943 | alloc_init_pud(pgd, addr, next, phys, type, alloc, ng); |
ae8f1541 | 944 | |
24e6c699 RK |
945 | phys += next - addr; |
946 | addr = next; | |
947 | } while (pgd++, addr != end); | |
ae8f1541 RK |
948 | } |
949 | ||
1bdb2d4e AB |
950 | /* |
951 | * Create the page directory entries and any necessary | |
952 | * page tables for the mapping specified by `md'. We | |
953 | * are able to cope here with varying sizes and address | |
954 | * offsets, and we take full advantage of sections and | |
955 | * supersections. | |
956 | */ | |
957 | static void __init create_mapping(struct map_desc *md) | |
958 | { | |
959 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { | |
960 | pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n", | |
961 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
962 | return; | |
963 | } | |
964 | ||
965 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && | |
966 | md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START && | |
967 | (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { | |
968 | pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n", | |
969 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
970 | } | |
971 | ||
b430e55b | 972 | __create_mapping(&init_mm, md, early_alloc, false); |
1bdb2d4e AB |
973 | } |
974 | ||
c7936206 AB |
975 | void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md, |
976 | bool ng) | |
977 | { | |
978 | #ifdef CONFIG_ARM_LPAE | |
979 | pud_t *pud = pud_alloc(mm, pgd_offset(mm, md->virtual), md->virtual); | |
980 | if (WARN_ON(!pud)) | |
981 | return; | |
982 | pmd_alloc(mm, pud, 0); | |
983 | #endif | |
984 | __create_mapping(mm, md, late_alloc, ng); | |
985 | } | |
986 | ||
ae8f1541 RK |
987 | /* |
988 | * Create the architecture specific mappings | |
989 | */ | |
990 | void __init iotable_init(struct map_desc *io_desc, int nr) | |
991 | { | |
0536bdf3 NP |
992 | struct map_desc *md; |
993 | struct vm_struct *vm; | |
101eeda3 | 994 | struct static_vm *svm; |
0536bdf3 NP |
995 | |
996 | if (!nr) | |
997 | return; | |
ae8f1541 | 998 | |
c2938eeb | 999 | svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm)); |
8a7f97b9 MR |
1000 | if (!svm) |
1001 | panic("%s: Failed to allocate %zu bytes align=0x%zx\n", | |
1002 | __func__, sizeof(*svm) * nr, __alignof__(*svm)); | |
0536bdf3 NP |
1003 | |
1004 | for (md = io_desc; nr; md++, nr--) { | |
1005 | create_mapping(md); | |
101eeda3 JK |
1006 | |
1007 | vm = &svm->vm; | |
0536bdf3 NP |
1008 | vm->addr = (void *)(md->virtual & PAGE_MASK); |
1009 | vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); | |
c2794437 RH |
1010 | vm->phys_addr = __pfn_to_phys(md->pfn); |
1011 | vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; | |
576d2f25 | 1012 | vm->flags |= VM_ARM_MTYPE(md->type); |
0536bdf3 | 1013 | vm->caller = iotable_init; |
101eeda3 | 1014 | add_static_vm_early(svm++); |
0536bdf3 | 1015 | } |
ae8f1541 RK |
1016 | } |
1017 | ||
c2794437 RH |
1018 | void __init vm_reserve_area_early(unsigned long addr, unsigned long size, |
1019 | void *caller) | |
1020 | { | |
1021 | struct vm_struct *vm; | |
101eeda3 JK |
1022 | struct static_vm *svm; |
1023 | ||
c2938eeb | 1024 | svm = memblock_alloc(sizeof(*svm), __alignof__(*svm)); |
8a7f97b9 MR |
1025 | if (!svm) |
1026 | panic("%s: Failed to allocate %zu bytes align=0x%zx\n", | |
1027 | __func__, sizeof(*svm), __alignof__(*svm)); | |
c2794437 | 1028 | |
101eeda3 | 1029 | vm = &svm->vm; |
c2794437 RH |
1030 | vm->addr = (void *)addr; |
1031 | vm->size = size; | |
863e99a8 | 1032 | vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; |
c2794437 | 1033 | vm->caller = caller; |
101eeda3 | 1034 | add_static_vm_early(svm); |
c2794437 RH |
1035 | } |
1036 | ||
19b52abe NP |
1037 | #ifndef CONFIG_ARM_LPAE |
1038 | ||
1039 | /* | |
1040 | * The Linux PMD is made of two consecutive section entries covering 2MB | |
1041 | * (see definition in include/asm/pgtable-2level.h). However a call to | |
1042 | * create_mapping() may optimize static mappings by using individual | |
1043 | * 1MB section mappings. This leaves the actual PMD potentially half | |
1044 | * initialized if the top or bottom section entry isn't used, leaving it | |
1045 | * open to problems if a subsequent ioremap() or vmalloc() tries to use | |
1046 | * the virtual space left free by that unused section entry. | |
1047 | * | |
1048 | * Let's avoid the issue by inserting dummy vm entries covering the unused | |
1049 | * PMD halves once the static mappings are in place. | |
1050 | */ | |
1051 | ||
1052 | static void __init pmd_empty_section_gap(unsigned long addr) | |
1053 | { | |
c2794437 | 1054 | vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); |
19b52abe NP |
1055 | } |
1056 | ||
1057 | static void __init fill_pmd_gaps(void) | |
1058 | { | |
101eeda3 | 1059 | struct static_vm *svm; |
19b52abe NP |
1060 | struct vm_struct *vm; |
1061 | unsigned long addr, next = 0; | |
1062 | pmd_t *pmd; | |
1063 | ||
101eeda3 JK |
1064 | list_for_each_entry(svm, &static_vmlist, list) { |
1065 | vm = &svm->vm; | |
19b52abe NP |
1066 | addr = (unsigned long)vm->addr; |
1067 | if (addr < next) | |
1068 | continue; | |
1069 | ||
1070 | /* | |
1071 | * Check if this vm starts on an odd section boundary. | |
1072 | * If so and the first section entry for this PMD is free | |
1073 | * then we block the corresponding virtual address. | |
1074 | */ | |
1075 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
1076 | pmd = pmd_off_k(addr); | |
1077 | if (pmd_none(*pmd)) | |
1078 | pmd_empty_section_gap(addr & PMD_MASK); | |
1079 | } | |
1080 | ||
1081 | /* | |
1082 | * Then check if this vm ends on an odd section boundary. | |
1083 | * If so and the second section entry for this PMD is empty | |
1084 | * then we block the corresponding virtual address. | |
1085 | */ | |
1086 | addr += vm->size; | |
1087 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
1088 | pmd = pmd_off_k(addr) + 1; | |
1089 | if (pmd_none(*pmd)) | |
1090 | pmd_empty_section_gap(addr); | |
1091 | } | |
1092 | ||
1093 | /* no need to look at any vm entry until we hit the next PMD */ | |
1094 | next = (addr + PMD_SIZE - 1) & PMD_MASK; | |
1095 | } | |
1096 | } | |
1097 | ||
1098 | #else | |
1099 | #define fill_pmd_gaps() do { } while (0) | |
1100 | #endif | |
1101 | ||
c2794437 RH |
1102 | #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) |
1103 | static void __init pci_reserve_io(void) | |
1104 | { | |
101eeda3 | 1105 | struct static_vm *svm; |
c2794437 | 1106 | |
101eeda3 JK |
1107 | svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); |
1108 | if (svm) | |
1109 | return; | |
c2794437 | 1110 | |
c2794437 RH |
1111 | vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); |
1112 | } | |
1113 | #else | |
1114 | #define pci_reserve_io() do { } while (0) | |
1115 | #endif | |
1116 | ||
e5c5f2ad RH |
1117 | #ifdef CONFIG_DEBUG_LL |
1118 | void __init debug_ll_io_init(void) | |
1119 | { | |
1120 | struct map_desc map; | |
1121 | ||
1122 | debug_ll_addr(&map.pfn, &map.virtual); | |
1123 | if (!map.pfn || !map.virtual) | |
1124 | return; | |
1125 | map.pfn = __phys_to_pfn(map.pfn); | |
1126 | map.virtual &= PAGE_MASK; | |
1127 | map.length = PAGE_SIZE; | |
1128 | map.type = MT_DEVICE; | |
ee4de5d9 | 1129 | iotable_init(&map, 1); |
e5c5f2ad RH |
1130 | } |
1131 | #endif | |
1132 | ||
0536bdf3 NP |
1133 | static void * __initdata vmalloc_min = |
1134 | (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); | |
6c5da7ac RK |
1135 | |
1136 | /* | |
1137 | * vmalloc=size forces the vmalloc area to be exactly 'size' | |
1138 | * bytes. This can be used to increase (or decrease) the vmalloc | |
0536bdf3 | 1139 | * area - the default is 240m. |
6c5da7ac | 1140 | */ |
2b0d8c25 | 1141 | static int __init early_vmalloc(char *arg) |
6c5da7ac | 1142 | { |
79612395 | 1143 | unsigned long vmalloc_reserve = memparse(arg, NULL); |
6c5da7ac RK |
1144 | |
1145 | if (vmalloc_reserve < SZ_16M) { | |
1146 | vmalloc_reserve = SZ_16M; | |
4ed89f22 | 1147 | pr_warn("vmalloc area too small, limiting to %luMB\n", |
6c5da7ac RK |
1148 | vmalloc_reserve >> 20); |
1149 | } | |
9210807c NP |
1150 | |
1151 | if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { | |
1152 | vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); | |
4ed89f22 | 1153 | pr_warn("vmalloc area is too big, limiting to %luMB\n", |
9210807c NP |
1154 | vmalloc_reserve >> 20); |
1155 | } | |
79612395 RK |
1156 | |
1157 | vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); | |
2b0d8c25 | 1158 | return 0; |
6c5da7ac | 1159 | } |
2b0d8c25 | 1160 | early_param("vmalloc", early_vmalloc); |
6c5da7ac | 1161 | |
c7909509 | 1162 | phys_addr_t arm_lowmem_limit __initdata = 0; |
8df65168 | 1163 | |
374d446d | 1164 | void __init adjust_lowmem_bounds(void) |
60296c71 | 1165 | { |
c65b7e98 | 1166 | phys_addr_t memblock_limit = 0; |
b9a01989 | 1167 | u64 vmalloc_limit; |
1c2f87c2 | 1168 | struct memblock_region *reg; |
98562656 | 1169 | phys_addr_t lowmem_limit = 0; |
60296c71 | 1170 | |
b9a01989 NP |
1171 | /* |
1172 | * Let's use our own (unoptimized) equivalent of __pa() that is | |
1173 | * not affected by wrap-arounds when sizeof(phys_addr_t) == 4. | |
1174 | * The result is used as the upper bound on physical memory address | |
1175 | * and may itself be outside the valid range for which phys_addr_t | |
1176 | * and therefore __pa() is defined. | |
1177 | */ | |
1178 | vmalloc_limit = (u64)(uintptr_t)vmalloc_min - PAGE_OFFSET + PHYS_OFFSET; | |
1179 | ||
00d2ec1e MR |
1180 | /* |
1181 | * The first usable region must be PMD aligned. Mark its start | |
1182 | * as MEMBLOCK_NOMAP if it isn't | |
1183 | */ | |
1184 | for_each_memblock(memory, reg) { | |
1185 | if (!memblock_is_nomap(reg)) { | |
1186 | if (!IS_ALIGNED(reg->base, PMD_SIZE)) { | |
1187 | phys_addr_t len; | |
1188 | ||
1189 | len = round_up(reg->base, PMD_SIZE) - reg->base; | |
1190 | memblock_mark_nomap(reg->base, len); | |
1191 | } | |
1192 | break; | |
1193 | } | |
1194 | } | |
1195 | ||
1c2f87c2 LA |
1196 | for_each_memblock(memory, reg) { |
1197 | phys_addr_t block_start = reg->base; | |
1198 | phys_addr_t block_end = reg->base + reg->size; | |
77f73a2c | 1199 | |
1d31999c CL |
1200 | if (memblock_is_nomap(reg)) |
1201 | continue; | |
1202 | ||
374d446d | 1203 | if (reg->base < vmalloc_limit) { |
98562656 | 1204 | if (block_end > lowmem_limit) |
374d446d LA |
1205 | /* |
1206 | * Compare as u64 to ensure vmalloc_limit does | |
1207 | * not get truncated. block_end should always | |
1208 | * fit in phys_addr_t so there should be no | |
1209 | * issue with assignment. | |
1210 | */ | |
98562656 | 1211 | lowmem_limit = min_t(u64, |
374d446d LA |
1212 | vmalloc_limit, |
1213 | block_end); | |
c65b7e98 RK |
1214 | |
1215 | /* | |
965278dc | 1216 | * Find the first non-pmd-aligned page, and point |
c65b7e98 | 1217 | * memblock_limit at it. This relies on rounding the |
965278dc MR |
1218 | * limit down to be pmd-aligned, which happens at the |
1219 | * end of this function. | |
c65b7e98 RK |
1220 | * |
1221 | * With this algorithm, the start or end of almost any | |
965278dc MR |
1222 | * bank can be non-pmd-aligned. The only exception is |
1223 | * that the start of the bank 0 must be section- | |
c65b7e98 RK |
1224 | * aligned, since otherwise memory would need to be |
1225 | * allocated when mapping the start of bank 0, which | |
1226 | * occurs before any free memory is mapped. | |
1227 | */ | |
1228 | if (!memblock_limit) { | |
965278dc | 1229 | if (!IS_ALIGNED(block_start, PMD_SIZE)) |
1c2f87c2 | 1230 | memblock_limit = block_start; |
965278dc | 1231 | else if (!IS_ALIGNED(block_end, PMD_SIZE)) |
98562656 | 1232 | memblock_limit = lowmem_limit; |
c65b7e98 | 1233 | } |
e616c591 | 1234 | |
e616c591 RK |
1235 | } |
1236 | } | |
1c2f87c2 | 1237 | |
98562656 LA |
1238 | arm_lowmem_limit = lowmem_limit; |
1239 | ||
c7909509 | 1240 | high_memory = __va(arm_lowmem_limit - 1) + 1; |
c65b7e98 | 1241 | |
9e25ebfe DB |
1242 | if (!memblock_limit) |
1243 | memblock_limit = arm_lowmem_limit; | |
1244 | ||
c65b7e98 | 1245 | /* |
965278dc | 1246 | * Round the memblock limit down to a pmd size. This |
c65b7e98 | 1247 | * helps to ensure that we will allocate memory from the |
965278dc | 1248 | * last full pmd, which should be mapped. |
c65b7e98 | 1249 | */ |
9e25ebfe | 1250 | memblock_limit = round_down(memblock_limit, PMD_SIZE); |
c65b7e98 | 1251 | |
374d446d LA |
1252 | if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) { |
1253 | if (memblock_end_of_DRAM() > arm_lowmem_limit) { | |
1254 | phys_addr_t end = memblock_end_of_DRAM(); | |
1255 | ||
1256 | pr_notice("Ignoring RAM at %pa-%pa\n", | |
1257 | &memblock_limit, &end); | |
1258 | pr_notice("Consider using a HIGHMEM enabled kernel.\n"); | |
1259 | ||
1260 | memblock_remove(memblock_limit, end - memblock_limit); | |
1261 | } | |
1262 | } | |
1263 | ||
c65b7e98 | 1264 | memblock_set_current_limit(memblock_limit); |
60296c71 LB |
1265 | } |
1266 | ||
4b5f32ce | 1267 | static inline void prepare_page_table(void) |
d111e8f9 RK |
1268 | { |
1269 | unsigned long addr; | |
8df65168 | 1270 | phys_addr_t end; |
d111e8f9 RK |
1271 | |
1272 | /* | |
1273 | * Clear out all the mappings below the kernel image. | |
1274 | */ | |
e73fc88e | 1275 | for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) |
d111e8f9 RK |
1276 | pmd_clear(pmd_off_k(addr)); |
1277 | ||
1278 | #ifdef CONFIG_XIP_KERNEL | |
1279 | /* The XIP kernel is mapped in the module area -- skip over it */ | |
02afa9a8 | 1280 | addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK; |
d111e8f9 | 1281 | #endif |
e73fc88e | 1282 | for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) |
d111e8f9 RK |
1283 | pmd_clear(pmd_off_k(addr)); |
1284 | ||
8df65168 RK |
1285 | /* |
1286 | * Find the end of the first block of lowmem. | |
1287 | */ | |
1288 | end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; | |
c7909509 MS |
1289 | if (end >= arm_lowmem_limit) |
1290 | end = arm_lowmem_limit; | |
8df65168 | 1291 | |
d111e8f9 RK |
1292 | /* |
1293 | * Clear out all the kernel space mappings, except for the first | |
0536bdf3 | 1294 | * memory bank, up to the vmalloc region. |
d111e8f9 | 1295 | */ |
8df65168 | 1296 | for (addr = __phys_to_virt(end); |
0536bdf3 | 1297 | addr < VMALLOC_START; addr += PMD_SIZE) |
d111e8f9 RK |
1298 | pmd_clear(pmd_off_k(addr)); |
1299 | } | |
1300 | ||
1b6ba46b CM |
1301 | #ifdef CONFIG_ARM_LPAE |
1302 | /* the first page is reserved for pgd */ | |
1303 | #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ | |
1304 | PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) | |
1305 | #else | |
e73fc88e | 1306 | #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) |
1b6ba46b | 1307 | #endif |
e73fc88e | 1308 | |
d111e8f9 | 1309 | /* |
2778f620 | 1310 | * Reserve the special regions of memory |
d111e8f9 | 1311 | */ |
2778f620 | 1312 | void __init arm_mm_memblock_reserve(void) |
d111e8f9 | 1313 | { |
d111e8f9 RK |
1314 | /* |
1315 | * Reserve the page tables. These are already in use, | |
1316 | * and can only be in node 0. | |
1317 | */ | |
e73fc88e | 1318 | memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); |
d111e8f9 | 1319 | |
d111e8f9 RK |
1320 | #ifdef CONFIG_SA1111 |
1321 | /* | |
1322 | * Because of the SA1111 DMA bug, we want to preserve our | |
1323 | * precious DMA-able memory... | |
1324 | */ | |
2778f620 | 1325 | memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
d111e8f9 | 1326 | #endif |
d111e8f9 RK |
1327 | } |
1328 | ||
1329 | /* | |
0536bdf3 | 1330 | * Set up the device mappings. Since we clear out the page tables for all |
a5f4c561 SA |
1331 | * mappings above VMALLOC_START, except early fixmap, we might remove debug |
1332 | * device mappings. This means earlycon can be used to debug this function | |
1333 | * Any other function or debugging method which may touch any device _will_ | |
1334 | * crash the kernel. | |
d111e8f9 | 1335 | */ |
ff69a4c8 | 1336 | static void __init devicemaps_init(const struct machine_desc *mdesc) |
d111e8f9 RK |
1337 | { |
1338 | struct map_desc map; | |
1339 | unsigned long addr; | |
94e5a85b | 1340 | void *vectors; |
d111e8f9 RK |
1341 | |
1342 | /* | |
1343 | * Allocate the vector page early. | |
1344 | */ | |
19accfd3 | 1345 | vectors = early_alloc(PAGE_SIZE * 2); |
94e5a85b RK |
1346 | |
1347 | early_trap_init(vectors); | |
d111e8f9 | 1348 | |
a5f4c561 SA |
1349 | /* |
1350 | * Clear page table except top pmd used by early fixmaps | |
1351 | */ | |
1352 | for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE) | |
d111e8f9 RK |
1353 | pmd_clear(pmd_off_k(addr)); |
1354 | ||
1355 | /* | |
1356 | * Map the kernel if it is XIP. | |
1357 | * It is always first in the modulearea. | |
1358 | */ | |
1359 | #ifdef CONFIG_XIP_KERNEL | |
1360 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); | |
ab4f2ee1 | 1361 | map.virtual = MODULES_VADDR; |
02afa9a8 | 1362 | map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
d111e8f9 RK |
1363 | map.type = MT_ROM; |
1364 | create_mapping(&map); | |
1365 | #endif | |
1366 | ||
1367 | /* | |
1368 | * Map the cache flushing regions. | |
1369 | */ | |
1370 | #ifdef FLUSH_BASE | |
1371 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); | |
1372 | map.virtual = FLUSH_BASE; | |
1373 | map.length = SZ_1M; | |
1374 | map.type = MT_CACHECLEAN; | |
1375 | create_mapping(&map); | |
1376 | #endif | |
1377 | #ifdef FLUSH_BASE_MINICACHE | |
1378 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); | |
1379 | map.virtual = FLUSH_BASE_MINICACHE; | |
1380 | map.length = SZ_1M; | |
1381 | map.type = MT_MINICLEAN; | |
1382 | create_mapping(&map); | |
1383 | #endif | |
1384 | ||
1385 | /* | |
1386 | * Create a mapping for the machine vectors at the high-vectors | |
1387 | * location (0xffff0000). If we aren't using high-vectors, also | |
1388 | * create a mapping at the low-vectors virtual address. | |
1389 | */ | |
94e5a85b | 1390 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); |
d111e8f9 RK |
1391 | map.virtual = 0xffff0000; |
1392 | map.length = PAGE_SIZE; | |
a5463cd3 | 1393 | #ifdef CONFIG_KUSER_HELPERS |
d111e8f9 | 1394 | map.type = MT_HIGH_VECTORS; |
a5463cd3 RK |
1395 | #else |
1396 | map.type = MT_LOW_VECTORS; | |
1397 | #endif | |
d111e8f9 RK |
1398 | create_mapping(&map); |
1399 | ||
1400 | if (!vectors_high()) { | |
1401 | map.virtual = 0; | |
19accfd3 | 1402 | map.length = PAGE_SIZE * 2; |
d111e8f9 RK |
1403 | map.type = MT_LOW_VECTORS; |
1404 | create_mapping(&map); | |
1405 | } | |
1406 | ||
19accfd3 RK |
1407 | /* Now create a kernel read-only mapping */ |
1408 | map.pfn += 1; | |
1409 | map.virtual = 0xffff0000 + PAGE_SIZE; | |
1410 | map.length = PAGE_SIZE; | |
1411 | map.type = MT_LOW_VECTORS; | |
1412 | create_mapping(&map); | |
1413 | ||
d111e8f9 RK |
1414 | /* |
1415 | * Ask the machine support to map in the statically mapped devices. | |
1416 | */ | |
1417 | if (mdesc->map_io) | |
1418 | mdesc->map_io(); | |
bc37324e MR |
1419 | else |
1420 | debug_ll_io_init(); | |
19b52abe | 1421 | fill_pmd_gaps(); |
d111e8f9 | 1422 | |
c2794437 RH |
1423 | /* Reserve fixed i/o space in VMALLOC region */ |
1424 | pci_reserve_io(); | |
1425 | ||
d111e8f9 RK |
1426 | /* |
1427 | * Finally flush the caches and tlb to ensure that we're in a | |
1428 | * consistent state wrt the writebuffer. This also ensures that | |
1429 | * any write-allocated cache lines in the vector page are written | |
1430 | * back. After this point, we can start to touch devices again. | |
1431 | */ | |
1432 | local_flush_tlb_all(); | |
1433 | flush_cache_all(); | |
bbeb9209 LS |
1434 | |
1435 | /* Enable asynchronous aborts */ | |
9254970c | 1436 | early_abt_enable(); |
d111e8f9 RK |
1437 | } |
1438 | ||
d73cd428 NP |
1439 | static void __init kmap_init(void) |
1440 | { | |
1441 | #ifdef CONFIG_HIGHMEM | |
4bb2e27d RK |
1442 | pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), |
1443 | PKMAP_BASE, _PAGE_KERNEL_TABLE); | |
d73cd428 | 1444 | #endif |
836a2418 RH |
1445 | |
1446 | early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START, | |
1447 | _PAGE_KERNEL_TABLE); | |
d73cd428 NP |
1448 | } |
1449 | ||
a2227120 RK |
1450 | static void __init map_lowmem(void) |
1451 | { | |
8df65168 | 1452 | struct memblock_region *reg; |
a09975bf | 1453 | phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE); |
ac084688 | 1454 | phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); |
a2227120 RK |
1455 | |
1456 | /* Map all the lowmem memory banks. */ | |
8df65168 RK |
1457 | for_each_memblock(memory, reg) { |
1458 | phys_addr_t start = reg->base; | |
1459 | phys_addr_t end = start + reg->size; | |
1460 | struct map_desc map; | |
1461 | ||
09414d00 AB |
1462 | if (memblock_is_nomap(reg)) |
1463 | continue; | |
1464 | ||
c7909509 MS |
1465 | if (end > arm_lowmem_limit) |
1466 | end = arm_lowmem_limit; | |
8df65168 RK |
1467 | if (start >= end) |
1468 | break; | |
1469 | ||
1e6b4811 | 1470 | if (end < kernel_x_start) { |
ebd4922e RK |
1471 | map.pfn = __phys_to_pfn(start); |
1472 | map.virtual = __phys_to_virt(start); | |
1473 | map.length = end - start; | |
1474 | map.type = MT_MEMORY_RWX; | |
a2227120 | 1475 | |
1e6b4811 KC |
1476 | create_mapping(&map); |
1477 | } else if (start >= kernel_x_end) { | |
1478 | map.pfn = __phys_to_pfn(start); | |
1479 | map.virtual = __phys_to_virt(start); | |
1480 | map.length = end - start; | |
1481 | map.type = MT_MEMORY_RW; | |
1482 | ||
ebd4922e RK |
1483 | create_mapping(&map); |
1484 | } else { | |
1485 | /* This better cover the entire kernel */ | |
1486 | if (start < kernel_x_start) { | |
1487 | map.pfn = __phys_to_pfn(start); | |
1488 | map.virtual = __phys_to_virt(start); | |
1489 | map.length = kernel_x_start - start; | |
1490 | map.type = MT_MEMORY_RW; | |
1491 | ||
1492 | create_mapping(&map); | |
1493 | } | |
1494 | ||
1495 | map.pfn = __phys_to_pfn(kernel_x_start); | |
1496 | map.virtual = __phys_to_virt(kernel_x_start); | |
1497 | map.length = kernel_x_end - kernel_x_start; | |
1498 | map.type = MT_MEMORY_RWX; | |
1499 | ||
1500 | create_mapping(&map); | |
1501 | ||
1502 | if (kernel_x_end < end) { | |
1503 | map.pfn = __phys_to_pfn(kernel_x_end); | |
1504 | map.virtual = __phys_to_virt(kernel_x_end); | |
1505 | map.length = end - kernel_x_end; | |
1506 | map.type = MT_MEMORY_RW; | |
1507 | ||
1508 | create_mapping(&map); | |
1509 | } | |
1510 | } | |
a2227120 RK |
1511 | } |
1512 | } | |
1513 | ||
d8dc7fbd RK |
1514 | #ifdef CONFIG_ARM_PV_FIXUP |
1515 | extern unsigned long __atags_pointer; | |
1516 | typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata); | |
1517 | pgtables_remap lpae_pgtables_remap_asm; | |
1518 | ||
a77e0c7b SS |
1519 | /* |
1520 | * early_paging_init() recreates boot time page table setup, allowing machines | |
1521 | * to switch over to a high (>4G) address space on LPAE systems | |
1522 | */ | |
b089c31c | 1523 | static void __init early_paging_init(const struct machine_desc *mdesc) |
a77e0c7b | 1524 | { |
d8dc7fbd RK |
1525 | pgtables_remap *lpae_pgtables_remap; |
1526 | unsigned long pa_pgd; | |
1527 | unsigned int cr, ttbcr; | |
c8ca2b4b | 1528 | long long offset; |
d8dc7fbd | 1529 | void *boot_data; |
a77e0c7b | 1530 | |
c0b759d8 | 1531 | if (!mdesc->pv_fixup) |
a77e0c7b SS |
1532 | return; |
1533 | ||
c0b759d8 | 1534 | offset = mdesc->pv_fixup(); |
c8ca2b4b RK |
1535 | if (offset == 0) |
1536 | return; | |
a77e0c7b | 1537 | |
d8dc7fbd RK |
1538 | /* |
1539 | * Get the address of the remap function in the 1:1 identity | |
1540 | * mapping setup by the early page table assembly code. We | |
1541 | * must get this prior to the pv update. The following barrier | |
1542 | * ensures that this is complete before we fixup any P:V offsets. | |
1543 | */ | |
1544 | lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm); | |
1545 | pa_pgd = __pa(swapper_pg_dir); | |
1546 | boot_data = __va(__atags_pointer); | |
1547 | barrier(); | |
a77e0c7b | 1548 | |
39b74fe8 RK |
1549 | pr_info("Switching physical address space to 0x%08llx\n", |
1550 | (u64)PHYS_OFFSET + offset); | |
a77e0c7b | 1551 | |
c8ca2b4b RK |
1552 | /* Re-set the phys pfn offset, and the pv offset */ |
1553 | __pv_offset += offset; | |
1554 | __pv_phys_pfn_offset += PFN_DOWN(offset); | |
a77e0c7b SS |
1555 | |
1556 | /* Run the patch stub to update the constants */ | |
1557 | fixup_pv_table(&__pv_table_begin, | |
1558 | (&__pv_table_end - &__pv_table_begin) << 2); | |
1559 | ||
1560 | /* | |
d8dc7fbd RK |
1561 | * We changing not only the virtual to physical mapping, but also |
1562 | * the physical addresses used to access memory. We need to flush | |
1563 | * all levels of cache in the system with caching disabled to | |
1564 | * ensure that all data is written back, and nothing is prefetched | |
1565 | * into the caches. We also need to prevent the TLB walkers | |
1566 | * allocating into the caches too. Note that this is ARMv7 LPAE | |
1567 | * specific. | |
3bb70de6 | 1568 | */ |
d8dc7fbd RK |
1569 | cr = get_cr(); |
1570 | set_cr(cr & ~(CR_I | CR_C)); | |
1571 | asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr)); | |
1572 | asm volatile("mcr p15, 0, %0, c2, c0, 2" | |
1573 | : : "r" (ttbcr & ~(3 << 8 | 3 << 10))); | |
a77e0c7b | 1574 | flush_cache_all(); |
3bb70de6 RK |
1575 | |
1576 | /* | |
d8dc7fbd RK |
1577 | * Fixup the page tables - this must be in the idmap region as |
1578 | * we need to disable the MMU to do this safely, and hence it | |
1579 | * needs to be assembly. It's fairly simple, as we're using the | |
1580 | * temporary tables setup by the initial assembly code. | |
3bb70de6 | 1581 | */ |
d8dc7fbd | 1582 | lpae_pgtables_remap(offset, pa_pgd, boot_data); |
3bb70de6 | 1583 | |
d8dc7fbd RK |
1584 | /* Re-enable the caches and cacheable TLB walks */ |
1585 | asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr)); | |
1586 | set_cr(cr); | |
a77e0c7b SS |
1587 | } |
1588 | ||
1589 | #else | |
1590 | ||
b089c31c | 1591 | static void __init early_paging_init(const struct machine_desc *mdesc) |
a77e0c7b | 1592 | { |
c8ca2b4b RK |
1593 | long long offset; |
1594 | ||
c0b759d8 | 1595 | if (!mdesc->pv_fixup) |
c8ca2b4b RK |
1596 | return; |
1597 | ||
c0b759d8 | 1598 | offset = mdesc->pv_fixup(); |
c8ca2b4b RK |
1599 | if (offset == 0) |
1600 | return; | |
1601 | ||
1602 | pr_crit("Physical address space modification is only to support Keystone2.\n"); | |
1603 | pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n"); | |
1604 | pr_crit("feature. Your kernel may crash now, have a good day.\n"); | |
1605 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); | |
a77e0c7b SS |
1606 | } |
1607 | ||
1608 | #endif | |
1609 | ||
a5f4c561 SA |
1610 | static void __init early_fixmap_shutdown(void) |
1611 | { | |
1612 | int i; | |
1613 | unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1); | |
1614 | ||
1615 | pte_offset_fixmap = pte_offset_late_fixmap; | |
1616 | pmd_clear(fixmap_pmd(va)); | |
1617 | local_flush_tlb_kernel_page(va); | |
1618 | ||
1619 | for (i = 0; i < __end_of_permanent_fixed_addresses; i++) { | |
1620 | pte_t *pte; | |
1621 | struct map_desc map; | |
1622 | ||
1623 | map.virtual = fix_to_virt(i); | |
1624 | pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual); | |
1625 | ||
1626 | /* Only i/o device mappings are supported ATM */ | |
1627 | if (pte_none(*pte) || | |
1628 | (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED) | |
1629 | continue; | |
1630 | ||
1631 | map.pfn = pte_pfn(*pte); | |
1632 | map.type = MT_DEVICE; | |
1633 | map.length = PAGE_SIZE; | |
1634 | ||
1635 | create_mapping(&map); | |
1636 | } | |
1637 | } | |
1638 | ||
d111e8f9 RK |
1639 | /* |
1640 | * paging_init() sets up the page tables, initialises the zone memory | |
1641 | * maps, and sets up the zero page, bad page and bad page tables. | |
1642 | */ | |
ff69a4c8 | 1643 | void __init paging_init(const struct machine_desc *mdesc) |
d111e8f9 RK |
1644 | { |
1645 | void *zero_page; | |
1646 | ||
4b5f32ce | 1647 | prepare_page_table(); |
a2227120 | 1648 | map_lowmem(); |
3de1f52a | 1649 | memblock_set_current_limit(arm_lowmem_limit); |
c7909509 | 1650 | dma_contiguous_remap(); |
a5f4c561 | 1651 | early_fixmap_shutdown(); |
d111e8f9 | 1652 | devicemaps_init(mdesc); |
d73cd428 | 1653 | kmap_init(); |
de40614e | 1654 | tcm_init(); |
d111e8f9 RK |
1655 | |
1656 | top_pmd = pmd_off_k(0xffff0000); | |
1657 | ||
3abe9d33 RK |
1658 | /* allocate the zero page. */ |
1659 | zero_page = early_alloc(PAGE_SIZE); | |
2778f620 | 1660 | |
8d717a52 | 1661 | bootmem_init(); |
2778f620 | 1662 | |
d111e8f9 | 1663 | empty_zero_page = virt_to_page(zero_page); |
421fe93c | 1664 | __flush_dcache_page(NULL, empty_zero_page); |
cf763e4e MZ |
1665 | |
1666 | /* Compute the virt/idmap offset, mostly for the sake of KVM */ | |
1667 | kimage_voffset = (unsigned long)&kimage_voffset - virt_to_idmap(&kimage_voffset); | |
d111e8f9 | 1668 | } |
b089c31c JM |
1669 | |
1670 | void __init early_mm_init(const struct machine_desc *mdesc) | |
1671 | { | |
1672 | build_mem_type_table(); | |
1673 | early_paging_init(mdesc); | |
1674 | } |