Commit | Line | Data |
---|---|---|
d111e8f9 RK |
1 | /* |
2 | * linux/arch/arm/mm/mmu.c | |
3 | * | |
4 | * Copyright (C) 1995-2005 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
ae8f1541 | 10 | #include <linux/module.h> |
d111e8f9 RK |
11 | #include <linux/kernel.h> |
12 | #include <linux/errno.h> | |
13 | #include <linux/init.h> | |
d111e8f9 RK |
14 | #include <linux/mman.h> |
15 | #include <linux/nodemask.h> | |
2778f620 | 16 | #include <linux/memblock.h> |
d907387c | 17 | #include <linux/fs.h> |
0536bdf3 | 18 | #include <linux/vmalloc.h> |
d111e8f9 | 19 | |
15d07dc9 | 20 | #include <asm/cp15.h> |
0ba8b9b2 | 21 | #include <asm/cputype.h> |
37efe642 | 22 | #include <asm/sections.h> |
3f973e22 | 23 | #include <asm/cachetype.h> |
d111e8f9 RK |
24 | #include <asm/setup.h> |
25 | #include <asm/sizes.h> | |
e616c591 | 26 | #include <asm/smp_plat.h> |
d111e8f9 | 27 | #include <asm/tlb.h> |
d73cd428 | 28 | #include <asm/highmem.h> |
9f97da78 | 29 | #include <asm/system_info.h> |
247055aa | 30 | #include <asm/traps.h> |
d111e8f9 RK |
31 | |
32 | #include <asm/mach/arch.h> | |
33 | #include <asm/mach/map.h> | |
34 | ||
35 | #include "mm.h" | |
36 | ||
d111e8f9 RK |
37 | /* |
38 | * empty_zero_page is a special page that is used for | |
39 | * zero-initialized data and COW. | |
40 | */ | |
41 | struct page *empty_zero_page; | |
3653f3ab | 42 | EXPORT_SYMBOL(empty_zero_page); |
d111e8f9 RK |
43 | |
44 | /* | |
45 | * The pmd table for the upper-most set of pages. | |
46 | */ | |
47 | pmd_t *top_pmd; | |
48 | ||
ae8f1541 RK |
49 | #define CPOLICY_UNCACHED 0 |
50 | #define CPOLICY_BUFFERED 1 | |
51 | #define CPOLICY_WRITETHROUGH 2 | |
52 | #define CPOLICY_WRITEBACK 3 | |
53 | #define CPOLICY_WRITEALLOC 4 | |
54 | ||
55 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; | |
56 | static unsigned int ecc_mask __initdata = 0; | |
44b18693 | 57 | pgprot_t pgprot_user; |
ae8f1541 RK |
58 | pgprot_t pgprot_kernel; |
59 | ||
44b18693 | 60 | EXPORT_SYMBOL(pgprot_user); |
ae8f1541 RK |
61 | EXPORT_SYMBOL(pgprot_kernel); |
62 | ||
63 | struct cachepolicy { | |
64 | const char policy[16]; | |
65 | unsigned int cr_mask; | |
442e70c0 | 66 | pmdval_t pmd; |
f6e3354d | 67 | pteval_t pte; |
ae8f1541 RK |
68 | }; |
69 | ||
70 | static struct cachepolicy cache_policies[] __initdata = { | |
71 | { | |
72 | .policy = "uncached", | |
73 | .cr_mask = CR_W|CR_C, | |
74 | .pmd = PMD_SECT_UNCACHED, | |
bb30f36f | 75 | .pte = L_PTE_MT_UNCACHED, |
ae8f1541 RK |
76 | }, { |
77 | .policy = "buffered", | |
78 | .cr_mask = CR_C, | |
79 | .pmd = PMD_SECT_BUFFERED, | |
bb30f36f | 80 | .pte = L_PTE_MT_BUFFERABLE, |
ae8f1541 RK |
81 | }, { |
82 | .policy = "writethrough", | |
83 | .cr_mask = 0, | |
84 | .pmd = PMD_SECT_WT, | |
bb30f36f | 85 | .pte = L_PTE_MT_WRITETHROUGH, |
ae8f1541 RK |
86 | }, { |
87 | .policy = "writeback", | |
88 | .cr_mask = 0, | |
89 | .pmd = PMD_SECT_WB, | |
bb30f36f | 90 | .pte = L_PTE_MT_WRITEBACK, |
ae8f1541 RK |
91 | }, { |
92 | .policy = "writealloc", | |
93 | .cr_mask = 0, | |
94 | .pmd = PMD_SECT_WBWA, | |
bb30f36f | 95 | .pte = L_PTE_MT_WRITEALLOC, |
ae8f1541 RK |
96 | } |
97 | }; | |
98 | ||
99 | /* | |
6cbdc8c5 | 100 | * These are useful for identifying cache coherency |
ae8f1541 RK |
101 | * problems by allowing the cache or the cache and |
102 | * writebuffer to be turned off. (Note: the write | |
103 | * buffer should not be on and the cache off). | |
104 | */ | |
2b0d8c25 | 105 | static int __init early_cachepolicy(char *p) |
ae8f1541 RK |
106 | { |
107 | int i; | |
108 | ||
109 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { | |
110 | int len = strlen(cache_policies[i].policy); | |
111 | ||
2b0d8c25 | 112 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
ae8f1541 RK |
113 | cachepolicy = i; |
114 | cr_alignment &= ~cache_policies[i].cr_mask; | |
115 | cr_no_alignment &= ~cache_policies[i].cr_mask; | |
ae8f1541 RK |
116 | break; |
117 | } | |
118 | } | |
119 | if (i == ARRAY_SIZE(cache_policies)) | |
120 | printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); | |
4b46d641 RK |
121 | /* |
122 | * This restriction is partly to do with the way we boot; it is | |
123 | * unpredictable to have memory mapped using two different sets of | |
124 | * memory attributes (shared, type, and cache attribs). We can not | |
125 | * change these attributes once the initial assembly has setup the | |
126 | * page tables. | |
127 | */ | |
11179d8c CM |
128 | if (cpu_architecture() >= CPU_ARCH_ARMv6) { |
129 | printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); | |
130 | cachepolicy = CPOLICY_WRITEBACK; | |
131 | } | |
ae8f1541 RK |
132 | flush_cache_all(); |
133 | set_cr(cr_alignment); | |
2b0d8c25 | 134 | return 0; |
ae8f1541 | 135 | } |
2b0d8c25 | 136 | early_param("cachepolicy", early_cachepolicy); |
ae8f1541 | 137 | |
2b0d8c25 | 138 | static int __init early_nocache(char *__unused) |
ae8f1541 RK |
139 | { |
140 | char *p = "buffered"; | |
141 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
142 | early_cachepolicy(p); |
143 | return 0; | |
ae8f1541 | 144 | } |
2b0d8c25 | 145 | early_param("nocache", early_nocache); |
ae8f1541 | 146 | |
2b0d8c25 | 147 | static int __init early_nowrite(char *__unused) |
ae8f1541 RK |
148 | { |
149 | char *p = "uncached"; | |
150 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
151 | early_cachepolicy(p); |
152 | return 0; | |
ae8f1541 | 153 | } |
2b0d8c25 | 154 | early_param("nowb", early_nowrite); |
ae8f1541 | 155 | |
1b6ba46b | 156 | #ifndef CONFIG_ARM_LPAE |
2b0d8c25 | 157 | static int __init early_ecc(char *p) |
ae8f1541 | 158 | { |
2b0d8c25 | 159 | if (memcmp(p, "on", 2) == 0) |
ae8f1541 | 160 | ecc_mask = PMD_PROTECTION; |
2b0d8c25 | 161 | else if (memcmp(p, "off", 3) == 0) |
ae8f1541 | 162 | ecc_mask = 0; |
2b0d8c25 | 163 | return 0; |
ae8f1541 | 164 | } |
2b0d8c25 | 165 | early_param("ecc", early_ecc); |
1b6ba46b | 166 | #endif |
ae8f1541 RK |
167 | |
168 | static int __init noalign_setup(char *__unused) | |
169 | { | |
170 | cr_alignment &= ~CR_A; | |
171 | cr_no_alignment &= ~CR_A; | |
172 | set_cr(cr_alignment); | |
173 | return 1; | |
174 | } | |
175 | __setup("noalign", noalign_setup); | |
176 | ||
255d1f86 RK |
177 | #ifndef CONFIG_SMP |
178 | void adjust_cr(unsigned long mask, unsigned long set) | |
179 | { | |
180 | unsigned long flags; | |
181 | ||
182 | mask &= ~CR_A; | |
183 | ||
184 | set &= mask; | |
185 | ||
186 | local_irq_save(flags); | |
187 | ||
188 | cr_no_alignment = (cr_no_alignment & ~mask) | set; | |
189 | cr_alignment = (cr_alignment & ~mask) | set; | |
190 | ||
191 | set_cr((get_cr() & ~mask) | set); | |
192 | ||
193 | local_irq_restore(flags); | |
194 | } | |
195 | #endif | |
196 | ||
36bb94ba | 197 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN |
b1cce6b1 | 198 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
0af92bef | 199 | |
b29e9f5e | 200 | static struct mem_type mem_types[] = { |
0af92bef | 201 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
bb30f36f RK |
202 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
203 | L_PTE_SHARED, | |
0af92bef | 204 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 205 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
0af92bef RK |
206 | .domain = DOMAIN_IO, |
207 | }, | |
208 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ | |
bb30f36f | 209 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
0af92bef | 210 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 211 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef RK |
212 | .domain = DOMAIN_IO, |
213 | }, | |
214 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ | |
bb30f36f | 215 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
0af92bef RK |
216 | .prot_l1 = PMD_TYPE_TABLE, |
217 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, | |
218 | .domain = DOMAIN_IO, | |
219 | }, | |
1ad77a87 | 220 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
bb30f36f | 221 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
0af92bef | 222 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 223 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef | 224 | .domain = DOMAIN_IO, |
ae8f1541 | 225 | }, |
ebb4c658 RK |
226 | [MT_UNCACHED] = { |
227 | .prot_pte = PROT_PTE_DEVICE, | |
228 | .prot_l1 = PMD_TYPE_TABLE, | |
229 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
230 | .domain = DOMAIN_IO, | |
231 | }, | |
ae8f1541 | 232 | [MT_CACHECLEAN] = { |
9ef79635 | 233 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
ae8f1541 RK |
234 | .domain = DOMAIN_KERNEL, |
235 | }, | |
1b6ba46b | 236 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 | 237 | [MT_MINICLEAN] = { |
9ef79635 | 238 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
ae8f1541 RK |
239 | .domain = DOMAIN_KERNEL, |
240 | }, | |
1b6ba46b | 241 | #endif |
ae8f1541 RK |
242 | [MT_LOW_VECTORS] = { |
243 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 244 | L_PTE_RDONLY, |
ae8f1541 RK |
245 | .prot_l1 = PMD_TYPE_TABLE, |
246 | .domain = DOMAIN_USER, | |
247 | }, | |
248 | [MT_HIGH_VECTORS] = { | |
249 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 250 | L_PTE_USER | L_PTE_RDONLY, |
ae8f1541 RK |
251 | .prot_l1 = PMD_TYPE_TABLE, |
252 | .domain = DOMAIN_USER, | |
253 | }, | |
254 | [MT_MEMORY] = { | |
36bb94ba | 255 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
f1a2481c | 256 | .prot_l1 = PMD_TYPE_TABLE, |
9ef79635 | 257 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
ae8f1541 RK |
258 | .domain = DOMAIN_KERNEL, |
259 | }, | |
260 | [MT_ROM] = { | |
9ef79635 | 261 | .prot_sect = PMD_TYPE_SECT, |
ae8f1541 RK |
262 | .domain = DOMAIN_KERNEL, |
263 | }, | |
e4707dd3 | 264 | [MT_MEMORY_NONCACHED] = { |
f1a2481c | 265 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 266 | L_PTE_MT_BUFFERABLE, |
f1a2481c | 267 | .prot_l1 = PMD_TYPE_TABLE, |
e4707dd3 PW |
268 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
269 | .domain = DOMAIN_KERNEL, | |
270 | }, | |
cb9d7707 | 271 | [MT_MEMORY_DTCM] = { |
f444fce3 | 272 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 273 | L_PTE_XN, |
f444fce3 LW |
274 | .prot_l1 = PMD_TYPE_TABLE, |
275 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
276 | .domain = DOMAIN_KERNEL, | |
cb9d7707 LW |
277 | }, |
278 | [MT_MEMORY_ITCM] = { | |
36bb94ba | 279 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
cb9d7707 | 280 | .prot_l1 = PMD_TYPE_TABLE, |
f444fce3 | 281 | .domain = DOMAIN_KERNEL, |
cb9d7707 | 282 | }, |
8fb54284 SS |
283 | [MT_MEMORY_SO] = { |
284 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
285 | L_PTE_MT_UNCACHED, | |
286 | .prot_l1 = PMD_TYPE_TABLE, | |
287 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | | |
288 | PMD_SECT_UNCACHED | PMD_SECT_XN, | |
289 | .domain = DOMAIN_KERNEL, | |
290 | }, | |
c7909509 MS |
291 | [MT_MEMORY_DMA_READY] = { |
292 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, | |
293 | .prot_l1 = PMD_TYPE_TABLE, | |
294 | .domain = DOMAIN_KERNEL, | |
295 | }, | |
ae8f1541 RK |
296 | }; |
297 | ||
b29e9f5e RK |
298 | const struct mem_type *get_mem_type(unsigned int type) |
299 | { | |
300 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; | |
301 | } | |
69d3a84a | 302 | EXPORT_SYMBOL(get_mem_type); |
b29e9f5e | 303 | |
ae8f1541 RK |
304 | /* |
305 | * Adjust the PMD section entries according to the CPU in use. | |
306 | */ | |
307 | static void __init build_mem_type_table(void) | |
308 | { | |
309 | struct cachepolicy *cp; | |
310 | unsigned int cr = get_cr(); | |
442e70c0 | 311 | pteval_t user_pgprot, kern_pgprot, vecs_pgprot; |
ae8f1541 RK |
312 | int cpu_arch = cpu_architecture(); |
313 | int i; | |
314 | ||
11179d8c | 315 | if (cpu_arch < CPU_ARCH_ARMv6) { |
ae8f1541 | 316 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
11179d8c CM |
317 | if (cachepolicy > CPOLICY_BUFFERED) |
318 | cachepolicy = CPOLICY_BUFFERED; | |
ae8f1541 | 319 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
11179d8c CM |
320 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
321 | cachepolicy = CPOLICY_WRITETHROUGH; | |
ae8f1541 | 322 | #endif |
11179d8c | 323 | } |
ae8f1541 RK |
324 | if (cpu_arch < CPU_ARCH_ARMv5) { |
325 | if (cachepolicy >= CPOLICY_WRITEALLOC) | |
326 | cachepolicy = CPOLICY_WRITEBACK; | |
327 | ecc_mask = 0; | |
328 | } | |
f00ec48f RK |
329 | if (is_smp()) |
330 | cachepolicy = CPOLICY_WRITEALLOC; | |
ae8f1541 | 331 | |
1ad77a87 | 332 | /* |
b1cce6b1 RK |
333 | * Strip out features not present on earlier architectures. |
334 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those | |
335 | * without extended page tables don't have the 'Shared' bit. | |
1ad77a87 | 336 | */ |
b1cce6b1 RK |
337 | if (cpu_arch < CPU_ARCH_ARMv5) |
338 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
339 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); | |
340 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) | |
341 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
342 | mem_types[i].prot_sect &= ~PMD_SECT_S; | |
ae8f1541 RK |
343 | |
344 | /* | |
b1cce6b1 RK |
345 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
346 | * "update-able on write" bit on ARM610). However, Xscale and | |
347 | * Xscale3 require this bit to be cleared. | |
ae8f1541 | 348 | */ |
b1cce6b1 | 349 | if (cpu_is_xscale() || cpu_is_xsc3()) { |
9ef79635 | 350 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
ae8f1541 | 351 | mem_types[i].prot_sect &= ~PMD_BIT4; |
9ef79635 RK |
352 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
353 | } | |
354 | } else if (cpu_arch < CPU_ARCH_ARMv6) { | |
355 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 RK |
356 | if (mem_types[i].prot_l1) |
357 | mem_types[i].prot_l1 |= PMD_BIT4; | |
9ef79635 RK |
358 | if (mem_types[i].prot_sect) |
359 | mem_types[i].prot_sect |= PMD_BIT4; | |
360 | } | |
361 | } | |
ae8f1541 | 362 | |
b1cce6b1 RK |
363 | /* |
364 | * Mark the device areas according to the CPU/architecture. | |
365 | */ | |
366 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { | |
367 | if (!cpu_is_xsc3()) { | |
368 | /* | |
369 | * Mark device regions on ARMv6+ as execute-never | |
370 | * to prevent speculative instruction fetches. | |
371 | */ | |
372 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; | |
373 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; | |
374 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; | |
375 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; | |
376 | } | |
377 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
378 | /* | |
379 | * For ARMv7 with TEX remapping, | |
380 | * - shared device is SXCB=1100 | |
381 | * - nonshared device is SXCB=0100 | |
382 | * - write combine device mem is SXCB=0001 | |
383 | * (Uncached Normal memory) | |
384 | */ | |
385 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); | |
386 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); | |
387 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
388 | } else if (cpu_is_xsc3()) { | |
389 | /* | |
390 | * For Xscale3, | |
391 | * - shared device is TEXCB=00101 | |
392 | * - nonshared device is TEXCB=01000 | |
393 | * - write combine device mem is TEXCB=00100 | |
394 | * (Inner/Outer Uncacheable in xsc3 parlance) | |
395 | */ | |
396 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; | |
397 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
398 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
399 | } else { | |
400 | /* | |
401 | * For ARMv6 and ARMv7 without TEX remapping, | |
402 | * - shared device is TEXCB=00001 | |
403 | * - nonshared device is TEXCB=01000 | |
404 | * - write combine device mem is TEXCB=00100 | |
405 | * (Uncached Normal in ARMv6 parlance). | |
406 | */ | |
407 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; | |
408 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
409 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
410 | } | |
411 | } else { | |
412 | /* | |
413 | * On others, write combining is "Uncached/Buffered" | |
414 | */ | |
415 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
416 | } | |
417 | ||
418 | /* | |
419 | * Now deal with the memory-type mappings | |
420 | */ | |
ae8f1541 | 421 | cp = &cache_policies[cachepolicy]; |
bb30f36f RK |
422 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
423 | ||
bb30f36f RK |
424 | /* |
425 | * Only use write-through for non-SMP systems | |
426 | */ | |
f00ec48f | 427 | if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) |
bb30f36f | 428 | vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte; |
ae8f1541 RK |
429 | |
430 | /* | |
431 | * Enable CPU-specific coherency if supported. | |
432 | * (Only available on XSC3 at the moment.) | |
433 | */ | |
f1a2481c | 434 | if (arch_is_coherent() && cpu_is_xsc3()) { |
b1cce6b1 | 435 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
f1a2481c | 436 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; |
c7909509 | 437 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; |
f1a2481c SS |
438 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; |
439 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; | |
440 | } | |
ae8f1541 RK |
441 | /* |
442 | * ARMv6 and above have extended page tables. | |
443 | */ | |
444 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { | |
1b6ba46b | 445 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
446 | /* |
447 | * Mark cache clean areas and XIP ROM read only | |
448 | * from SVC mode and no access from userspace. | |
449 | */ | |
450 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
451 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
452 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
1b6ba46b | 453 | #endif |
ae8f1541 | 454 | |
f00ec48f RK |
455 | if (is_smp()) { |
456 | /* | |
457 | * Mark memory with the "shared" attribute | |
458 | * for SMP systems | |
459 | */ | |
460 | user_pgprot |= L_PTE_SHARED; | |
461 | kern_pgprot |= L_PTE_SHARED; | |
462 | vecs_pgprot |= L_PTE_SHARED; | |
463 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; | |
464 | mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; | |
465 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; | |
466 | mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; | |
467 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; | |
468 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; | |
c7909509 | 469 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; |
f00ec48f RK |
470 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; |
471 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; | |
472 | } | |
ae8f1541 RK |
473 | } |
474 | ||
e4707dd3 PW |
475 | /* |
476 | * Non-cacheable Normal - intended for memory areas that must | |
477 | * not cause dirty cache line writebacks when used | |
478 | */ | |
479 | if (cpu_arch >= CPU_ARCH_ARMv6) { | |
480 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
481 | /* Non-cacheable Normal is XCB = 001 */ | |
482 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
483 | PMD_SECT_BUFFERED; | |
484 | } else { | |
485 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | |
486 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
487 | PMD_SECT_TEX(1); | |
488 | } | |
489 | } else { | |
490 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; | |
491 | } | |
492 | ||
1b6ba46b CM |
493 | #ifdef CONFIG_ARM_LPAE |
494 | /* | |
495 | * Do not generate access flag faults for the kernel mappings. | |
496 | */ | |
497 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
498 | mem_types[i].prot_pte |= PTE_EXT_AF; | |
1a3abcf4 VA |
499 | if (mem_types[i].prot_sect) |
500 | mem_types[i].prot_sect |= PMD_SECT_AF; | |
1b6ba46b CM |
501 | } |
502 | kern_pgprot |= PTE_EXT_AF; | |
503 | vecs_pgprot |= PTE_EXT_AF; | |
504 | #endif | |
505 | ||
ae8f1541 RK |
506 | for (i = 0; i < 16; i++) { |
507 | unsigned long v = pgprot_val(protection_map[i]); | |
bb30f36f | 508 | protection_map[i] = __pgprot(v | user_pgprot); |
ae8f1541 RK |
509 | } |
510 | ||
bb30f36f RK |
511 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
512 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; | |
ae8f1541 | 513 | |
44b18693 | 514 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
ae8f1541 | 515 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
36bb94ba | 516 | L_PTE_DIRTY | kern_pgprot); |
ae8f1541 RK |
517 | |
518 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | |
519 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | |
520 | mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; | |
f1a2481c | 521 | mem_types[MT_MEMORY].prot_pte |= kern_pgprot; |
c7909509 | 522 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; |
f1a2481c | 523 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; |
ae8f1541 RK |
524 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
525 | ||
526 | switch (cp->pmd) { | |
527 | case PMD_SECT_WT: | |
528 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; | |
529 | break; | |
530 | case PMD_SECT_WB: | |
531 | case PMD_SECT_WBWA: | |
532 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; | |
533 | break; | |
534 | } | |
535 | printk("Memory policy: ECC %sabled, Data cache %s\n", | |
536 | ecc_mask ? "en" : "dis", cp->policy); | |
2497f0a8 RK |
537 | |
538 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
539 | struct mem_type *t = &mem_types[i]; | |
540 | if (t->prot_l1) | |
541 | t->prot_l1 |= PMD_DOMAIN(t->domain); | |
542 | if (t->prot_sect) | |
543 | t->prot_sect |= PMD_DOMAIN(t->domain); | |
544 | } | |
ae8f1541 RK |
545 | } |
546 | ||
d907387c CM |
547 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE |
548 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
549 | unsigned long size, pgprot_t vma_prot) | |
550 | { | |
551 | if (!pfn_valid(pfn)) | |
552 | return pgprot_noncached(vma_prot); | |
553 | else if (file->f_flags & O_SYNC) | |
554 | return pgprot_writecombine(vma_prot); | |
555 | return vma_prot; | |
556 | } | |
557 | EXPORT_SYMBOL(phys_mem_access_prot); | |
558 | #endif | |
559 | ||
ae8f1541 RK |
560 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
561 | ||
0536bdf3 | 562 | static void __init *early_alloc_aligned(unsigned long sz, unsigned long align) |
3abe9d33 | 563 | { |
0536bdf3 | 564 | void *ptr = __va(memblock_alloc(sz, align)); |
2778f620 RK |
565 | memset(ptr, 0, sz); |
566 | return ptr; | |
3abe9d33 RK |
567 | } |
568 | ||
0536bdf3 NP |
569 | static void __init *early_alloc(unsigned long sz) |
570 | { | |
571 | return early_alloc_aligned(sz, sz); | |
572 | } | |
573 | ||
4bb2e27d | 574 | static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) |
ae8f1541 | 575 | { |
24e6c699 | 576 | if (pmd_none(*pmd)) { |
410f1483 | 577 | pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); |
97092e0c | 578 | __pmd_populate(pmd, __pa(pte), prot); |
24e6c699 | 579 | } |
4bb2e27d RK |
580 | BUG_ON(pmd_bad(*pmd)); |
581 | return pte_offset_kernel(pmd, addr); | |
582 | } | |
ae8f1541 | 583 | |
4bb2e27d RK |
584 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
585 | unsigned long end, unsigned long pfn, | |
586 | const struct mem_type *type) | |
587 | { | |
588 | pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); | |
24e6c699 | 589 | do { |
40d192b6 | 590 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); |
24e6c699 RK |
591 | pfn++; |
592 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
ae8f1541 RK |
593 | } |
594 | ||
516295e5 | 595 | static void __init alloc_init_section(pud_t *pud, unsigned long addr, |
97092e0c | 596 | unsigned long end, phys_addr_t phys, |
24e6c699 | 597 | const struct mem_type *type) |
ae8f1541 | 598 | { |
516295e5 | 599 | pmd_t *pmd = pmd_offset(pud, addr); |
ae8f1541 | 600 | |
24e6c699 RK |
601 | /* |
602 | * Try a section mapping - end, addr and phys must all be aligned | |
603 | * to a section boundary. Note that PMDs refer to the individual | |
604 | * L1 entries, whereas PGDs refer to a group of L1 entries making | |
605 | * up one logical pointer to an L2 table. | |
606 | */ | |
c7909509 | 607 | if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) { |
24e6c699 | 608 | pmd_t *p = pmd; |
ae8f1541 | 609 | |
1b6ba46b | 610 | #ifndef CONFIG_ARM_LPAE |
24e6c699 RK |
611 | if (addr & SECTION_SIZE) |
612 | pmd++; | |
1b6ba46b | 613 | #endif |
24e6c699 RK |
614 | |
615 | do { | |
616 | *pmd = __pmd(phys | type->prot_sect); | |
617 | phys += SECTION_SIZE; | |
618 | } while (pmd++, addr += SECTION_SIZE, addr != end); | |
ae8f1541 | 619 | |
24e6c699 RK |
620 | flush_pmd_entry(p); |
621 | } else { | |
622 | /* | |
623 | * No need to loop; pte's aren't interested in the | |
624 | * individual L1 entries. | |
625 | */ | |
626 | alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); | |
627 | } | |
ae8f1541 RK |
628 | } |
629 | ||
14904927 SB |
630 | static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, |
631 | unsigned long end, unsigned long phys, const struct mem_type *type) | |
516295e5 RK |
632 | { |
633 | pud_t *pud = pud_offset(pgd, addr); | |
634 | unsigned long next; | |
635 | ||
636 | do { | |
637 | next = pud_addr_end(addr, end); | |
638 | alloc_init_section(pud, addr, next, phys, type); | |
639 | phys += next - addr; | |
640 | } while (pud++, addr = next, addr != end); | |
641 | } | |
642 | ||
1b6ba46b | 643 | #ifndef CONFIG_ARM_LPAE |
4a56c1e4 RK |
644 | static void __init create_36bit_mapping(struct map_desc *md, |
645 | const struct mem_type *type) | |
646 | { | |
97092e0c RK |
647 | unsigned long addr, length, end; |
648 | phys_addr_t phys; | |
4a56c1e4 RK |
649 | pgd_t *pgd; |
650 | ||
651 | addr = md->virtual; | |
cae6292b | 652 | phys = __pfn_to_phys(md->pfn); |
4a56c1e4 RK |
653 | length = PAGE_ALIGN(md->length); |
654 | ||
655 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { | |
656 | printk(KERN_ERR "MM: CPU does not support supersection " | |
657 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 658 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
659 | return; |
660 | } | |
661 | ||
662 | /* N.B. ARMv6 supersections are only defined to work with domain 0. | |
663 | * Since domain assignments can in fact be arbitrary, the | |
664 | * 'domain == 0' check below is required to insure that ARMv6 | |
665 | * supersections are only allocated for domain 0 regardless | |
666 | * of the actual domain assignments in use. | |
667 | */ | |
668 | if (type->domain) { | |
669 | printk(KERN_ERR "MM: invalid domain in supersection " | |
670 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 671 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
672 | return; |
673 | } | |
674 | ||
675 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { | |
29a38193 WD |
676 | printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" |
677 | " at 0x%08lx invalid alignment\n", | |
678 | (long long)__pfn_to_phys((u64)md->pfn), addr); | |
4a56c1e4 RK |
679 | return; |
680 | } | |
681 | ||
682 | /* | |
683 | * Shift bits [35:32] of address into bits [23:20] of PMD | |
684 | * (See ARMv6 spec). | |
685 | */ | |
686 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); | |
687 | ||
688 | pgd = pgd_offset_k(addr); | |
689 | end = addr + length; | |
690 | do { | |
516295e5 RK |
691 | pud_t *pud = pud_offset(pgd, addr); |
692 | pmd_t *pmd = pmd_offset(pud, addr); | |
4a56c1e4 RK |
693 | int i; |
694 | ||
695 | for (i = 0; i < 16; i++) | |
696 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); | |
697 | ||
698 | addr += SUPERSECTION_SIZE; | |
699 | phys += SUPERSECTION_SIZE; | |
700 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; | |
701 | } while (addr != end); | |
702 | } | |
1b6ba46b | 703 | #endif /* !CONFIG_ARM_LPAE */ |
4a56c1e4 | 704 | |
ae8f1541 RK |
705 | /* |
706 | * Create the page directory entries and any necessary | |
707 | * page tables for the mapping specified by `md'. We | |
708 | * are able to cope here with varying sizes and address | |
709 | * offsets, and we take full advantage of sections and | |
710 | * supersections. | |
711 | */ | |
a2227120 | 712 | static void __init create_mapping(struct map_desc *md) |
ae8f1541 | 713 | { |
cae6292b WD |
714 | unsigned long addr, length, end; |
715 | phys_addr_t phys; | |
d5c98176 | 716 | const struct mem_type *type; |
24e6c699 | 717 | pgd_t *pgd; |
ae8f1541 RK |
718 | |
719 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { | |
29a38193 WD |
720 | printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" |
721 | " at 0x%08lx in user region\n", | |
722 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
ae8f1541 RK |
723 | return; |
724 | } | |
725 | ||
726 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && | |
0536bdf3 NP |
727 | md->virtual >= PAGE_OFFSET && |
728 | (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { | |
29a38193 | 729 | printk(KERN_WARNING "BUG: mapping for 0x%08llx" |
0536bdf3 | 730 | " at 0x%08lx out of vmalloc space\n", |
29a38193 | 731 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); |
ae8f1541 RK |
732 | } |
733 | ||
d5c98176 | 734 | type = &mem_types[md->type]; |
ae8f1541 | 735 | |
1b6ba46b | 736 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
737 | /* |
738 | * Catch 36-bit addresses | |
739 | */ | |
4a56c1e4 RK |
740 | if (md->pfn >= 0x100000) { |
741 | create_36bit_mapping(md, type); | |
742 | return; | |
ae8f1541 | 743 | } |
1b6ba46b | 744 | #endif |
ae8f1541 | 745 | |
7b9c7b4d | 746 | addr = md->virtual & PAGE_MASK; |
cae6292b | 747 | phys = __pfn_to_phys(md->pfn); |
7b9c7b4d | 748 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
ae8f1541 | 749 | |
24e6c699 | 750 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
29a38193 | 751 | printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " |
ae8f1541 | 752 | "be mapped using pages, ignoring.\n", |
29a38193 | 753 | (long long)__pfn_to_phys(md->pfn), addr); |
ae8f1541 RK |
754 | return; |
755 | } | |
756 | ||
24e6c699 RK |
757 | pgd = pgd_offset_k(addr); |
758 | end = addr + length; | |
759 | do { | |
760 | unsigned long next = pgd_addr_end(addr, end); | |
ae8f1541 | 761 | |
516295e5 | 762 | alloc_init_pud(pgd, addr, next, phys, type); |
ae8f1541 | 763 | |
24e6c699 RK |
764 | phys += next - addr; |
765 | addr = next; | |
766 | } while (pgd++, addr != end); | |
ae8f1541 RK |
767 | } |
768 | ||
769 | /* | |
770 | * Create the architecture specific mappings | |
771 | */ | |
772 | void __init iotable_init(struct map_desc *io_desc, int nr) | |
773 | { | |
0536bdf3 NP |
774 | struct map_desc *md; |
775 | struct vm_struct *vm; | |
776 | ||
777 | if (!nr) | |
778 | return; | |
ae8f1541 | 779 | |
0536bdf3 NP |
780 | vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm)); |
781 | ||
782 | for (md = io_desc; nr; md++, nr--) { | |
783 | create_mapping(md); | |
784 | vm->addr = (void *)(md->virtual & PAGE_MASK); | |
785 | vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); | |
786 | vm->phys_addr = __pfn_to_phys(md->pfn); | |
576d2f25 NP |
787 | vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; |
788 | vm->flags |= VM_ARM_MTYPE(md->type); | |
0536bdf3 NP |
789 | vm->caller = iotable_init; |
790 | vm_area_add_early(vm++); | |
791 | } | |
ae8f1541 RK |
792 | } |
793 | ||
19b52abe NP |
794 | #ifndef CONFIG_ARM_LPAE |
795 | ||
796 | /* | |
797 | * The Linux PMD is made of two consecutive section entries covering 2MB | |
798 | * (see definition in include/asm/pgtable-2level.h). However a call to | |
799 | * create_mapping() may optimize static mappings by using individual | |
800 | * 1MB section mappings. This leaves the actual PMD potentially half | |
801 | * initialized if the top or bottom section entry isn't used, leaving it | |
802 | * open to problems if a subsequent ioremap() or vmalloc() tries to use | |
803 | * the virtual space left free by that unused section entry. | |
804 | * | |
805 | * Let's avoid the issue by inserting dummy vm entries covering the unused | |
806 | * PMD halves once the static mappings are in place. | |
807 | */ | |
808 | ||
809 | static void __init pmd_empty_section_gap(unsigned long addr) | |
810 | { | |
811 | struct vm_struct *vm; | |
812 | ||
813 | vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm)); | |
814 | vm->addr = (void *)addr; | |
815 | vm->size = SECTION_SIZE; | |
816 | vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; | |
817 | vm->caller = pmd_empty_section_gap; | |
818 | vm_area_add_early(vm); | |
819 | } | |
820 | ||
821 | static void __init fill_pmd_gaps(void) | |
822 | { | |
823 | struct vm_struct *vm; | |
824 | unsigned long addr, next = 0; | |
825 | pmd_t *pmd; | |
826 | ||
827 | /* we're still single threaded hence no lock needed here */ | |
828 | for (vm = vmlist; vm; vm = vm->next) { | |
829 | if (!(vm->flags & VM_ARM_STATIC_MAPPING)) | |
830 | continue; | |
831 | addr = (unsigned long)vm->addr; | |
832 | if (addr < next) | |
833 | continue; | |
834 | ||
835 | /* | |
836 | * Check if this vm starts on an odd section boundary. | |
837 | * If so and the first section entry for this PMD is free | |
838 | * then we block the corresponding virtual address. | |
839 | */ | |
840 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
841 | pmd = pmd_off_k(addr); | |
842 | if (pmd_none(*pmd)) | |
843 | pmd_empty_section_gap(addr & PMD_MASK); | |
844 | } | |
845 | ||
846 | /* | |
847 | * Then check if this vm ends on an odd section boundary. | |
848 | * If so and the second section entry for this PMD is empty | |
849 | * then we block the corresponding virtual address. | |
850 | */ | |
851 | addr += vm->size; | |
852 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
853 | pmd = pmd_off_k(addr) + 1; | |
854 | if (pmd_none(*pmd)) | |
855 | pmd_empty_section_gap(addr); | |
856 | } | |
857 | ||
858 | /* no need to look at any vm entry until we hit the next PMD */ | |
859 | next = (addr + PMD_SIZE - 1) & PMD_MASK; | |
860 | } | |
861 | } | |
862 | ||
863 | #else | |
864 | #define fill_pmd_gaps() do { } while (0) | |
865 | #endif | |
866 | ||
0536bdf3 NP |
867 | static void * __initdata vmalloc_min = |
868 | (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); | |
6c5da7ac RK |
869 | |
870 | /* | |
871 | * vmalloc=size forces the vmalloc area to be exactly 'size' | |
872 | * bytes. This can be used to increase (or decrease) the vmalloc | |
0536bdf3 | 873 | * area - the default is 240m. |
6c5da7ac | 874 | */ |
2b0d8c25 | 875 | static int __init early_vmalloc(char *arg) |
6c5da7ac | 876 | { |
79612395 | 877 | unsigned long vmalloc_reserve = memparse(arg, NULL); |
6c5da7ac RK |
878 | |
879 | if (vmalloc_reserve < SZ_16M) { | |
880 | vmalloc_reserve = SZ_16M; | |
881 | printk(KERN_WARNING | |
882 | "vmalloc area too small, limiting to %luMB\n", | |
883 | vmalloc_reserve >> 20); | |
884 | } | |
9210807c NP |
885 | |
886 | if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { | |
887 | vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); | |
888 | printk(KERN_WARNING | |
889 | "vmalloc area is too big, limiting to %luMB\n", | |
890 | vmalloc_reserve >> 20); | |
891 | } | |
79612395 RK |
892 | |
893 | vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); | |
2b0d8c25 | 894 | return 0; |
6c5da7ac | 895 | } |
2b0d8c25 | 896 | early_param("vmalloc", early_vmalloc); |
6c5da7ac | 897 | |
c7909509 | 898 | phys_addr_t arm_lowmem_limit __initdata = 0; |
8df65168 | 899 | |
0371d3f7 | 900 | void __init sanity_check_meminfo(void) |
60296c71 | 901 | { |
dde5828f | 902 | int i, j, highmem = 0; |
60296c71 | 903 | |
4b5f32ce | 904 | for (i = 0, j = 0; i < meminfo.nr_banks; i++) { |
a1bbaec0 NP |
905 | struct membank *bank = &meminfo.bank[j]; |
906 | *bank = meminfo.bank[i]; | |
60296c71 | 907 | |
77f73a2c WD |
908 | if (bank->start > ULONG_MAX) |
909 | highmem = 1; | |
910 | ||
a1bbaec0 | 911 | #ifdef CONFIG_HIGHMEM |
40f7bfe4 | 912 | if (__va(bank->start) >= vmalloc_min || |
dde5828f RK |
913 | __va(bank->start) < (void *)PAGE_OFFSET) |
914 | highmem = 1; | |
915 | ||
916 | bank->highmem = highmem; | |
917 | ||
a1bbaec0 NP |
918 | /* |
919 | * Split those memory banks which are partially overlapping | |
920 | * the vmalloc area greatly simplifying things later. | |
921 | */ | |
77f73a2c | 922 | if (!highmem && __va(bank->start) < vmalloc_min && |
79612395 | 923 | bank->size > vmalloc_min - __va(bank->start)) { |
a1bbaec0 NP |
924 | if (meminfo.nr_banks >= NR_BANKS) { |
925 | printk(KERN_CRIT "NR_BANKS too low, " | |
926 | "ignoring high memory\n"); | |
927 | } else { | |
928 | memmove(bank + 1, bank, | |
929 | (meminfo.nr_banks - i) * sizeof(*bank)); | |
930 | meminfo.nr_banks++; | |
931 | i++; | |
79612395 RK |
932 | bank[1].size -= vmalloc_min - __va(bank->start); |
933 | bank[1].start = __pa(vmalloc_min - 1) + 1; | |
dde5828f | 934 | bank[1].highmem = highmem = 1; |
a1bbaec0 NP |
935 | j++; |
936 | } | |
79612395 | 937 | bank->size = vmalloc_min - __va(bank->start); |
a1bbaec0 NP |
938 | } |
939 | #else | |
041d785f RK |
940 | bank->highmem = highmem; |
941 | ||
77f73a2c WD |
942 | /* |
943 | * Highmem banks not allowed with !CONFIG_HIGHMEM. | |
944 | */ | |
945 | if (highmem) { | |
946 | printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " | |
947 | "(!CONFIG_HIGHMEM).\n", | |
948 | (unsigned long long)bank->start, | |
949 | (unsigned long long)bank->start + bank->size - 1); | |
950 | continue; | |
951 | } | |
952 | ||
a1bbaec0 NP |
953 | /* |
954 | * Check whether this memory bank would entirely overlap | |
955 | * the vmalloc area. | |
956 | */ | |
79612395 | 957 | if (__va(bank->start) >= vmalloc_min || |
f0bba9f9 | 958 | __va(bank->start) < (void *)PAGE_OFFSET) { |
e33b9d08 | 959 | printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " |
a1bbaec0 | 960 | "(vmalloc region overlap).\n", |
e33b9d08 RK |
961 | (unsigned long long)bank->start, |
962 | (unsigned long long)bank->start + bank->size - 1); | |
a1bbaec0 NP |
963 | continue; |
964 | } | |
60296c71 | 965 | |
a1bbaec0 NP |
966 | /* |
967 | * Check whether this memory bank would partially overlap | |
968 | * the vmalloc area. | |
969 | */ | |
79612395 | 970 | if (__va(bank->start + bank->size) > vmalloc_min || |
a1bbaec0 | 971 | __va(bank->start + bank->size) < __va(bank->start)) { |
79612395 | 972 | unsigned long newsize = vmalloc_min - __va(bank->start); |
e33b9d08 RK |
973 | printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " |
974 | "to -%.8llx (vmalloc region overlap).\n", | |
975 | (unsigned long long)bank->start, | |
976 | (unsigned long long)bank->start + bank->size - 1, | |
977 | (unsigned long long)bank->start + newsize - 1); | |
a1bbaec0 NP |
978 | bank->size = newsize; |
979 | } | |
980 | #endif | |
c7909509 MS |
981 | if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit) |
982 | arm_lowmem_limit = bank->start + bank->size; | |
40f7bfe4 | 983 | |
a1bbaec0 | 984 | j++; |
60296c71 | 985 | } |
e616c591 RK |
986 | #ifdef CONFIG_HIGHMEM |
987 | if (highmem) { | |
988 | const char *reason = NULL; | |
989 | ||
990 | if (cache_is_vipt_aliasing()) { | |
991 | /* | |
992 | * Interactions between kmap and other mappings | |
993 | * make highmem support with aliasing VIPT caches | |
994 | * rather difficult. | |
995 | */ | |
996 | reason = "with VIPT aliasing cache"; | |
e616c591 RK |
997 | } |
998 | if (reason) { | |
999 | printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", | |
1000 | reason); | |
1001 | while (j > 0 && meminfo.bank[j - 1].highmem) | |
1002 | j--; | |
1003 | } | |
1004 | } | |
1005 | #endif | |
4b5f32ce | 1006 | meminfo.nr_banks = j; |
c7909509 MS |
1007 | high_memory = __va(arm_lowmem_limit - 1) + 1; |
1008 | memblock_set_current_limit(arm_lowmem_limit); | |
60296c71 LB |
1009 | } |
1010 | ||
4b5f32ce | 1011 | static inline void prepare_page_table(void) |
d111e8f9 RK |
1012 | { |
1013 | unsigned long addr; | |
8df65168 | 1014 | phys_addr_t end; |
d111e8f9 RK |
1015 | |
1016 | /* | |
1017 | * Clear out all the mappings below the kernel image. | |
1018 | */ | |
e73fc88e | 1019 | for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) |
d111e8f9 RK |
1020 | pmd_clear(pmd_off_k(addr)); |
1021 | ||
1022 | #ifdef CONFIG_XIP_KERNEL | |
1023 | /* The XIP kernel is mapped in the module area -- skip over it */ | |
e73fc88e | 1024 | addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; |
d111e8f9 | 1025 | #endif |
e73fc88e | 1026 | for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) |
d111e8f9 RK |
1027 | pmd_clear(pmd_off_k(addr)); |
1028 | ||
8df65168 RK |
1029 | /* |
1030 | * Find the end of the first block of lowmem. | |
1031 | */ | |
1032 | end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; | |
c7909509 MS |
1033 | if (end >= arm_lowmem_limit) |
1034 | end = arm_lowmem_limit; | |
8df65168 | 1035 | |
d111e8f9 RK |
1036 | /* |
1037 | * Clear out all the kernel space mappings, except for the first | |
0536bdf3 | 1038 | * memory bank, up to the vmalloc region. |
d111e8f9 | 1039 | */ |
8df65168 | 1040 | for (addr = __phys_to_virt(end); |
0536bdf3 | 1041 | addr < VMALLOC_START; addr += PMD_SIZE) |
d111e8f9 RK |
1042 | pmd_clear(pmd_off_k(addr)); |
1043 | } | |
1044 | ||
1b6ba46b CM |
1045 | #ifdef CONFIG_ARM_LPAE |
1046 | /* the first page is reserved for pgd */ | |
1047 | #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ | |
1048 | PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) | |
1049 | #else | |
e73fc88e | 1050 | #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) |
1b6ba46b | 1051 | #endif |
e73fc88e | 1052 | |
d111e8f9 | 1053 | /* |
2778f620 | 1054 | * Reserve the special regions of memory |
d111e8f9 | 1055 | */ |
2778f620 | 1056 | void __init arm_mm_memblock_reserve(void) |
d111e8f9 | 1057 | { |
d111e8f9 RK |
1058 | /* |
1059 | * Reserve the page tables. These are already in use, | |
1060 | * and can only be in node 0. | |
1061 | */ | |
e73fc88e | 1062 | memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); |
d111e8f9 | 1063 | |
d111e8f9 RK |
1064 | #ifdef CONFIG_SA1111 |
1065 | /* | |
1066 | * Because of the SA1111 DMA bug, we want to preserve our | |
1067 | * precious DMA-able memory... | |
1068 | */ | |
2778f620 | 1069 | memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
d111e8f9 | 1070 | #endif |
d111e8f9 RK |
1071 | } |
1072 | ||
1073 | /* | |
0536bdf3 NP |
1074 | * Set up the device mappings. Since we clear out the page tables for all |
1075 | * mappings above VMALLOC_START, we will remove any debug device mappings. | |
d111e8f9 RK |
1076 | * This means you have to be careful how you debug this function, or any |
1077 | * called function. This means you can't use any function or debugging | |
1078 | * method which may touch any device, otherwise the kernel _will_ crash. | |
1079 | */ | |
1080 | static void __init devicemaps_init(struct machine_desc *mdesc) | |
1081 | { | |
1082 | struct map_desc map; | |
1083 | unsigned long addr; | |
94e5a85b | 1084 | void *vectors; |
d111e8f9 RK |
1085 | |
1086 | /* | |
1087 | * Allocate the vector page early. | |
1088 | */ | |
94e5a85b RK |
1089 | vectors = early_alloc(PAGE_SIZE); |
1090 | ||
1091 | early_trap_init(vectors); | |
d111e8f9 | 1092 | |
0536bdf3 | 1093 | for (addr = VMALLOC_START; addr; addr += PMD_SIZE) |
d111e8f9 RK |
1094 | pmd_clear(pmd_off_k(addr)); |
1095 | ||
1096 | /* | |
1097 | * Map the kernel if it is XIP. | |
1098 | * It is always first in the modulearea. | |
1099 | */ | |
1100 | #ifdef CONFIG_XIP_KERNEL | |
1101 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); | |
ab4f2ee1 | 1102 | map.virtual = MODULES_VADDR; |
37efe642 | 1103 | map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
d111e8f9 RK |
1104 | map.type = MT_ROM; |
1105 | create_mapping(&map); | |
1106 | #endif | |
1107 | ||
1108 | /* | |
1109 | * Map the cache flushing regions. | |
1110 | */ | |
1111 | #ifdef FLUSH_BASE | |
1112 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); | |
1113 | map.virtual = FLUSH_BASE; | |
1114 | map.length = SZ_1M; | |
1115 | map.type = MT_CACHECLEAN; | |
1116 | create_mapping(&map); | |
1117 | #endif | |
1118 | #ifdef FLUSH_BASE_MINICACHE | |
1119 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); | |
1120 | map.virtual = FLUSH_BASE_MINICACHE; | |
1121 | map.length = SZ_1M; | |
1122 | map.type = MT_MINICLEAN; | |
1123 | create_mapping(&map); | |
1124 | #endif | |
1125 | ||
1126 | /* | |
1127 | * Create a mapping for the machine vectors at the high-vectors | |
1128 | * location (0xffff0000). If we aren't using high-vectors, also | |
1129 | * create a mapping at the low-vectors virtual address. | |
1130 | */ | |
94e5a85b | 1131 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); |
d111e8f9 RK |
1132 | map.virtual = 0xffff0000; |
1133 | map.length = PAGE_SIZE; | |
1134 | map.type = MT_HIGH_VECTORS; | |
1135 | create_mapping(&map); | |
1136 | ||
1137 | if (!vectors_high()) { | |
1138 | map.virtual = 0; | |
1139 | map.type = MT_LOW_VECTORS; | |
1140 | create_mapping(&map); | |
1141 | } | |
1142 | ||
1143 | /* | |
1144 | * Ask the machine support to map in the statically mapped devices. | |
1145 | */ | |
1146 | if (mdesc->map_io) | |
1147 | mdesc->map_io(); | |
19b52abe | 1148 | fill_pmd_gaps(); |
d111e8f9 RK |
1149 | |
1150 | /* | |
1151 | * Finally flush the caches and tlb to ensure that we're in a | |
1152 | * consistent state wrt the writebuffer. This also ensures that | |
1153 | * any write-allocated cache lines in the vector page are written | |
1154 | * back. After this point, we can start to touch devices again. | |
1155 | */ | |
1156 | local_flush_tlb_all(); | |
1157 | flush_cache_all(); | |
1158 | } | |
1159 | ||
d73cd428 NP |
1160 | static void __init kmap_init(void) |
1161 | { | |
1162 | #ifdef CONFIG_HIGHMEM | |
4bb2e27d RK |
1163 | pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), |
1164 | PKMAP_BASE, _PAGE_KERNEL_TABLE); | |
d73cd428 NP |
1165 | #endif |
1166 | } | |
1167 | ||
a2227120 RK |
1168 | static void __init map_lowmem(void) |
1169 | { | |
8df65168 | 1170 | struct memblock_region *reg; |
a2227120 RK |
1171 | |
1172 | /* Map all the lowmem memory banks. */ | |
8df65168 RK |
1173 | for_each_memblock(memory, reg) { |
1174 | phys_addr_t start = reg->base; | |
1175 | phys_addr_t end = start + reg->size; | |
1176 | struct map_desc map; | |
1177 | ||
c7909509 MS |
1178 | if (end > arm_lowmem_limit) |
1179 | end = arm_lowmem_limit; | |
8df65168 RK |
1180 | if (start >= end) |
1181 | break; | |
1182 | ||
1183 | map.pfn = __phys_to_pfn(start); | |
1184 | map.virtual = __phys_to_virt(start); | |
1185 | map.length = end - start; | |
1186 | map.type = MT_MEMORY; | |
a2227120 | 1187 | |
8df65168 | 1188 | create_mapping(&map); |
a2227120 RK |
1189 | } |
1190 | } | |
1191 | ||
d111e8f9 RK |
1192 | /* |
1193 | * paging_init() sets up the page tables, initialises the zone memory | |
1194 | * maps, and sets up the zero page, bad page and bad page tables. | |
1195 | */ | |
4b5f32ce | 1196 | void __init paging_init(struct machine_desc *mdesc) |
d111e8f9 RK |
1197 | { |
1198 | void *zero_page; | |
1199 | ||
c7909509 | 1200 | memblock_set_current_limit(arm_lowmem_limit); |
0371d3f7 | 1201 | |
d111e8f9 | 1202 | build_mem_type_table(); |
4b5f32ce | 1203 | prepare_page_table(); |
a2227120 | 1204 | map_lowmem(); |
c7909509 | 1205 | dma_contiguous_remap(); |
d111e8f9 | 1206 | devicemaps_init(mdesc); |
d73cd428 | 1207 | kmap_init(); |
d111e8f9 RK |
1208 | |
1209 | top_pmd = pmd_off_k(0xffff0000); | |
1210 | ||
3abe9d33 RK |
1211 | /* allocate the zero page. */ |
1212 | zero_page = early_alloc(PAGE_SIZE); | |
2778f620 | 1213 | |
8d717a52 | 1214 | bootmem_init(); |
2778f620 | 1215 | |
d111e8f9 | 1216 | empty_zero_page = virt_to_page(zero_page); |
421fe93c | 1217 | __flush_dcache_page(NULL, empty_zero_page); |
d111e8f9 | 1218 | } |