[linux-2.6-block.git] / arch / arm / mm / fault-armv.c

/*
 *  linux/arch/arm/mm/fault-armv.c
 *
 *  Copyright (C) 1995  Linus Torvalds
 *  Modifications for ARM processor (c) 1995-2002 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/bitops.h>
#include <linux/vmalloc.h>
#include <linux/init.h>
#include <linux/pagemap.h>

#include <asm/bugs.h>
#include <asm/cacheflush.h>
#include <asm/cachetype.h>
#include <asm/pgtable.h>
#include <asm/tlbflush.h>

#include "mm.h"

static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;

/*
 * We take the easy way out of this problem - we make the
 * PTE uncacheable.  However, we leave the write buffer on.
 *
 * Note that the pte lock held when calling update_mmu_cache must also
 * guard the pte (somewhere else in the same mm) that we modify here.
 * Therefore those configurations which might call adjust_pte (those
 * without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
 */
static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address,
	pte_t *ptep)
{
	pte_t entry = *ptep;
	int ret;

	/*
	 * If this page is present, it's actually being shared.
	 */
	ret = pte_present(entry);

	/*
	 * If this page isn't present, or is already setup to
	 * fault (ie, is old), we can safely ignore any issues.
	 */
	if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
		unsigned long pfn = pte_pfn(entry);
		flush_cache_page(vma, address, pfn);
		outer_flush_range((pfn << PAGE_SHIFT),
				  (pfn << PAGE_SHIFT) + PAGE_SIZE);
		pte_val(entry) &= ~L_PTE_MT_MASK;
		pte_val(entry) |= shared_pte_mask;
		set_pte_at(vma->vm_mm, address, ptep, entry);
		flush_tlb_page(vma, address);
	}

	return ret;
}

static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
{
	spinlock_t *ptl;
	pgd_t *pgd;
	pmd_t *pmd;
	pte_t *pte;
	int ret;

	pgd = pgd_offset(vma->vm_mm, address);
	if (pgd_none_or_clear_bad(pgd))
		return 0;

	pmd = pmd_offset(pgd, address);
	if (pmd_none_or_clear_bad(pmd))
		return 0;

	/*
	 * This is called while another page table is mapped, so we
	 * must use the nested version.  This also means we need to
	 * open-code the spin-locking.
	 */
	ptl = pte_lockptr(vma->vm_mm, pmd);
	pte = pte_offset_map_nested(pmd, address);
	spin_lock(ptl);

	ret = do_adjust_pte(vma, address, pte);

	spin_unlock(ptl);
	pte_unmap_nested(pte);

	return ret;
}

static void
make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
{
	struct mm_struct *mm = vma->vm_mm;
	struct vm_area_struct *mpnt;
	struct prio_tree_iter iter;
	unsigned long offset;
	pgoff_t pgoff;
	int aliases = 0;

	pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);

	/*
	 * If we have any shared mappings that are in the same mm
	 * space, then we need to handle them specially to maintain
	 * cache coherency.
	 */
	flush_dcache_mmap_lock(mapping);
	vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
		/*
		 * If this VMA is not in our MM, we can ignore it.
		 * Note that we intentionally mask out the VMA
		 * that we are fixing up.
		 */
		if (mpnt->vm_mm != mm || mpnt == vma)
			continue;
		if (!(mpnt->vm_flags & VM_MAYSHARE))
			continue;
		offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
		aliases += adjust_pte(mpnt, mpnt->vm_start + offset);
	}
	flush_dcache_mmap_unlock(mapping);
	if (aliases)
		adjust_pte(vma, addr);
	else
		flush_cache_page(vma, addr, pfn);
}

/*
 * Take care of architecture specific things when placing a new PTE into
 * a page table, or changing an existing PTE.  Basically, there are two
 * things that we need to take care of:
 *
 *  1. If PG_dcache_dirty is set for the page, we need to ensure
 *     that any cache entries for the kernels virtual memory
 *     range are written back to the page.
 *  2. If we have multiple shared mappings of the same space in
 *     an object, we need to deal with the cache aliasing issues.
 *
 * Note that the pte lock will be held.
 */
void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
{
	unsigned long pfn = pte_pfn(pte);
	struct address_space *mapping;
	struct page *page;

	if (!pfn_valid(pfn))
		return;

	/*
	 * The zero page is never written to, so never has any dirty
	 * cache lines, and therefore never needs to be flushed.
	 */
	page = pfn_to_page(pfn);
	if (page == ZERO_PAGE(0))
		return;

	mapping = page_mapping(page);
#ifndef CONFIG_SMP
	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
		__flush_dcache_page(mapping, page);
#endif
	if (mapping) {
		if (cache_is_vivt())
			make_coherent(mapping, vma, addr, pfn);
		else if (vma->vm_flags & VM_EXEC)
			__flush_icache_all();
	}
}

/*
 * Check whether the write buffer has physical address aliasing
 * issues.  If it has, we need to avoid them for the case where
 * we have several shared mappings of the same object in user
 * space.
 */
static int __init check_writebuffer(unsigned long *p1, unsigned long *p2)
{
	register unsigned long zero = 0, one = 1, val;

	local_irq_disable();
	mb();
	*p1 = one;
	mb();
	*p2 = zero;
	mb();
	val = *p1;
	mb();
	local_irq_enable();
	return val != zero;
}

void __init check_writebuffer_bugs(void)
{
	struct page *page;
	const char *reason;
	unsigned long v = 1;

	printk(KERN_INFO "CPU: Testing write buffer coherency: ");

	page = alloc_page(GFP_KERNEL);
	if (page) {
		unsigned long *p1, *p2;
		pgprot_t prot = __pgprot_modify(PAGE_KERNEL,
					L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE);

		p1 = vmap(&page, 1, VM_IOREMAP, prot);
		p2 = vmap(&page, 1, VM_IOREMAP, prot);

		if (p1 && p2) {
			v = check_writebuffer(p1, p2);
			reason = "enabling work-around";
		} else {
			reason = "unable to map memory\n";
		}

		vunmap(p1);
		vunmap(p2);
		put_page(page);
	} else {
		reason = "unable to grab page\n";
	}

	if (v) {
		printk("failed, %s\n", reason);
		shared_pte_mask = L_PTE_MT_UNCACHED;
	} else {
		printk("ok\n");
	}
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/fault-armv.c
	3	*
	4	* Copyright (C) 1995 Linus Torvalds
	5	* Modifications for ARM processor (c) 1995-2002 Russell King
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11	#include <linux/module.h>
	12	#include <linux/sched.h>
	13	#include <linux/kernel.h>
	14	#include <linux/mm.h>
	15	#include <linux/bitops.h>
	16	#include <linux/vmalloc.h>
	17	#include <linux/init.h>
	18	#include <linux/pagemap.h>
	19
09d9bae0	20	#include <asm/bugs.h>
1da177e4	21	#include <asm/cacheflush.h>
46097c7d	22	#include <asm/cachetype.h>
1da177e4 LT	23	#include <asm/pgtable.h>
	24	#include <asm/tlbflush.h>
	25
7b0a1003 RK	26	#include "mm.h"
7b0a1003 RK	27
bb30f36f	28	static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
1da177e4 LT	29
	30	/*
	31	* We take the easy way out of this problem - we make the
	32	* PTE uncacheable. However, we leave the write buffer on.
69b04754 HD	33	*
	34	* Note that the pte lock held when calling update_mmu_cache must also
	35	* guard the pte (somewhere else in the same mm) that we modify here.
	36	* Therefore those configurations which might call adjust_pte (those
	37	* without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
1da177e4	38	*/
c26c20b8 RK	39	static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address,
c26c20b8 RK	40	pte_t *ptep)
1da177e4	41	{
c26c20b8	42	pte_t entry = *ptep;
53cdb27a	43	int ret;
1da177e4	44
53cdb27a RK	45	/*
	46	* If this page is present, it's actually being shared.
	47	*/
	48	ret = pte_present(entry);
	49
1da177e4 LT	50	/*
	51	* If this page isn't present, or is already setup to
	52	* fault (ie, is old), we can safely ignore any issues.
	53	*/
bb30f36f	54	if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
08e445bd NP	55	unsigned long pfn = pte_pfn(entry);
	56	flush_cache_page(vma, address, pfn);
	57	outer_flush_range((pfn << PAGE_SHIFT),
	58	(pfn << PAGE_SHIFT) + PAGE_SIZE);
bb30f36f RK	59	pte_val(entry) &= ~L_PTE_MT_MASK;
bb30f36f RK	60	pte_val(entry) \|= shared_pte_mask;
c26c20b8	61	set_pte_at(vma->vm_mm, address, ptep, entry);
1da177e4	62	flush_tlb_page(vma, address);
1da177e4	63	}
c26c20b8 RK	64
	65	return ret;
	66	}
	67
	68	static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
	69	{
56dd4709	70	spinlock_t *ptl;
c26c20b8 RK	71	pgd_t *pgd;
	72	pmd_t *pmd;
	73	pte_t *pte;
	74	int ret;
	75
	76	pgd = pgd_offset(vma->vm_mm, address);
f8a85f11 RK	77	if (pgd_none_or_clear_bad(pgd))
f8a85f11 RK	78	return 0;
c26c20b8 RK	79
c26c20b8 RK	80	pmd = pmd_offset(pgd, address);
f8a85f11 RK	81	if (pmd_none_or_clear_bad(pmd))
f8a85f11 RK	82	return 0;
c26c20b8	83
56dd4709 RK	84	/*
	85	* This is called while another page table is mapped, so we
	86	* must use the nested version. This also means we need to
	87	* open-code the spin-locking.
	88	*/
	89	ptl = pte_lockptr(vma->vm_mm, pmd);
	90	pte = pte_offset_map_nested(pmd, address);
	91	spin_lock(ptl);
c26c20b8 RK	92
	93	ret = do_adjust_pte(vma, address, pte);
	94
56dd4709 RK	95	spin_unlock(ptl);
56dd4709 RK	96	pte_unmap_nested(pte);
c26c20b8	97
1da177e4	98	return ret;
1da177e4 LT	99	}
	100
	101	static void
8830f04a	102	make_coherent(struct address_space mapping, struct vm_area_struct vma, unsigned long addr, unsigned long pfn)
1da177e4	103	{
1da177e4 LT	104	struct mm_struct *mm = vma->vm_mm;
	105	struct vm_area_struct *mpnt;
	106	struct prio_tree_iter iter;
	107	unsigned long offset;
	108	pgoff_t pgoff;
	109	int aliases = 0;
	110
1da177e4 LT	111	pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);
	112
	113	/*
	114	* If we have any shared mappings that are in the same mm
	115	* space, then we need to handle them specially to maintain
	116	* cache coherency.
	117	*/
	118	flush_dcache_mmap_lock(mapping);
	119	vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
	120	/*
	121	* If this VMA is not in our MM, we can ignore it.
	122	* Note that we intentionally mask out the VMA
	123	* that we are fixing up.
	124	*/
	125	if (mpnt->vm_mm != mm \|\| mpnt == vma)
	126	continue;
	127	if (!(mpnt->vm_flags & VM_MAYSHARE))
	128	continue;
	129	offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
	130	aliases += adjust_pte(mpnt, mpnt->vm_start + offset);
	131	}
	132	flush_dcache_mmap_unlock(mapping);
	133	if (aliases)
	134	adjust_pte(vma, addr);
	135	else
8830f04a	136	flush_cache_page(vma, addr, pfn);
1da177e4 LT	137	}
	138
	139	/*
	140	* Take care of architecture specific things when placing a new PTE into
	141	* a page table, or changing an existing PTE. Basically, there are two
	142	* things that we need to take care of:
	143	*
	144	* 1. If PG_dcache_dirty is set for the page, we need to ensure
	145	* that any cache entries for the kernels virtual memory
	146	* range are written back to the page.
	147	* 2. If we have multiple shared mappings of the same space in
	148	* an object, we need to deal with the cache aliasing issues.
	149	*
69b04754	150	* Note that the pte lock will be held.
1da177e4 LT	151	*/
	152	void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
	153	{
	154	unsigned long pfn = pte_pfn(pte);
8830f04a	155	struct address_space *mapping;
1da177e4 LT	156	struct page *page;
	157
	158	if (!pfn_valid(pfn))
	159	return;
8830f04a	160
421fe93c RK	161	/*
	162	* The zero page is never written to, so never has any dirty
	163	* cache lines, and therefore never needs to be flushed.
	164	*/
1da177e4	165	page = pfn_to_page(pfn);
421fe93c RK	166	if (page == ZERO_PAGE(0))
	167	return;
	168
8830f04a	169	mapping = page_mapping(page);
826cbdaf	170	#ifndef CONFIG_SMP
787b2faa NG	171	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
787b2faa NG	172	__flush_dcache_page(mapping, page);
826cbdaf	173	#endif
787b2faa	174	if (mapping) {
1da177e4	175	if (cache_is_vivt())
8830f04a	176	make_coherent(mapping, vma, addr, pfn);
826cbdaf CM	177	else if (vma->vm_flags & VM_EXEC)
826cbdaf CM	178	__flush_icache_all();
1da177e4 LT	179	}
	180	}
	181
	182	/*
	183	* Check whether the write buffer has physical address aliasing
	184	* issues. If it has, we need to avoid them for the case where
	185	* we have several shared mappings of the same object in user
	186	* space.
	187	*/
	188	static int __init check_writebuffer(unsigned long p1, unsigned long p2)
	189	{
	190	register unsigned long zero = 0, one = 1, val;
	191
	192	local_irq_disable();
	193	mb();
	194	*p1 = one;
	195	mb();
	196	*p2 = zero;
	197	mb();
	198	val = *p1;
	199	mb();
	200	local_irq_enable();
	201	return val != zero;
	202	}
	203
	204	void __init check_writebuffer_bugs(void)
	205	{
	206	struct page *page;
	207	const char *reason;
	208	unsigned long v = 1;
	209
	210	printk(KERN_INFO "CPU: Testing write buffer coherency: ");
	211
	212	page = alloc_page(GFP_KERNEL);
	213	if (page) {
	214	unsigned long p1, p2;
52e8bfd8 RK	215	pgprot_t prot = __pgprot_modify(PAGE_KERNEL,
52e8bfd8 RK	216	L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE);
1da177e4 LT	217
	218	p1 = vmap(&page, 1, VM_IOREMAP, prot);
	219	p2 = vmap(&page, 1, VM_IOREMAP, prot);
	220
	221	if (p1 && p2) {
	222	v = check_writebuffer(p1, p2);
	223	reason = "enabling work-around";
	224	} else {
	225	reason = "unable to map memory\n";
	226	}
	227
	228	vunmap(p1);
	229	vunmap(p2);
	230	put_page(page);
	231	} else {
	232	reason = "unable to grab page\n";
	233	}
	234
	235	if (v) {
	236	printk("failed, %s\n", reason);
bb30f36f	237	shared_pte_mask = L_PTE_MT_UNCACHED;
1da177e4 LT	238	} else {
	239	printk("ok\n");
	240	}
	241	}