Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | comment "Processor Type" |
2 | ||
1da177e4 LT |
3 | # Select CPU types depending on the architecture selected. This selects |
4 | # which CPUs we support in the kernel image, and the compiler instruction | |
5 | # optimiser behaviour. | |
6 | ||
07e0da78 HC |
7 | # ARM7TDMI |
8 | config CPU_ARM7TDMI | |
9 | bool "Support ARM7TDMI processor" | |
6b237a35 | 10 | depends on !MMU |
07e0da78 HC |
11 | select CPU_32v4T |
12 | select CPU_ABRT_LV4T | |
13 | select CPU_CACHE_V4 | |
b1b3f49c | 14 | select CPU_PABRT_LEGACY |
07e0da78 HC |
15 | help |
16 | A 32-bit RISC microprocessor based on the ARM7 processor core | |
17 | which has no memory control unit and cache. | |
18 | ||
19 | Say Y if you want support for the ARM7TDMI processor. | |
20 | Otherwise, say N. | |
21 | ||
1da177e4 LT |
22 | # ARM720T |
23 | config CPU_ARM720T | |
c750815e | 24 | bool "Support ARM720T processor" if ARCH_INTEGRATOR |
260e98ed | 25 | select CPU_32v4T |
1da177e4 LT |
26 | select CPU_ABRT_LV4T |
27 | select CPU_CACHE_V4 | |
28 | select CPU_CACHE_VIVT | |
f9c21a6e | 29 | select CPU_COPY_V4WT if MMU |
b1b3f49c RK |
30 | select CPU_CP15_MMU |
31 | select CPU_PABRT_LEGACY | |
f9c21a6e | 32 | select CPU_TLB_V4WT if MMU |
1da177e4 LT |
33 | help |
34 | A 32-bit RISC processor with 8kByte Cache, Write Buffer and | |
35 | MMU built around an ARM7TDMI core. | |
36 | ||
37 | Say Y if you want support for the ARM720T processor. | |
38 | Otherwise, say N. | |
39 | ||
b731c311 HC |
40 | # ARM740T |
41 | config CPU_ARM740T | |
42 | bool "Support ARM740T processor" if ARCH_INTEGRATOR | |
6b237a35 | 43 | depends on !MMU |
b731c311 HC |
44 | select CPU_32v4T |
45 | select CPU_ABRT_LV4T | |
82d9b0d0 | 46 | select CPU_CACHE_V4 |
b731c311 | 47 | select CPU_CP15_MPU |
b1b3f49c | 48 | select CPU_PABRT_LEGACY |
b731c311 HC |
49 | help |
50 | A 32-bit RISC processor with 8KB cache or 4KB variants, | |
51 | write buffer and MPU(Protection Unit) built around | |
52 | an ARM7TDMI core. | |
53 | ||
54 | Say Y if you want support for the ARM740T processor. | |
55 | Otherwise, say N. | |
56 | ||
43f5f014 HC |
57 | # ARM9TDMI |
58 | config CPU_ARM9TDMI | |
59 | bool "Support ARM9TDMI processor" | |
6b237a35 | 60 | depends on !MMU |
43f5f014 | 61 | select CPU_32v4T |
0f45d7f3 | 62 | select CPU_ABRT_NOMMU |
43f5f014 | 63 | select CPU_CACHE_V4 |
b1b3f49c | 64 | select CPU_PABRT_LEGACY |
43f5f014 HC |
65 | help |
66 | A 32-bit RISC microprocessor based on the ARM9 processor core | |
67 | which has no memory control unit and cache. | |
68 | ||
69 | Say Y if you want support for the ARM9TDMI processor. | |
70 | Otherwise, say N. | |
71 | ||
1da177e4 LT |
72 | # ARM920T |
73 | config CPU_ARM920T | |
c750815e | 74 | bool "Support ARM920T processor" if ARCH_INTEGRATOR |
260e98ed | 75 | select CPU_32v4T |
1da177e4 LT |
76 | select CPU_ABRT_EV4T |
77 | select CPU_CACHE_V4WT | |
78 | select CPU_CACHE_VIVT | |
f9c21a6e | 79 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
80 | select CPU_CP15_MMU |
81 | select CPU_PABRT_LEGACY | |
f9c21a6e | 82 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
83 | help |
84 | The ARM920T is licensed to be produced by numerous vendors, | |
c768e676 | 85 | and is used in the Cirrus EP93xx and the Samsung S3C2410. |
1da177e4 LT |
86 | |
87 | Say Y if you want support for the ARM920T processor. | |
88 | Otherwise, say N. | |
89 | ||
90 | # ARM922T | |
91 | config CPU_ARM922T | |
92 | bool "Support ARM922T processor" if ARCH_INTEGRATOR | |
260e98ed | 93 | select CPU_32v4T |
1da177e4 LT |
94 | select CPU_ABRT_EV4T |
95 | select CPU_CACHE_V4WT | |
96 | select CPU_CACHE_VIVT | |
f9c21a6e | 97 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
98 | select CPU_CP15_MMU |
99 | select CPU_PABRT_LEGACY | |
f9c21a6e | 100 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
101 | help |
102 | The ARM922T is a version of the ARM920T, but with smaller | |
103 | instruction and data caches. It is used in Altera's | |
c53c9cf6 | 104 | Excalibur XA device family and Micrel's KS8695 Centaur. |
1da177e4 LT |
105 | |
106 | Say Y if you want support for the ARM922T processor. | |
107 | Otherwise, say N. | |
108 | ||
109 | # ARM925T | |
110 | config CPU_ARM925T | |
b288f75f | 111 | bool "Support ARM925T processor" if ARCH_OMAP1 |
260e98ed | 112 | select CPU_32v4T |
1da177e4 LT |
113 | select CPU_ABRT_EV4T |
114 | select CPU_CACHE_V4WT | |
115 | select CPU_CACHE_VIVT | |
f9c21a6e | 116 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
117 | select CPU_CP15_MMU |
118 | select CPU_PABRT_LEGACY | |
f9c21a6e | 119 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
120 | help |
121 | The ARM925T is a mix between the ARM920T and ARM926T, but with | |
122 | different instruction and data caches. It is used in TI's OMAP | |
123 | device family. | |
124 | ||
125 | Say Y if you want support for the ARM925T processor. | |
126 | Otherwise, say N. | |
127 | ||
128 | # ARM926T | |
129 | config CPU_ARM926T | |
c750815e | 130 | bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB |
1da177e4 LT |
131 | select CPU_32v5 |
132 | select CPU_ABRT_EV5TJ | |
133 | select CPU_CACHE_VIVT | |
f9c21a6e | 134 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
135 | select CPU_CP15_MMU |
136 | select CPU_PABRT_LEGACY | |
f9c21a6e | 137 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
138 | help |
139 | This is a variant of the ARM920. It has slightly different | |
140 | instruction sequences for cache and TLB operations. Curiously, | |
141 | there is no documentation on it at the ARM corporate website. | |
142 | ||
143 | Say Y if you want support for the ARM926T processor. | |
144 | Otherwise, say N. | |
145 | ||
28853ac8 PZ |
146 | # FA526 |
147 | config CPU_FA526 | |
148 | bool | |
149 | select CPU_32v4 | |
150 | select CPU_ABRT_EV4 | |
28853ac8 | 151 | select CPU_CACHE_FA |
b1b3f49c | 152 | select CPU_CACHE_VIVT |
28853ac8 | 153 | select CPU_COPY_FA if MMU |
b1b3f49c RK |
154 | select CPU_CP15_MMU |
155 | select CPU_PABRT_LEGACY | |
28853ac8 PZ |
156 | select CPU_TLB_FA if MMU |
157 | help | |
158 | The FA526 is a version of the ARMv4 compatible processor with | |
159 | Branch Target Buffer, Unified TLB and cache line size 16. | |
160 | ||
161 | Say Y if you want support for the FA526 processor. | |
162 | Otherwise, say N. | |
163 | ||
d60674eb HC |
164 | # ARM940T |
165 | config CPU_ARM940T | |
166 | bool "Support ARM940T processor" if ARCH_INTEGRATOR | |
6b237a35 | 167 | depends on !MMU |
d60674eb | 168 | select CPU_32v4T |
0f45d7f3 | 169 | select CPU_ABRT_NOMMU |
d60674eb HC |
170 | select CPU_CACHE_VIVT |
171 | select CPU_CP15_MPU | |
b1b3f49c | 172 | select CPU_PABRT_LEGACY |
d60674eb HC |
173 | help |
174 | ARM940T is a member of the ARM9TDMI family of general- | |
3cb2fccc | 175 | purpose microprocessors with MPU and separate 4KB |
d60674eb HC |
176 | instruction and 4KB data cases, each with a 4-word line |
177 | length. | |
178 | ||
179 | Say Y if you want support for the ARM940T processor. | |
180 | Otherwise, say N. | |
181 | ||
f37f46eb HC |
182 | # ARM946E-S |
183 | config CPU_ARM946E | |
184 | bool "Support ARM946E-S processor" if ARCH_INTEGRATOR | |
6b237a35 | 185 | depends on !MMU |
f37f46eb | 186 | select CPU_32v5 |
0f45d7f3 | 187 | select CPU_ABRT_NOMMU |
f37f46eb HC |
188 | select CPU_CACHE_VIVT |
189 | select CPU_CP15_MPU | |
b1b3f49c | 190 | select CPU_PABRT_LEGACY |
f37f46eb HC |
191 | help |
192 | ARM946E-S is a member of the ARM9E-S family of high- | |
193 | performance, 32-bit system-on-chip processor solutions. | |
194 | The TCM and ARMv5TE 32-bit instruction set is supported. | |
195 | ||
196 | Say Y if you want support for the ARM946E-S processor. | |
197 | Otherwise, say N. | |
198 | ||
1da177e4 LT |
199 | # ARM1020 - needs validating |
200 | config CPU_ARM1020 | |
c750815e | 201 | bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR |
1da177e4 LT |
202 | select CPU_32v5 |
203 | select CPU_ABRT_EV4T | |
204 | select CPU_CACHE_V4WT | |
205 | select CPU_CACHE_VIVT | |
f9c21a6e | 206 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
207 | select CPU_CP15_MMU |
208 | select CPU_PABRT_LEGACY | |
f9c21a6e | 209 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
210 | help |
211 | The ARM1020 is the 32K cached version of the ARM10 processor, | |
212 | with an addition of a floating-point unit. | |
213 | ||
214 | Say Y if you want support for the ARM1020 processor. | |
215 | Otherwise, say N. | |
216 | ||
217 | # ARM1020E - needs validating | |
218 | config CPU_ARM1020E | |
c750815e | 219 | bool "Support ARM1020E processor" if ARCH_INTEGRATOR |
b1b3f49c | 220 | depends on n |
1da177e4 LT |
221 | select CPU_32v5 |
222 | select CPU_ABRT_EV4T | |
223 | select CPU_CACHE_V4WT | |
224 | select CPU_CACHE_VIVT | |
f9c21a6e | 225 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
226 | select CPU_CP15_MMU |
227 | select CPU_PABRT_LEGACY | |
f9c21a6e | 228 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
229 | |
230 | # ARM1022E | |
231 | config CPU_ARM1022 | |
c750815e | 232 | bool "Support ARM1022E processor" if ARCH_INTEGRATOR |
1da177e4 LT |
233 | select CPU_32v5 |
234 | select CPU_ABRT_EV4T | |
235 | select CPU_CACHE_VIVT | |
f9c21a6e | 236 | select CPU_COPY_V4WB if MMU # can probably do better |
b1b3f49c RK |
237 | select CPU_CP15_MMU |
238 | select CPU_PABRT_LEGACY | |
f9c21a6e | 239 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
240 | help |
241 | The ARM1022E is an implementation of the ARMv5TE architecture | |
242 | based upon the ARM10 integer core with a 16KiB L1 Harvard cache, | |
243 | embedded trace macrocell, and a floating-point unit. | |
244 | ||
245 | Say Y if you want support for the ARM1022E processor. | |
246 | Otherwise, say N. | |
247 | ||
248 | # ARM1026EJ-S | |
249 | config CPU_ARM1026 | |
c750815e | 250 | bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR |
1da177e4 LT |
251 | select CPU_32v5 |
252 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 | |
253 | select CPU_CACHE_VIVT | |
f9c21a6e | 254 | select CPU_COPY_V4WB if MMU # can probably do better |
b1b3f49c RK |
255 | select CPU_CP15_MMU |
256 | select CPU_PABRT_LEGACY | |
f9c21a6e | 257 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
258 | help |
259 | The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture | |
260 | based upon the ARM10 integer core. | |
261 | ||
262 | Say Y if you want support for the ARM1026EJ-S processor. | |
263 | Otherwise, say N. | |
264 | ||
265 | # SA110 | |
266 | config CPU_SA110 | |
fa04e209 | 267 | bool |
1da177e4 LT |
268 | select CPU_32v3 if ARCH_RPC |
269 | select CPU_32v4 if !ARCH_RPC | |
270 | select CPU_ABRT_EV4 | |
271 | select CPU_CACHE_V4WB | |
272 | select CPU_CACHE_VIVT | |
f9c21a6e | 273 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
274 | select CPU_CP15_MMU |
275 | select CPU_PABRT_LEGACY | |
f9c21a6e | 276 | select CPU_TLB_V4WB if MMU |
1da177e4 LT |
277 | help |
278 | The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and | |
279 | is available at five speeds ranging from 100 MHz to 233 MHz. | |
280 | More information is available at | |
281 | <http://developer.intel.com/design/strong/sa110.htm>. | |
282 | ||
283 | Say Y if you want support for the SA-110 processor. | |
284 | Otherwise, say N. | |
285 | ||
286 | # SA1100 | |
287 | config CPU_SA1100 | |
288 | bool | |
1da177e4 LT |
289 | select CPU_32v4 |
290 | select CPU_ABRT_EV4 | |
291 | select CPU_CACHE_V4WB | |
292 | select CPU_CACHE_VIVT | |
fefdaa06 | 293 | select CPU_CP15_MMU |
b1b3f49c | 294 | select CPU_PABRT_LEGACY |
f9c21a6e | 295 | select CPU_TLB_V4WB if MMU |
1da177e4 LT |
296 | |
297 | # XScale | |
298 | config CPU_XSCALE | |
299 | bool | |
1da177e4 LT |
300 | select CPU_32v5 |
301 | select CPU_ABRT_EV5T | |
302 | select CPU_CACHE_VIVT | |
fefdaa06 | 303 | select CPU_CP15_MMU |
b1b3f49c | 304 | select CPU_PABRT_LEGACY |
f9c21a6e | 305 | select CPU_TLB_V4WBI if MMU |
1da177e4 | 306 | |
23bdf86a LB |
307 | # XScale Core Version 3 |
308 | config CPU_XSC3 | |
309 | bool | |
23bdf86a LB |
310 | select CPU_32v5 |
311 | select CPU_ABRT_EV5T | |
312 | select CPU_CACHE_VIVT | |
fefdaa06 | 313 | select CPU_CP15_MMU |
b1b3f49c | 314 | select CPU_PABRT_LEGACY |
f9c21a6e | 315 | select CPU_TLB_V4WBI if MMU |
23bdf86a LB |
316 | select IO_36 |
317 | ||
49cbe786 EM |
318 | # Marvell PJ1 (Mohawk) |
319 | config CPU_MOHAWK | |
320 | bool | |
321 | select CPU_32v5 | |
322 | select CPU_ABRT_EV5T | |
49cbe786 | 323 | select CPU_CACHE_VIVT |
b1b3f49c | 324 | select CPU_COPY_V4WB if MMU |
49cbe786 | 325 | select CPU_CP15_MMU |
b1b3f49c | 326 | select CPU_PABRT_LEGACY |
49cbe786 | 327 | select CPU_TLB_V4WBI if MMU |
49cbe786 | 328 | |
e50d6409 AH |
329 | # Feroceon |
330 | config CPU_FEROCEON | |
331 | bool | |
e50d6409 AH |
332 | select CPU_32v5 |
333 | select CPU_ABRT_EV5T | |
334 | select CPU_CACHE_VIVT | |
0ed15071 | 335 | select CPU_COPY_FEROCEON if MMU |
b1b3f49c RK |
336 | select CPU_CP15_MMU |
337 | select CPU_PABRT_LEGACY | |
99c6dc11 | 338 | select CPU_TLB_FEROCEON if MMU |
e50d6409 | 339 | |
d910a0aa TP |
340 | config CPU_FEROCEON_OLD_ID |
341 | bool "Accept early Feroceon cores with an ARM926 ID" | |
342 | depends on CPU_FEROCEON && !CPU_ARM926T | |
343 | default y | |
344 | help | |
345 | This enables the usage of some old Feroceon cores | |
346 | for which the CPU ID is equal to the ARM926 ID. | |
347 | Relevant for Feroceon-1850 and early Feroceon-2850. | |
348 | ||
a4553358 HZ |
349 | # Marvell PJ4 |
350 | config CPU_PJ4 | |
351 | bool | |
a4553358 | 352 | select ARM_THUMBEE |
b1b3f49c | 353 | select CPU_V7 |
a4553358 | 354 | |
de490193 GC |
355 | config CPU_PJ4B |
356 | bool | |
357 | select CPU_V7 | |
358 | ||
1da177e4 LT |
359 | # ARMv6 |
360 | config CPU_V6 | |
c786282e | 361 | bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
1da177e4 LT |
362 | select CPU_32v6 |
363 | select CPU_ABRT_EV6 | |
364 | select CPU_CACHE_V6 | |
365 | select CPU_CACHE_VIPT | |
b1b3f49c | 366 | select CPU_COPY_V6 if MMU |
fefdaa06 | 367 | select CPU_CP15_MMU |
7b4c965a | 368 | select CPU_HAS_ASID if MMU |
b1b3f49c | 369 | select CPU_PABRT_V6 |
f9c21a6e | 370 | select CPU_TLB_V6 if MMU |
1da177e4 | 371 | |
4a5f79e7 | 372 | # ARMv6k |
e399b1a4 | 373 | config CPU_V6K |
c786282e | 374 | bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
e399b1a4 | 375 | select CPU_32v6 |
60799c6d | 376 | select CPU_32v6K |
e399b1a4 | 377 | select CPU_ABRT_EV6 |
e399b1a4 RK |
378 | select CPU_CACHE_V6 |
379 | select CPU_CACHE_VIPT | |
b1b3f49c | 380 | select CPU_COPY_V6 if MMU |
e399b1a4 RK |
381 | select CPU_CP15_MMU |
382 | select CPU_HAS_ASID if MMU | |
b1b3f49c | 383 | select CPU_PABRT_V6 |
e399b1a4 | 384 | select CPU_TLB_V6 if MMU |
4a5f79e7 | 385 | |
23688e99 CM |
386 | # ARMv7 |
387 | config CPU_V7 | |
1b504bbe | 388 | bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
15490ef8 | 389 | select CPU_32v6K |
23688e99 CM |
390 | select CPU_32v7 |
391 | select CPU_ABRT_EV7 | |
392 | select CPU_CACHE_V7 | |
393 | select CPU_CACHE_VIPT | |
b1b3f49c | 394 | select CPU_COPY_V6 if MMU |
66567618 JA |
395 | select CPU_CP15_MMU if MMU |
396 | select CPU_CP15_MPU if !MMU | |
2eb8c82b | 397 | select CPU_HAS_ASID if MMU |
b1b3f49c | 398 | select CPU_PABRT_V7 |
2ccdd1e7 | 399 | select CPU_TLB_V7 if MMU |
23688e99 | 400 | |
4477ca45 UKK |
401 | # ARMv7M |
402 | config CPU_V7M | |
403 | bool | |
404 | select CPU_32v7M | |
405 | select CPU_ABRT_NOMMU | |
406 | select CPU_CACHE_NOP | |
407 | select CPU_PABRT_LEGACY | |
408 | select CPU_THUMBONLY | |
409 | ||
bc7dea00 UKK |
410 | config CPU_THUMBONLY |
411 | bool | |
412 | # There are no CPUs available with MMU that don't implement an ARM ISA: | |
413 | depends on !MMU | |
414 | help | |
415 | Select this if your CPU doesn't support the 32 bit ARM instructions. | |
416 | ||
1da177e4 LT |
417 | # Figure out what processor architecture version we should be using. |
418 | # This defines the compiler instruction set which depends on the machine type. | |
419 | config CPU_32v3 | |
420 | bool | |
8762df4d | 421 | select CPU_USE_DOMAINS if MMU |
b1b3f49c | 422 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
f6f91b0d | 423 | select NEED_KUSER_HELPERS |
51aaf81f | 424 | select TLS_REG_EMUL if SMP || !MMU |
1da177e4 LT |
425 | |
426 | config CPU_32v4 | |
427 | bool | |
8762df4d | 428 | select CPU_USE_DOMAINS if MMU |
b1b3f49c | 429 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
f6f91b0d | 430 | select NEED_KUSER_HELPERS |
51aaf81f | 431 | select TLS_REG_EMUL if SMP || !MMU |
1da177e4 | 432 | |
260e98ed LB |
433 | config CPU_32v4T |
434 | bool | |
8762df4d | 435 | select CPU_USE_DOMAINS if MMU |
b1b3f49c | 436 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
f6f91b0d | 437 | select NEED_KUSER_HELPERS |
51aaf81f | 438 | select TLS_REG_EMUL if SMP || !MMU |
260e98ed | 439 | |
1da177e4 LT |
440 | config CPU_32v5 |
441 | bool | |
8762df4d | 442 | select CPU_USE_DOMAINS if MMU |
b1b3f49c | 443 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
f6f91b0d | 444 | select NEED_KUSER_HELPERS |
51aaf81f | 445 | select TLS_REG_EMUL if SMP || !MMU |
1da177e4 LT |
446 | |
447 | config CPU_32v6 | |
448 | bool | |
b1b3f49c | 449 | select TLS_REG_EMUL if !CPU_32v6K && !MMU |
1da177e4 | 450 | |
e399b1a4 | 451 | config CPU_32v6K |
60799c6d | 452 | bool |
1da177e4 | 453 | |
23688e99 CM |
454 | config CPU_32v7 |
455 | bool | |
456 | ||
4477ca45 UKK |
457 | config CPU_32v7M |
458 | bool | |
459 | ||
1da177e4 | 460 | # The abort model |
0f45d7f3 HC |
461 | config CPU_ABRT_NOMMU |
462 | bool | |
463 | ||
1da177e4 LT |
464 | config CPU_ABRT_EV4 |
465 | bool | |
466 | ||
467 | config CPU_ABRT_EV4T | |
468 | bool | |
469 | ||
470 | config CPU_ABRT_LV4T | |
471 | bool | |
472 | ||
473 | config CPU_ABRT_EV5T | |
474 | bool | |
475 | ||
476 | config CPU_ABRT_EV5TJ | |
477 | bool | |
478 | ||
479 | config CPU_ABRT_EV6 | |
480 | bool | |
481 | ||
23688e99 CM |
482 | config CPU_ABRT_EV7 |
483 | bool | |
484 | ||
4fb28474 | 485 | config CPU_PABRT_LEGACY |
48d7927b PB |
486 | bool |
487 | ||
4fb28474 KS |
488 | config CPU_PABRT_V6 |
489 | bool | |
490 | ||
491 | config CPU_PABRT_V7 | |
48d7927b PB |
492 | bool |
493 | ||
1da177e4 | 494 | # The cache model |
1da177e4 LT |
495 | config CPU_CACHE_V4 |
496 | bool | |
497 | ||
498 | config CPU_CACHE_V4WT | |
499 | bool | |
500 | ||
501 | config CPU_CACHE_V4WB | |
502 | bool | |
503 | ||
504 | config CPU_CACHE_V6 | |
505 | bool | |
506 | ||
23688e99 CM |
507 | config CPU_CACHE_V7 |
508 | bool | |
509 | ||
4477ca45 UKK |
510 | config CPU_CACHE_NOP |
511 | bool | |
512 | ||
1da177e4 LT |
513 | config CPU_CACHE_VIVT |
514 | bool | |
515 | ||
516 | config CPU_CACHE_VIPT | |
517 | bool | |
518 | ||
28853ac8 PZ |
519 | config CPU_CACHE_FA |
520 | bool | |
521 | ||
f9c21a6e | 522 | if MMU |
1da177e4 | 523 | # The copy-page model |
1da177e4 LT |
524 | config CPU_COPY_V4WT |
525 | bool | |
526 | ||
527 | config CPU_COPY_V4WB | |
528 | bool | |
529 | ||
0ed15071 LB |
530 | config CPU_COPY_FEROCEON |
531 | bool | |
532 | ||
28853ac8 PZ |
533 | config CPU_COPY_FA |
534 | bool | |
535 | ||
1da177e4 LT |
536 | config CPU_COPY_V6 |
537 | bool | |
538 | ||
539 | # This selects the TLB model | |
1da177e4 LT |
540 | config CPU_TLB_V4WT |
541 | bool | |
542 | help | |
543 | ARM Architecture Version 4 TLB with writethrough cache. | |
544 | ||
545 | config CPU_TLB_V4WB | |
546 | bool | |
547 | help | |
548 | ARM Architecture Version 4 TLB with writeback cache. | |
549 | ||
550 | config CPU_TLB_V4WBI | |
551 | bool | |
552 | help | |
553 | ARM Architecture Version 4 TLB with writeback cache and invalidate | |
554 | instruction cache entry. | |
555 | ||
99c6dc11 LB |
556 | config CPU_TLB_FEROCEON |
557 | bool | |
558 | help | |
559 | Feroceon TLB (v4wbi with non-outer-cachable page table walks). | |
560 | ||
28853ac8 PZ |
561 | config CPU_TLB_FA |
562 | bool | |
563 | help | |
564 | Faraday ARM FA526 architecture, unified TLB with writeback cache | |
565 | and invalidate instruction cache entry. Branch target buffer is | |
566 | also supported. | |
567 | ||
1da177e4 LT |
568 | config CPU_TLB_V6 |
569 | bool | |
570 | ||
2ccdd1e7 CM |
571 | config CPU_TLB_V7 |
572 | bool | |
573 | ||
e220ba60 DE |
574 | config VERIFY_PERMISSION_FAULT |
575 | bool | |
f9c21a6e HC |
576 | endif |
577 | ||
516793c6 RK |
578 | config CPU_HAS_ASID |
579 | bool | |
580 | help | |
581 | This indicates whether the CPU has the ASID register; used to | |
582 | tag TLB and possibly cache entries. | |
583 | ||
fefdaa06 HC |
584 | config CPU_CP15 |
585 | bool | |
586 | help | |
587 | Processor has the CP15 register. | |
588 | ||
589 | config CPU_CP15_MMU | |
590 | bool | |
591 | select CPU_CP15 | |
592 | help | |
593 | Processor has the CP15 register, which has MMU related registers. | |
594 | ||
595 | config CPU_CP15_MPU | |
596 | bool | |
597 | select CPU_CP15 | |
598 | help | |
599 | Processor has the CP15 register, which has MPU related registers. | |
600 | ||
247055aa CM |
601 | config CPU_USE_DOMAINS |
602 | bool | |
247055aa CM |
603 | help |
604 | This option enables or disables the use of domain switching | |
605 | via the set_fs() function. | |
606 | ||
23bdf86a LB |
607 | # |
608 | # CPU supports 36-bit I/O | |
609 | # | |
610 | config IO_36 | |
611 | bool | |
612 | ||
1da177e4 LT |
613 | comment "Processor Features" |
614 | ||
497b7e94 CM |
615 | config ARM_LPAE |
616 | bool "Support for the Large Physical Address Extension" | |
08a183f0 CM |
617 | depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \ |
618 | !CPU_32v4 && !CPU_32v3 | |
497b7e94 CM |
619 | help |
620 | Say Y if you have an ARMv7 processor supporting the LPAE page | |
621 | table format and you would like to access memory beyond the | |
622 | 4GB limit. The resulting kernel image will not run on | |
623 | processors without the LPA extension. | |
624 | ||
625 | If unsure, say N. | |
626 | ||
627 | config ARCH_PHYS_ADDR_T_64BIT | |
628 | def_bool ARM_LPAE | |
629 | ||
630 | config ARCH_DMA_ADDR_T_64BIT | |
631 | bool | |
632 | ||
1da177e4 | 633 | config ARM_THUMB |
bc7dea00 | 634 | bool "Support Thumb user binaries" if !CPU_THUMBONLY |
4477ca45 UKK |
635 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \ |
636 | CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \ | |
637 | CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ | |
638 | CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \ | |
639 | CPU_V7 || CPU_FEROCEON || CPU_V7M | |
1da177e4 LT |
640 | default y |
641 | help | |
642 | Say Y if you want to include kernel support for running user space | |
643 | Thumb binaries. | |
644 | ||
645 | The Thumb instruction set is a compressed form of the standard ARM | |
646 | instruction set resulting in smaller binaries at the expense of | |
647 | slightly less efficient code. | |
648 | ||
649 | If you don't know what this all is, saying Y is a safe choice. | |
650 | ||
d7f864be CM |
651 | config ARM_THUMBEE |
652 | bool "Enable ThumbEE CPU extension" | |
653 | depends on CPU_V7 | |
654 | help | |
655 | Say Y here if you have a CPU with the ThumbEE extension and code to | |
656 | make use of it. Say N for code that can run on CPUs without ThumbEE. | |
657 | ||
5b6728d4 | 658 | config ARM_VIRT_EXT |
651134b0 WD |
659 | bool |
660 | depends on MMU | |
661 | default y if CPU_V7 | |
5b6728d4 DM |
662 | help |
663 | Enable the kernel to make use of the ARM Virtualization | |
664 | Extensions to install hypervisors without run-time firmware | |
665 | assistance. | |
666 | ||
667 | A compliant bootloader is required in order to make maximum | |
668 | use of this feature. Refer to Documentation/arm/Booting for | |
669 | details. | |
670 | ||
64d2dc38 | 671 | config SWP_EMULATE |
a11dd731 | 672 | bool "Emulate SWP/SWPB instructions" if !SMP |
b6ccb980 | 673 | depends on CPU_V7 |
64d2dc38 | 674 | default y if SMP |
b1b3f49c | 675 | select HAVE_PROC_CPU if PROC_FS |
64d2dc38 LL |
676 | help |
677 | ARMv6 architecture deprecates use of the SWP/SWPB instructions. | |
678 | ARMv7 multiprocessing extensions introduce the ability to disable | |
679 | these instructions, triggering an undefined instruction exception | |
680 | when executed. Say Y here to enable software emulation of these | |
681 | instructions for userspace (not kernel) using LDREX/STREX. | |
682 | Also creates /proc/cpu/swp_emulation for statistics. | |
683 | ||
684 | In some older versions of glibc [<=2.8] SWP is used during futex | |
685 | trylock() operations with the assumption that the code will not | |
686 | be preempted. This invalid assumption may be more likely to fail | |
687 | with SWP emulation enabled, leading to deadlock of the user | |
688 | application. | |
689 | ||
690 | NOTE: when accessing uncached shared regions, LDREX/STREX rely | |
691 | on an external transaction monitoring block called a global | |
692 | monitor to maintain update atomicity. If your system does not | |
693 | implement a global monitor, this option can cause programs that | |
694 | perform SWP operations to uncached memory to deadlock. | |
695 | ||
696 | If unsure, say Y. | |
697 | ||
1da177e4 LT |
698 | config CPU_BIG_ENDIAN |
699 | bool "Build big-endian kernel" | |
700 | depends on ARCH_SUPPORTS_BIG_ENDIAN | |
701 | help | |
702 | Say Y if you plan on running a kernel in big-endian mode. | |
703 | Note that your board must be properly built and your board | |
704 | port must properly enable any big-endian related features | |
705 | of your chipset/board/processor. | |
706 | ||
26584853 CM |
707 | config CPU_ENDIAN_BE8 |
708 | bool | |
709 | depends on CPU_BIG_ENDIAN | |
e399b1a4 | 710 | default CPU_V6 || CPU_V6K || CPU_V7 |
26584853 CM |
711 | help |
712 | Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. | |
713 | ||
714 | config CPU_ENDIAN_BE32 | |
715 | bool | |
716 | depends on CPU_BIG_ENDIAN | |
717 | default !CPU_ENDIAN_BE8 | |
718 | help | |
719 | Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. | |
720 | ||
6afd6fae | 721 | config CPU_HIGH_VECTOR |
6340aa61 | 722 | depends on !MMU && CPU_CP15 && !CPU_ARM740T |
6afd6fae | 723 | bool "Select the High exception vector" |
6afd6fae HC |
724 | help |
725 | Say Y here to select high exception vector(0xFFFF0000~). | |
9b7333a9 | 726 | The exception vector can vary depending on the platform |
6afd6fae HC |
727 | design in nommu mode. If your platform needs to select |
728 | high exception vector, say Y. | |
729 | Otherwise or if you are unsure, say N, and the low exception | |
730 | vector (0x00000000~) will be used. | |
731 | ||
1da177e4 | 732 | config CPU_ICACHE_DISABLE |
f12d0d7c | 733 | bool "Disable I-Cache (I-bit)" |
357c9c1f | 734 | depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) |
1da177e4 LT |
735 | help |
736 | Say Y here to disable the processor instruction cache. Unless | |
737 | you have a reason not to or are unsure, say N. | |
738 | ||
739 | config CPU_DCACHE_DISABLE | |
f12d0d7c HC |
740 | bool "Disable D-Cache (C-bit)" |
741 | depends on CPU_CP15 | |
1da177e4 LT |
742 | help |
743 | Say Y here to disable the processor data cache. Unless | |
744 | you have a reason not to or are unsure, say N. | |
745 | ||
f37f46eb HC |
746 | config CPU_DCACHE_SIZE |
747 | hex | |
748 | depends on CPU_ARM740T || CPU_ARM946E | |
749 | default 0x00001000 if CPU_ARM740T | |
750 | default 0x00002000 # default size for ARM946E-S | |
751 | help | |
752 | Some cores are synthesizable to have various sized cache. For | |
753 | ARM946E-S case, it can vary from 0KB to 1MB. | |
754 | To support such cache operations, it is efficient to know the size | |
755 | before compile time. | |
756 | If your SoC is configured to have a different size, define the value | |
757 | here with proper conditions. | |
758 | ||
1da177e4 LT |
759 | config CPU_DCACHE_WRITETHROUGH |
760 | bool "Force write through D-cache" | |
28853ac8 | 761 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE |
1da177e4 LT |
762 | default y if CPU_ARM925T |
763 | help | |
764 | Say Y here to use the data cache in writethrough mode. Unless you | |
765 | specifically require this or are unsure, say N. | |
766 | ||
767 | config CPU_CACHE_ROUND_ROBIN | |
768 | bool "Round robin I and D cache replacement algorithm" | |
f37f46eb | 769 | depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) |
1da177e4 LT |
770 | help |
771 | Say Y here to use the predictable round-robin cache replacement | |
772 | policy. Unless you specifically require this or are unsure, say N. | |
773 | ||
774 | config CPU_BPREDICT_DISABLE | |
775 | bool "Disable branch prediction" | |
e399b1a4 | 776 | depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 |
1da177e4 LT |
777 | help |
778 | Say Y here to disable branch prediction. If unsure, say N. | |
2d2669b6 | 779 | |
4b0e07a5 NP |
780 | config TLS_REG_EMUL |
781 | bool | |
f6f91b0d | 782 | select NEED_KUSER_HELPERS |
4b0e07a5 | 783 | help |
70489c88 NP |
784 | An SMP system using a pre-ARMv6 processor (there are apparently |
785 | a few prototypes like that in existence) and therefore access to | |
786 | that required register must be emulated. | |
4b0e07a5 | 787 | |
dcef1f63 NP |
788 | config NEEDS_SYSCALL_FOR_CMPXCHG |
789 | bool | |
f6f91b0d | 790 | select NEED_KUSER_HELPERS |
dcef1f63 NP |
791 | help |
792 | SMP on a pre-ARMv6 processor? Well OK then. | |
793 | Forget about fast user space cmpxchg support. | |
794 | It is just not possible. | |
795 | ||
f6f91b0d RK |
796 | config NEED_KUSER_HELPERS |
797 | bool | |
798 | ||
799 | config KUSER_HELPERS | |
800 | bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS | |
801 | default y | |
802 | help | |
803 | Warning: disabling this option may break user programs. | |
804 | ||
805 | Provide kuser helpers in the vector page. The kernel provides | |
806 | helper code to userspace in read only form at a fixed location | |
807 | in the high vector page to allow userspace to be independent of | |
808 | the CPU type fitted to the system. This permits binaries to be | |
809 | run on ARMv4 through to ARMv7 without modification. | |
810 | ||
ac124504 NP |
811 | See Documentation/arm/kernel_user_helpers.txt for details. |
812 | ||
f6f91b0d RK |
813 | However, the fixed address nature of these helpers can be used |
814 | by ROP (return orientated programming) authors when creating | |
815 | exploits. | |
816 | ||
817 | If all of the binaries and libraries which run on your platform | |
818 | are built specifically for your platform, and make no use of | |
ac124504 NP |
819 | these helpers, then you can turn this option off to hinder |
820 | such exploits. However, in that case, if a binary or library | |
821 | relying on those helpers is run, it will receive a SIGILL signal, | |
822 | which will terminate the program. | |
f6f91b0d RK |
823 | |
824 | Say N here only if you are absolutely certain that you do not | |
825 | need these helpers; otherwise, the safe option is to say Y. | |
826 | ||
ad642d9f CM |
827 | config DMA_CACHE_RWFO |
828 | bool "Enable read/write for ownership DMA cache maintenance" | |
3bc28c8e | 829 | depends on CPU_V6K && SMP |
ad642d9f CM |
830 | default y |
831 | help | |
832 | The Snoop Control Unit on ARM11MPCore does not detect the | |
833 | cache maintenance operations and the dma_{map,unmap}_area() | |
834 | functions may leave stale cache entries on other CPUs. By | |
835 | enabling this option, Read or Write For Ownership in the ARMv6 | |
836 | DMA cache maintenance functions is performed. These LDR/STR | |
837 | instructions change the cache line state to shared or modified | |
838 | so that the cache operation has the desired effect. | |
839 | ||
840 | Note that the workaround is only valid on processors that do | |
841 | not perform speculative loads into the D-cache. For such | |
842 | processors, if cache maintenance operations are not broadcast | |
843 | in hardware, other workarounds are needed (e.g. cache | |
844 | maintenance broadcasting in software via FIQ). | |
845 | ||
953233dc CM |
846 | config OUTER_CACHE |
847 | bool | |
382266ad | 848 | |
319f551a CM |
849 | config OUTER_CACHE_SYNC |
850 | bool | |
851 | help | |
852 | The outer cache has a outer_cache_fns.sync function pointer | |
853 | that can be used to drain the write buffer of the outer cache. | |
854 | ||
99c6dc11 LB |
855 | config CACHE_FEROCEON_L2 |
856 | bool "Enable the Feroceon L2 cache controller" | |
ba364fc7 | 857 | depends on ARCH_MV78XX0 || ARCH_MVEBU |
99c6dc11 LB |
858 | default y |
859 | select OUTER_CACHE | |
860 | help | |
861 | This option enables the Feroceon L2 cache controller. | |
862 | ||
4360bb41 RS |
863 | config CACHE_FEROCEON_L2_WRITETHROUGH |
864 | bool "Force Feroceon L2 cache write through" | |
865 | depends on CACHE_FEROCEON_L2 | |
4360bb41 RS |
866 | help |
867 | Say Y here to use the Feroceon L2 cache in writethrough mode. | |
868 | Unless you specifically require this, say N for writeback mode. | |
869 | ||
ce5ea9f3 DM |
870 | config MIGHT_HAVE_CACHE_L2X0 |
871 | bool | |
872 | help | |
873 | This option should be selected by machines which have a L2x0 | |
874 | or PL310 cache controller, but where its use is optional. | |
875 | ||
876 | The only effect of this option is to make CACHE_L2X0 and | |
877 | related options available to the user for configuration. | |
878 | ||
879 | Boards or SoCs which always require the cache controller | |
880 | support to be present should select CACHE_L2X0 directly | |
881 | instead of this option, thus preventing the user from | |
882 | inadvertently configuring a broken kernel. | |
883 | ||
382266ad | 884 | config CACHE_L2X0 |
ce5ea9f3 DM |
885 | bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0 |
886 | default MIGHT_HAVE_CACHE_L2X0 | |
382266ad | 887 | select OUTER_CACHE |
23107c54 | 888 | select OUTER_CACHE_SYNC |
ba927951 CM |
889 | help |
890 | This option enables the L2x0 PrimeCell. | |
905a09d5 | 891 | |
a641f3a6 RK |
892 | if CACHE_L2X0 |
893 | ||
9a6655e4 CM |
894 | config CACHE_PL310 |
895 | bool | |
e399b1a4 | 896 | default y if CPU_V7 && !(CPU_V6 || CPU_V6K) |
9a6655e4 CM |
897 | help |
898 | This option enables optimisations for the PL310 cache | |
899 | controller. | |
900 | ||
c0fe18ba RK |
901 | config PL310_ERRATA_588369 |
902 | bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines" | |
c0fe18ba RK |
903 | help |
904 | The PL310 L2 cache controller implements three types of Clean & | |
905 | Invalidate maintenance operations: by Physical Address | |
906 | (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). | |
907 | They are architecturally defined to behave as the execution of a | |
908 | clean operation followed immediately by an invalidate operation, | |
909 | both performing to the same memory location. This functionality | |
80d3cb91 SG |
910 | is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0) |
911 | as clean lines are not invalidated as a result of these operations. | |
c0fe18ba RK |
912 | |
913 | config PL310_ERRATA_727915 | |
914 | bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption" | |
c0fe18ba RK |
915 | help |
916 | PL310 implements the Clean & Invalidate by Way L2 cache maintenance | |
917 | operation (offset 0x7FC). This operation runs in background so that | |
918 | PL310 can handle normal accesses while it is in progress. Under very | |
919 | rare circumstances, due to this erratum, write data can be lost when | |
920 | PL310 treats a cacheable write transaction during a Clean & | |
80d3cb91 SG |
921 | Invalidate by Way operation. Revisions prior to r3p1 are affected by |
922 | this errata (fixed in r3p1). | |
c0fe18ba RK |
923 | |
924 | config PL310_ERRATA_753970 | |
925 | bool "PL310 errata: cache sync operation may be faulty" | |
c0fe18ba RK |
926 | help |
927 | This option enables the workaround for the 753970 PL310 (r3p0) erratum. | |
928 | ||
929 | Under some condition the effect of cache sync operation on | |
930 | the store buffer still remains when the operation completes. | |
931 | This means that the store buffer is always asked to drain and | |
932 | this prevents it from merging any further writes. The workaround | |
933 | is to replace the normal offset of cache sync operation (0x730) | |
934 | by another offset targeting an unmapped PL310 register 0x740. | |
935 | This has the same effect as the cache sync operation: store buffer | |
936 | drain and waiting for all buffers empty. | |
937 | ||
938 | config PL310_ERRATA_769419 | |
939 | bool "PL310 errata: no automatic Store Buffer drain" | |
c0fe18ba RK |
940 | help |
941 | On revisions of the PL310 prior to r3p2, the Store Buffer does | |
942 | not automatically drain. This can cause normal, non-cacheable | |
943 | writes to be retained when the memory system is idle, leading | |
944 | to suboptimal I/O performance for drivers using coherent DMA. | |
945 | This option adds a write barrier to the cpu_idle loop so that, | |
946 | on systems with an outer cache, the store buffer is drained | |
947 | explicitly. | |
948 | ||
a641f3a6 RK |
949 | endif |
950 | ||
573a652f LB |
951 | config CACHE_TAUROS2 |
952 | bool "Enable the Tauros2 L2 cache controller" | |
3f408fa0 | 953 | depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) |
573a652f LB |
954 | default y |
955 | select OUTER_CACHE | |
956 | help | |
957 | This option enables the Tauros2 L2 cache controller (as | |
958 | found on PJ1/PJ4). | |
959 | ||
905a09d5 EM |
960 | config CACHE_XSC3L2 |
961 | bool "Enable the L2 cache on XScale3" | |
962 | depends on CPU_XSC3 | |
963 | default y | |
964 | select OUTER_CACHE | |
965 | help | |
966 | This option enables the L2 cache on XScale3. | |
910a17e5 | 967 | |
5637a126 RK |
968 | config ARM_L1_CACHE_SHIFT_6 |
969 | bool | |
a092f2b1 | 970 | default y if CPU_V7 |
5637a126 RK |
971 | help |
972 | Setting ARM L1 cache line size to 64 Bytes. | |
973 | ||
910a17e5 KS |
974 | config ARM_L1_CACHE_SHIFT |
975 | int | |
d6d502fa | 976 | default 6 if ARM_L1_CACHE_SHIFT_6 |
910a17e5 | 977 | default 5 |
47ab0dee RK |
978 | |
979 | config ARM_DMA_MEM_BUFFERABLE | |
e399b1a4 | 980 | bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7 |
42c4dafe CM |
981 | depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \ |
982 | MACH_REALVIEW_PB11MP) | |
e399b1a4 | 983 | default y if CPU_V6 || CPU_V6K || CPU_V7 |
47ab0dee RK |
984 | help |
985 | Historically, the kernel has used strongly ordered mappings to | |
986 | provide DMA coherent memory. With the advent of ARMv7, mapping | |
987 | memory with differing types results in unpredictable behaviour, | |
988 | so on these CPUs, this option is forced on. | |
989 | ||
990 | Multiple mappings with differing attributes is also unpredictable | |
991 | on ARMv6 CPUs, but since they do not have aggressive speculative | |
992 | prefetch, no harm appears to occur. | |
993 | ||
994 | However, drivers may be missing the necessary barriers for ARMv6, | |
995 | and therefore turning this on may result in unpredictable driver | |
996 | behaviour. Therefore, we offer this as an option. | |
997 | ||
998 | You are recommended say 'Y' here and debug any affected drivers. | |
ac1d426e | 999 | |
e7c5650f CM |
1000 | config ARCH_HAS_BARRIERS |
1001 | bool | |
1002 | help | |
1003 | This option allows the use of custom mandatory barriers | |
1004 | included via the mach/barriers.h file. | |
d10d2d48 BD |
1005 | |
1006 | config ARCH_SUPPORTS_BIG_ENDIAN | |
1007 | bool | |
1008 | help | |
1009 | This option specifies the architecture can support big endian | |
1010 | operation. |