[linux-block.git] / arch / arm / mach-vexpress / dcscb_setup.S

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * arch/arm/include/asm/dcscb_setup.S
 *
 * Created by:  Dave Martin, 2012-06-22
 * Copyright:   (C) 2012-2013  Linaro Limited
 */

#include <linux/linkage.h>


ENTRY(dcscb_power_up_setup)

	cmp	r0, #0			@ check affinity level
	beq	2f

/*
 * Enable cluster-level coherency, in preparation for turning on the MMU.
 * The ACTLR SMP bit does not need to be set here, because cpu_resume()
 * already restores that.
 *
 * A15/A7 may not require explicit L2 invalidation on reset, dependent
 * on hardware integration decisions.
 * For now, this code assumes that L2 is either already invalidated,
 * or invalidation is not required.
 */

	b	cci_enable_port_for_self

2:	@ Implementation-specific local CPU setup operations should go here,
	@ if any.  In this case, there is nothing to do.

	bx	lr

ENDPROC(dcscb_power_up_setup)
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
d41418c0 DM	2	/*
	3	* arch/arm/include/asm/dcscb_setup.S
	4	*
	5	* Created by: Dave Martin, 2012-06-22
	6	* Copyright: (C) 2012-2013 Linaro Limited
d41418c0 DM	7	*/
	8
	9	#include <linux/linkage.h>
	10
	11
	12	ENTRY(dcscb_power_up_setup)
	13
	14	cmp r0, #0 @ check affinity level
	15	beq 2f
	16
	17	/*
	18	* Enable cluster-level coherency, in preparation for turning on the MMU.
	19	* The ACTLR SMP bit does not need to be set here, because cpu_resume()
	20	* already restores that.
	21	*
	22	* A15/A7 may not require explicit L2 invalidation on reset, dependent
	23	* on hardware integration decisions.
	24	* For now, this code assumes that L2 is either already invalidated,
	25	* or invalidation is not required.
	26	*/
	27
	28	b cci_enable_port_for_self
	29
	30	2: @ Implementation-specific local CPU setup operations should go here,
	31	@ if any. In this case, there is nothing to do.
	32
	33	bx lr
	34
	35	ENDPROC(dcscb_power_up_setup)