[linux-2.6-block.git] / arch / arm / mach-versatile / pci.c

/*
 *  linux/arch/arm/mach-versatile/pci.c
 *
 * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
 * You can redistribute and/or modify this software under the terms of version 2
 * of the GNU General Public License as published by the Free Software Foundation.
 * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
 *
 * ARM Versatile PCI driver.
 *
 * 14/04/2005 Initial version, colin.king@philips.com
 *
 */
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/init.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/irqs.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>

/*
 * these spaces are mapped using the following base registers:
 *
 * Usage Local Bus Memory         Base/Map registers used
 *
 * Mem   50000000 - 5FFFFFFF      LB_BASE0/LB_MAP0,  non prefetch
 * Mem   60000000 - 6FFFFFFF      LB_BASE1/LB_MAP1,  prefetch
 * IO    44000000 - 4FFFFFFF      LB_BASE2/LB_MAP2,  IO
 * Cfg   42000000 - 42FFFFFF	  PCI config
 *
 */
#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
#define SYS_PCICTL		__IO_ADDRESS(VERSATILE_SYS_PCICTL)
#define PCI_IMAP0		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
#define PCI_IMAP1		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
#define PCI_IMAP2		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
#define PCI_SMAP0		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
#define PCI_SMAP1		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
#define PCI_SMAP2		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x1c)
#define PCI_SELFID		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)

#define DEVICE_ID_OFFSET		0x00
#define CSR_OFFSET			0x04
#define CLASS_ID_OFFSET			0x08

#define VP_PCI_DEVICE_ID		0x030010ee
#define VP_PCI_CLASS_ID			0x0b400000

static unsigned long pci_slot_ignore = 0;

static int __init versatile_pci_slot_ignore(char *str)
{
	int retval;
	int slot;

	while ((retval = get_option(&str,&slot))) {
		if ((slot < 0) || (slot > 31)) {
			printk("Illegal slot value: %d\n",slot);
		} else {
			pci_slot_ignore |= (1 << slot);
		}
	}
	return 1;
}

__setup("pci_slot_ignore=", versatile_pci_slot_ignore);


static void __iomem *__pci_addr(struct pci_bus *bus,
				unsigned int devfn, int offset)
{
	unsigned int busnr = bus->number;

	/*
	 * Trap out illegal values
	 */
	if (offset > 255)
		BUG();
	if (busnr > 255)
		BUG();
	if (devfn > 255)
		BUG();

	return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) |
		(PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
}

static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
				 int size, u32 *val)
{
	void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
	u32 v;
	int slot = PCI_SLOT(devfn);

	if (pci_slot_ignore & (1 << slot)) {
		/* Ignore this slot */
		switch (size) {
		case 1:
			v = 0xff;
			break;
		case 2:
			v = 0xffff;
			break;
		default:
			v = 0xffffffff;
		}
	} else {
		switch (size) {
		case 1:
			v = __raw_readl(addr);
			if (where & 2) v >>= 16;
			if (where & 1) v >>= 8;
 			v &= 0xff;
			break;

		case 2:
			v = __raw_readl(addr);
			if (where & 2) v >>= 16;
 			v &= 0xffff;
			break;

		default:
			v = __raw_readl(addr);
			break;
		}
	}

	*val = v;
	return PCIBIOS_SUCCESSFUL;
}

static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
				  int size, u32 val)
{
	void __iomem *addr = __pci_addr(bus, devfn, where);
	int slot = PCI_SLOT(devfn);

	if (pci_slot_ignore & (1 << slot)) {
		return PCIBIOS_SUCCESSFUL;
	}

	switch (size) {
	case 1:
		__raw_writeb((u8)val, addr);
		break;

	case 2:
		__raw_writew((u16)val, addr);
		break;

	case 4:
		__raw_writel(val, addr);
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops pci_versatile_ops = {
	.read	= versatile_read_config,
	.write	= versatile_write_config,
};

static struct resource unused_mem = {
	.name	= "PCI unused",
	.start	= VERSATILE_PCI_MEM_BASE0,
	.end	= VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
	.flags	= IORESOURCE_MEM,
};

static struct resource non_mem = {
	.name	= "PCI non-prefetchable",
	.start	= VERSATILE_PCI_MEM_BASE1,
	.end	= VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
	.flags	= IORESOURCE_MEM,
};

static struct resource pre_mem = {
	.name	= "PCI prefetchable",
	.start	= VERSATILE_PCI_MEM_BASE2,
	.end	= VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
	.flags	= IORESOURCE_MEM | IORESOURCE_PREFETCH,
};

static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
{
	int ret = 0;

	ret = request_resource(&iomem_resource, &unused_mem);
	if (ret) {
		printk(KERN_ERR "PCI: unable to allocate unused "
		       "memory region (%d)\n", ret);
		goto out;
	}
	ret = request_resource(&iomem_resource, &non_mem);
	if (ret) {
		printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
		       "memory region (%d)\n", ret);
		goto release_unused_mem;
	}
	ret = request_resource(&iomem_resource, &pre_mem);
	if (ret) {
		printk(KERN_ERR "PCI: unable to allocate prefetchable "
		       "memory region (%d)\n", ret);
		goto release_non_mem;
	}

	/*
	 * the mem resource for this bus
	 * the prefetch mem resource for this bus
	 */
	pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
	pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);

	goto out;

 release_non_mem:
	release_resource(&non_mem);
 release_unused_mem:
	release_resource(&unused_mem);
 out:
	return ret;
}

int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
{
	int ret = 0;
        int i;
        int myslot = -1;
	unsigned long val;
	void __iomem *local_pci_cfg_base;

	val = __raw_readl(SYS_PCICTL);
	if (!(val & 1)) {
		printk("Not plugged into PCI backplane!\n");
		ret = -EIO;
		goto out;
	}

	ret = pci_ioremap_io(0, VERSATILE_PCI_IO_BASE);
	if (ret)
		goto out;

	if (nr == 0) {
		ret = pci_versatile_setup_resources(sys);
		if (ret < 0) {
			printk("pci_versatile_setup: resources... oops?\n");
			goto out;
		}
	} else {
		printk("pci_versatile_setup: resources... nr == 0??\n");
		goto out;
	}

	/*
	 *  We need to discover the PCI core first to configure itself
	 *  before the main PCI probing is performed
	 */
	for (i=0; i<32; i++)
		if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
		    (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
			myslot = i;
			break;
		}

	if (myslot == -1) {
		printk("Cannot find PCI core!\n");
		ret = -EIO;
		goto out;
	}

	printk("PCI core found (slot %d)\n",myslot);

	__raw_writel(myslot, PCI_SELFID);
	local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);

	val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
	val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
	__raw_writel(val, local_pci_cfg_base + CSR_OFFSET);

	/*
	 * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
	 */
	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);

	/*
	 * For many years the kernel and QEMU were symbiotically buggy
	 * in that they both assumed the same broken IRQ mapping.
	 * QEMU therefore attempts to auto-detect old broken kernels
	 * so that they still work on newer QEMU as they did on old
	 * QEMU. Since we now use the correct (ie matching-hardware)
	 * IRQ mapping we write a definitely different value to a
	 * PCI_INTERRUPT_LINE register to tell QEMU that we expect
	 * real hardware behaviour and it need not be backwards
	 * compatible for us. This write is harmless on real hardware.
	 */
	__raw_writel(0, VERSATILE_PCI_VIRT_BASE+PCI_INTERRUPT_LINE);

	/*
	 * Do not to map Versatile FPGA PCI device into memory space
	 */
	pci_slot_ignore |= (1 << myslot);
	ret = 1;

 out:
	return ret;
}


void __init pci_versatile_preinit(void)
{
	pcibios_min_mem = 0x50000000;

	__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
	__raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
	__raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);

	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);

	__raw_writel(1, SYS_PCICTL);
}

/*
 * map the specified device/slot/pin to an IRQ.   Different backplanes may need to modify this.
 */
static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
	int irq;

	/*
	 * Slot	INTA	INTB	INTC	INTD
	 * 31	PCI1	PCI2	PCI3	PCI0
	 * 30	PCI0	PCI1	PCI2	PCI3
	 * 29	PCI3	PCI0	PCI1	PCI2
	 */
	irq = IRQ_SIC_PCI0 + ((slot + 2 + pin - 1) & 3);

	return irq;
}

static struct hw_pci versatile_pci __initdata = {
	.map_irq		= versatile_map_irq,
	.nr_controllers		= 1,
	.ops			= &pci_versatile_ops,
	.setup			= pci_versatile_setup,
	.preinit		= pci_versatile_preinit,
};

static int __init versatile_pci_init(void)
{
	pci_common_init(&versatile_pci);
	return 0;
}

subsys_initcall(versatile_pci_init);
Commit	Line	Data
c0da085a CM	1	/*
	2	* linux/arch/arm/mach-versatile/pci.c
	3	*
	4	* (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
	5	* You can redistribute and/or modify this software under the terms of version 2
	6	* of the GNU General Public License as published by the Free Software Foundation.
	7	* THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
	8	* WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	9	* General Public License for more details.
	10	* Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
	11	*
	12	* ARM Versatile PCI driver.
	13	*
	14	* 14/04/2005 Initial version, colin.king@philips.com
	15	*
	16	*/
c0da085a CM	17	#include <linux/kernel.h>
c0da085a CM	18	#include <linux/pci.h>
c0da085a CM	19	#include <linux/ioport.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/spinlock.h>
	22	#include <linux/init.h>
fced80c7	23	#include <linux/io.h>
c0da085a	24
a09e64fb	25	#include <mach/hardware.h>
e3e92a7b	26	#include <mach/irqs.h>
c0da085a	27	#include <asm/irq.h>
c0da085a	28	#include <asm/mach/pci.h>
c0da085a CM	29
	30	/*
	31	* these spaces are mapped using the following base registers:
	32	*
	33	* Usage Local Bus Memory Base/Map registers used
	34	*
	35	* Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
	36	* Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
	37	* IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
	38	* Cfg 42000000 - 42FFFFFF PCI config
	39	*
	40	*/
399ad77b AV	41	#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
	42	#define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL)
	43	#define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
	44	#define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
	45	#define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
99f2b130 PM	46	#define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
	47	#define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
	48	#define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x1c)
399ad77b	49	#define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
c0da085a CM	50
	51	#define DEVICE_ID_OFFSET 0x00
	52	#define CSR_OFFSET 0x04
	53	#define CLASS_ID_OFFSET 0x08
	54
	55	#define VP_PCI_DEVICE_ID 0x030010ee
	56	#define VP_PCI_CLASS_ID 0x0b400000
	57
	58	static unsigned long pci_slot_ignore = 0;
	59
	60	static int __init versatile_pci_slot_ignore(char *str)
	61	{
	62	int retval;
	63	int slot;
	64
	65	while ((retval = get_option(&str,&slot))) {
	66	if ((slot < 0) \|\| (slot > 31)) {
	67	printk("Illegal slot value: %d\n",slot);
	68	} else {
	69	pci_slot_ignore \|= (1 << slot);
	70	}
	71	}
	72	return 1;
	73	}
	74
	75	__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
	76
	77
399ad77b	78	static void __iomem __pci_addr(struct pci_bus bus,
c0da085a CM	79	unsigned int devfn, int offset)
	80	{
	81	unsigned int busnr = bus->number;
	82
	83	/*
	84	* Trap out illegal values
	85	*/
	86	if (offset > 255)
	87	BUG();
	88	if (busnr > 255)
	89	BUG();
	90	if (devfn > 255)
	91	BUG();
	92
399ad77b	93	return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) \|
c0da085a CM	94	(PCI_SLOT(devfn) << 11) \| (PCI_FUNC(devfn) << 8) \| offset);
	95	}
	96
	97	static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
	98	int size, u32 *val)
	99	{
399ad77b	100	void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
c0da085a CM	101	u32 v;
	102	int slot = PCI_SLOT(devfn);
	103
	104	if (pci_slot_ignore & (1 << slot)) {
	105	/* Ignore this slot */
	106	switch (size) {
	107	case 1:
	108	v = 0xff;
	109	break;
	110	case 2:
	111	v = 0xffff;
	112	break;
	113	default:
	114	v = 0xffffffff;
	115	}
	116	} else {
	117	switch (size) {
	118	case 1:
756813ca AZ	119	v = __raw_readl(addr);
	120	if (where & 2) v >>= 16;
	121	if (where & 1) v >>= 8;
	122	v &= 0xff;
c0da085a CM	123	break;
	124
	125	case 2:
399ad77b AV	126	v = __raw_readl(addr);
399ad77b AV	127	if (where & 2) v >>= 16;
c0da085a CM	128	v &= 0xffff;
	129	break;
	130
	131	default:
c0da085a CM	132	v = __raw_readl(addr);
	133	break;
	134	}
	135	}
	136
	137	*val = v;
	138	return PCIBIOS_SUCCESSFUL;
	139	}
	140
	141	static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
	142	int size, u32 val)
	143	{
399ad77b	144	void __iomem *addr = __pci_addr(bus, devfn, where);
c0da085a CM	145	int slot = PCI_SLOT(devfn);
	146
	147	if (pci_slot_ignore & (1 << slot)) {
	148	return PCIBIOS_SUCCESSFUL;
	149	}
	150
	151	switch (size) {
	152	case 1:
	153	__raw_writeb((u8)val, addr);
	154	break;
	155
	156	case 2:
	157	__raw_writew((u16)val, addr);
	158	break;
	159
	160	case 4:
	161	__raw_writel(val, addr);
	162	break;
	163	}
	164
	165	return PCIBIOS_SUCCESSFUL;
	166	}
	167
	168	static struct pci_ops pci_versatile_ops = {
	169	.read = versatile_read_config,
	170	.write = versatile_write_config,
	171	};
	172
829f9fed PM	173	static struct resource unused_mem = {
829f9fed PM	174	.name = "PCI unused",
c0da085a CM	175	.start = VERSATILE_PCI_MEM_BASE0,
c0da085a CM	176	.end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
9b0f7e39	177	.flags = IORESOURCE_MEM,
c0da085a CM	178	};
	179
	180	static struct resource non_mem = {
	181	.name = "PCI non-prefetchable",
	182	.start = VERSATILE_PCI_MEM_BASE1,
	183	.end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
	184	.flags = IORESOURCE_MEM,
	185	};
	186
	187	static struct resource pre_mem = {
	188	.name = "PCI prefetchable",
	189	.start = VERSATILE_PCI_MEM_BASE2,
	190	.end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
	191	.flags = IORESOURCE_MEM \| IORESOURCE_PREFETCH,
	192	};
	193
ee5324ea	194	static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
c0da085a CM	195	{
	196	int ret = 0;
	197
829f9fed	198	ret = request_resource(&iomem_resource, &unused_mem);
c0da085a	199	if (ret) {
829f9fed	200	printk(KERN_ERR "PCI: unable to allocate unused "
c0da085a CM	201	"memory region (%d)\n", ret);
	202	goto out;
	203	}
	204	ret = request_resource(&iomem_resource, &non_mem);
	205	if (ret) {
	206	printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
	207	"memory region (%d)\n", ret);
829f9fed	208	goto release_unused_mem;
c0da085a CM	209	}
	210	ret = request_resource(&iomem_resource, &pre_mem);
	211	if (ret) {
	212	printk(KERN_ERR "PCI: unable to allocate prefetchable "
	213	"memory region (%d)\n", ret);
	214	goto release_non_mem;
	215	}
	216
	217	/*
37d15909 BH	218	* the mem resource for this bus
37d15909 BH	219	* the prefetch mem resource for this bus
c0da085a	220	*/
ee5324ea PG	221	pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
ee5324ea PG	222	pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
c0da085a CM	223
	224	goto out;
	225
	226	release_non_mem:
	227	release_resource(&non_mem);
829f9fed PM	228	release_unused_mem:
829f9fed PM	229	release_resource(&unused_mem);
c0da085a CM	230	out:
	231	return ret;
	232	}
	233
	234	int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
	235	{
	236	int ret = 0;
	237	int i;
	238	int myslot = -1;
	239	unsigned long val;
c27a2164 CM	240	void __iomem *local_pci_cfg_base;
	241
	242	val = __raw_readl(SYS_PCICTL);
	243	if (!(val & 1)) {
	244	printk("Not plugged into PCI backplane!\n");
	245	ret = -EIO;
	246	goto out;
	247	}
c0da085a	248
829f9fed	249	ret = pci_ioremap_io(0, VERSATILE_PCI_IO_BASE);
fe505175 RH	250	if (ret)
	251	goto out;
	252
c0da085a	253	if (nr == 0) {
ee5324ea	254	ret = pci_versatile_setup_resources(sys);
c0da085a CM	255	if (ret < 0) {
	256	printk("pci_versatile_setup: resources... oops?\n");
	257	goto out;
	258	}
	259	} else {
	260	printk("pci_versatile_setup: resources... nr == 0??\n");
	261	goto out;
	262	}
	263
c0da085a CM	264	/*
	265	* We need to discover the PCI core first to configure itself
	266	* before the main PCI probing is performed
	267	*/
c27a2164	268	for (i=0; i<32; i++)
c0da085a CM	269	if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
	270	(__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
	271	myslot = i;
c0da085a CM	272	break;
c0da085a CM	273	}
c0da085a CM	274
	275	if (myslot == -1) {
	276	printk("Cannot find PCI core!\n");
	277	ret = -EIO;
c27a2164	278	goto out;
c0da085a CM	279	}
c0da085a CM	280
c27a2164 CM	281	printk("PCI core found (slot %d)\n",myslot);
	282
	283	__raw_writel(myslot, PCI_SELFID);
399ad77b	284	local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
c27a2164 CM	285
	286	val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
	287	val \|= PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER \| PCI_COMMAND_INVALIDATE;
	288	__raw_writel(val, local_pci_cfg_base + CSR_OFFSET);
	289
	290	/*
	291	* Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
	292	*/
	293	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0);
	294	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
	295	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
	296
f9b71fef PM	297	/*
	298	* For many years the kernel and QEMU were symbiotically buggy
	299	* in that they both assumed the same broken IRQ mapping.
	300	* QEMU therefore attempts to auto-detect old broken kernels
	301	* so that they still work on newer QEMU as they did on old
	302	* QEMU. Since we now use the correct (ie matching-hardware)
	303	* IRQ mapping we write a definitely different value to a
	304	* PCI_INTERRUPT_LINE register to tell QEMU that we expect
	305	* real hardware behaviour and it need not be backwards
	306	* compatible for us. This write is harmless on real hardware.
	307	*/
	308	__raw_writel(0, VERSATILE_PCI_VIRT_BASE+PCI_INTERRUPT_LINE);
	309
c27a2164 CM	310	/*
	311	* Do not to map Versatile FPGA PCI device into memory space
	312	*/
	313	pci_slot_ignore \|= (1 << myslot);
	314	ret = 1;
	315
c0da085a CM	316	out:
	317	return ret;
	318	}
	319
	320
c0da085a CM	321	void __init pci_versatile_preinit(void)
c0da085a CM	322	{
c9d95fbe RH	323	pcibios_min_mem = 0x50000000;
c9d95fbe RH	324
c27a2164 CM	325	__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
	326	__raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
	327	__raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
c0da085a	328
c27a2164 CM	329	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP0);
	330	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP1);
	331	__raw_writel(PHYS_OFFSET >> 28, PCI_SMAP2);
c0da085a	332
c27a2164 CM	333	__raw_writel(1, SYS_PCICTL);
c27a2164 CM	334	}
c0da085a CM	335
	336	/*
	337	* map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
	338	*/
d5341942	339	static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
c0da085a CM	340	{
c0da085a CM	341	int irq;
c0da085a	342
f9b71fef PM	343	/*
	344	* Slot INTA INTB INTC INTD
	345	* 31 PCI1 PCI2 PCI3 PCI0
	346	* 30 PCI0 PCI1 PCI2 PCI3
	347	* 29 PCI3 PCI0 PCI1 PCI2
c27a2164	348	*/
f9b71fef	349	irq = IRQ_SIC_PCI0 + ((slot + 2 + pin - 1) & 3);
c0da085a CM	350
	351	return irq;
	352	}
	353
	354	static struct hw_pci versatile_pci __initdata = {
c0da085a CM	355	.map_irq = versatile_map_irq,
c0da085a CM	356	.nr_controllers = 1,
c23bfc38	357	.ops = &pci_versatile_ops,
c0da085a	358	.setup = pci_versatile_setup,
c0da085a	359	.preinit = pci_versatile_preinit,
c0da085a CM	360	};
	361
	362	static int __init versatile_pci_init(void)
	363	{
	364	pci_common_init(&versatile_pci);
	365	return 0;
	366	}
	367
	368	subsys_initcall(versatile_pci_init);