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1da177e4 | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-versatile/include/mach/irqs.h |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
a09e64fb | 22 | #include <mach/platform.h> |
1da177e4 LT |
23 | |
24 | /* | |
a247b5d5 | 25 | * IRQ interrupts definitions are the same as the INT definitions |
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26 | * held within platform.h |
27 | */ | |
28 | #define IRQ_VIC_START 0 | |
29 | #define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT) | |
30 | #define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT) | |
31 | #define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx) | |
32 | #define IRQ_COMMTx (IRQ_VIC_START + INT_COMMTx) | |
33 | #define IRQ_TIMERINT0_1 (IRQ_VIC_START + INT_TIMERINT0_1) | |
34 | #define IRQ_TIMERINT2_3 (IRQ_VIC_START + INT_TIMERINT2_3) | |
35 | #define IRQ_GPIOINT0 (IRQ_VIC_START + INT_GPIOINT0) | |
36 | #define IRQ_GPIOINT1 (IRQ_VIC_START + INT_GPIOINT1) | |
37 | #define IRQ_GPIOINT2 (IRQ_VIC_START + INT_GPIOINT2) | |
38 | #define IRQ_GPIOINT3 (IRQ_VIC_START + INT_GPIOINT3) | |
39 | #define IRQ_RTCINT (IRQ_VIC_START + INT_RTCINT) | |
40 | #define IRQ_SSPINT (IRQ_VIC_START + INT_SSPINT) | |
41 | #define IRQ_UARTINT0 (IRQ_VIC_START + INT_UARTINT0) | |
42 | #define IRQ_UARTINT1 (IRQ_VIC_START + INT_UARTINT1) | |
43 | #define IRQ_UARTINT2 (IRQ_VIC_START + INT_UARTINT2) | |
44 | #define IRQ_SCIINT (IRQ_VIC_START + INT_SCIINT) | |
45 | #define IRQ_CLCDINT (IRQ_VIC_START + INT_CLCDINT) | |
46 | #define IRQ_DMAINT (IRQ_VIC_START + INT_DMAINT) | |
47 | #define IRQ_PWRFAILINT (IRQ_VIC_START + INT_PWRFAILINT) | |
48 | #define IRQ_MBXINT (IRQ_VIC_START + INT_MBXINT) | |
49 | #define IRQ_GNDINT (IRQ_VIC_START + INT_GNDINT) | |
50 | #define IRQ_VICSOURCE21 (IRQ_VIC_START + INT_VICSOURCE21) | |
51 | #define IRQ_VICSOURCE22 (IRQ_VIC_START + INT_VICSOURCE22) | |
52 | #define IRQ_VICSOURCE23 (IRQ_VIC_START + INT_VICSOURCE23) | |
53 | #define IRQ_VICSOURCE24 (IRQ_VIC_START + INT_VICSOURCE24) | |
54 | #define IRQ_VICSOURCE25 (IRQ_VIC_START + INT_VICSOURCE25) | |
55 | #define IRQ_VICSOURCE26 (IRQ_VIC_START + INT_VICSOURCE26) | |
56 | #define IRQ_VICSOURCE27 (IRQ_VIC_START + INT_VICSOURCE27) | |
57 | #define IRQ_VICSOURCE28 (IRQ_VIC_START + INT_VICSOURCE28) | |
58 | #define IRQ_VICSOURCE29 (IRQ_VIC_START + INT_VICSOURCE29) | |
59 | #define IRQ_VICSOURCE30 (IRQ_VIC_START + INT_VICSOURCE30) | |
60 | #define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31) | |
61 | #define IRQ_VIC_END (IRQ_VIC_START + 31) | |
62 | ||
1da177e4 | 63 | /* |
a247b5d5 | 64 | * FIQ interrupts definitions are the same as the INT definitions. |
1da177e4 LT |
65 | */ |
66 | #define FIQ_WDOGINT INT_WDOGINT | |
67 | #define FIQ_SOFTINT INT_SOFTINT | |
68 | #define FIQ_COMMRx INT_COMMRx | |
69 | #define FIQ_COMMTx INT_COMMTx | |
70 | #define FIQ_TIMERINT0_1 INT_TIMERINT0_1 | |
71 | #define FIQ_TIMERINT2_3 INT_TIMERINT2_3 | |
72 | #define FIQ_GPIOINT0 INT_GPIOINT0 | |
73 | #define FIQ_GPIOINT1 INT_GPIOINT1 | |
74 | #define FIQ_GPIOINT2 INT_GPIOINT2 | |
75 | #define FIQ_GPIOINT3 INT_GPIOINT3 | |
76 | #define FIQ_RTCINT INT_RTCINT | |
77 | #define FIQ_SSPINT INT_SSPINT | |
78 | #define FIQ_UARTINT0 INT_UARTINT0 | |
79 | #define FIQ_UARTINT1 INT_UARTINT1 | |
80 | #define FIQ_UARTINT2 INT_UARTINT2 | |
81 | #define FIQ_SCIINT INT_SCIINT | |
82 | #define FIQ_CLCDINT INT_CLCDINT | |
83 | #define FIQ_DMAINT INT_DMAINT | |
84 | #define FIQ_PWRFAILINT INT_PWRFAILINT | |
85 | #define FIQ_MBXINT INT_MBXINT | |
86 | #define FIQ_GNDINT INT_GNDINT | |
87 | #define FIQ_VICSOURCE21 INT_VICSOURCE21 | |
88 | #define FIQ_VICSOURCE22 INT_VICSOURCE22 | |
89 | #define FIQ_VICSOURCE23 INT_VICSOURCE23 | |
90 | #define FIQ_VICSOURCE24 INT_VICSOURCE24 | |
91 | #define FIQ_VICSOURCE25 INT_VICSOURCE25 | |
92 | #define FIQ_VICSOURCE26 INT_VICSOURCE26 | |
93 | #define FIQ_VICSOURCE27 INT_VICSOURCE27 | |
94 | #define FIQ_VICSOURCE28 INT_VICSOURCE28 | |
95 | #define FIQ_VICSOURCE29 INT_VICSOURCE29 | |
96 | #define FIQ_VICSOURCE30 INT_VICSOURCE30 | |
97 | #define FIQ_VICSOURCE31 INT_VICSOURCE31 | |
98 | ||
99 | ||
1da177e4 LT |
100 | /* |
101 | * Secondary interrupt controller | |
102 | */ | |
103 | #define IRQ_SIC_START 32 | |
104 | #define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B) | |
105 | #define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B) | |
106 | #define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0) | |
107 | #define IRQ_SIC_KMI1 (IRQ_SIC_START + SIC_INT_KMI1) | |
108 | #define IRQ_SIC_SCI3 (IRQ_SIC_START + SIC_INT_SCI3) | |
109 | #define IRQ_SIC_UART3 (IRQ_SIC_START + SIC_INT_UART3) | |
110 | #define IRQ_SIC_CLCD (IRQ_SIC_START + SIC_INT_CLCD) | |
111 | #define IRQ_SIC_TOUCH (IRQ_SIC_START + SIC_INT_TOUCH) | |
112 | #define IRQ_SIC_KEYPAD (IRQ_SIC_START + SIC_INT_KEYPAD) | |
113 | #define IRQ_SIC_DoC (IRQ_SIC_START + SIC_INT_DoC) | |
114 | #define IRQ_SIC_MMCI0A (IRQ_SIC_START + SIC_INT_MMCI0A) | |
115 | #define IRQ_SIC_MMCI1A (IRQ_SIC_START + SIC_INT_MMCI1A) | |
116 | #define IRQ_SIC_AACI (IRQ_SIC_START + SIC_INT_AACI) | |
117 | #define IRQ_SIC_ETH (IRQ_SIC_START + SIC_INT_ETH) | |
118 | #define IRQ_SIC_USB (IRQ_SIC_START + SIC_INT_USB) | |
119 | #define IRQ_SIC_PCI0 (IRQ_SIC_START + SIC_INT_PCI0) | |
120 | #define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1) | |
121 | #define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2) | |
122 | #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) | |
123 | #define IRQ_SIC_END 63 | |
124 | ||
1da177e4 | 125 | #define NR_IRQS 64 |