[linux-block.git] / arch / arm / mach-ux500 / pm.c

/*
 * Copyright (C) ST-Ericsson SA 2010-2013
 * Author: Rickard Andersson <rickard.andersson@stericsson.com> for
 *         ST-Ericsson.
 * Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
 * Author: Ulf Hansson <ulf.hansson@linaro.org> for Linaro.
 *
 * License terms: GNU General Public License (GPL) version 2
 *
 */

#include <linux/kernel.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/suspend.h>
#include <linux/platform_data/arm-ux500-pm.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include "db8500-regs.h"
#include "pm_domains.h"

/* ARM WFI Standby signal register */
#define PRCM_ARM_WFI_STANDBY    (prcmu_base + 0x130)
#define PRCM_ARM_WFI_STANDBY_WFI0		0x08
#define PRCM_ARM_WFI_STANDBY_WFI1		0x10
#define PRCM_IOCR		(prcmu_base + 0x310)
#define PRCM_IOCR_IOFORCE			0x1

/* Dual A9 core interrupt management unit registers */
#define PRCM_A9_MASK_REQ	(prcmu_base + 0x328)
#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ	0x1

#define PRCM_A9_MASK_ACK	(prcmu_base + 0x32c)
#define PRCM_ARMITMSK31TO0	(prcmu_base + 0x11c)
#define PRCM_ARMITMSK63TO32	(prcmu_base + 0x120)
#define PRCM_ARMITMSK95TO64	(prcmu_base + 0x124)
#define PRCM_ARMITMSK127TO96	(prcmu_base + 0x128)
#define PRCM_POWER_STATE_VAL	(prcmu_base + 0x25C)
#define PRCM_ARMITVAL31TO0	(prcmu_base + 0x260)
#define PRCM_ARMITVAL63TO32	(prcmu_base + 0x264)
#define PRCM_ARMITVAL95TO64	(prcmu_base + 0x268)
#define PRCM_ARMITVAL127TO96	(prcmu_base + 0x26C)

static void __iomem *prcmu_base;
static void __iomem *dist_base;

/* This function decouple the gic from the prcmu */
int prcmu_gic_decouple(void)
{
	u32 val = readl(PRCM_A9_MASK_REQ);

	/* Set bit 0 register value to 1 */
	writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
	       PRCM_A9_MASK_REQ);

	/* Make sure the register is updated */
	readl(PRCM_A9_MASK_REQ);

	/* Wait a few cycles for the gic mask completion */
	udelay(1);

	return 0;
}

/* This function recouple the gic with the prcmu */
int prcmu_gic_recouple(void)
{
	u32 val = readl(PRCM_A9_MASK_REQ);

	/* Set bit 0 register value to 0 */
	writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);

	return 0;
}

#define PRCMU_GIC_NUMBER_REGS 5

/*
 * This function checks if there are pending irq on the gic. It only
 * makes sense if the gic has been decoupled before with the
 * db8500_prcmu_gic_decouple function. Disabling an interrupt only
 * disables the forwarding of the interrupt to any CPU interface. It
 * does not prevent the interrupt from changing state, for example
 * becoming pending, or active and pending if it is already
 * active. Hence, we have to check the interrupt is pending *and* is
 * active.
 */
bool prcmu_gic_pending_irq(void)
{
	u32 pr; /* Pending register */
	u32 er; /* Enable register */
	int i;

	/* 5 registers. STI & PPI not skipped */
	for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {

		pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
		er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);

		if (pr & er)
			return true; /* There is a pending interrupt */
	}

	return false;
}

/*
 * This function checks if there are pending interrupt on the
 * prcmu which has been delegated to monitor the irqs with the
 * db8500_prcmu_copy_gic_settings function.
 */
bool prcmu_pending_irq(void)
{
	u32 it, im;
	int i;

	for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
		it = readl(PRCM_ARMITVAL31TO0 + i * 4);
		im = readl(PRCM_ARMITMSK31TO0 + i * 4);
		if (it & im)
			return true; /* There is a pending interrupt */
	}

	return false;
}

/*
 * This function checks if the specified cpu is in in WFI. It's usage
 * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
 * function. Of course passing smp_processor_id() to this function will
 * always return false...
 */
bool prcmu_is_cpu_in_wfi(int cpu)
{
	return readl(PRCM_ARM_WFI_STANDBY) &
		(cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : PRCM_ARM_WFI_STANDBY_WFI0);
}

/*
 * This function copies the gic SPI settings to the prcmu in order to
 * monitor them and abort/finish the retention/off sequence or state.
 */
int prcmu_copy_gic_settings(void)
{
	u32 er; /* Enable register */
	int i;

	/* We skip the STI and PPI */
	for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
		er = readl_relaxed(dist_base +
				   GIC_DIST_ENABLE_SET + (i + 1) * 4);
		writel(er, PRCM_ARMITMSK31TO0 + i * 4);
	}

	return 0;
}

#ifdef CONFIG_SUSPEND
static int ux500_suspend_enter(suspend_state_t state)
{
	cpu_do_idle();
	return 0;
}

static int ux500_suspend_valid(suspend_state_t state)
{
	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
}

static const struct platform_suspend_ops ux500_suspend_ops = {
	.enter	      = ux500_suspend_enter,
	.valid	      = ux500_suspend_valid,
};
#define UX500_SUSPEND_OPS	(&ux500_suspend_ops)
#else
#define UX500_SUSPEND_OPS	NULL
#endif

void __init ux500_pm_init(u32 phy_base, u32 size)
{
	struct device_node *np;

	prcmu_base = ioremap(phy_base, size);
	if (!prcmu_base) {
		pr_err("could not remap PRCMU for PM functions\n");
		return;
	}
	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
	dist_base = of_iomap(np, 0);
	of_node_put(np);
	if (!dist_base) {
		pr_err("could not remap GIC dist base for PM functions\n");
		return;
	}

	/*
	 * On watchdog reboot the GIC is in some cases decoupled.
	 * This will make sure that the GIC is correctly configured.
	 */
	prcmu_gic_recouple();

	/* Set up ux500 suspend callbacks. */
	suspend_set_ops(UX500_SUSPEND_OPS);

	/* Initialize ux500 power domains */
	ux500_pm_domains_init();
}
Commit	Line	Data
1e22a8c6 LW	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010-2013
	3	* Author: Rickard Andersson <rickard.andersson@stericsson.com> for
	4	* ST-Ericsson.
	5	* Author: Daniel Lezcano <daniel.lezcano@linaro.org> for Linaro.
ead9e293 UH	6	* Author: Ulf Hansson <ulf.hansson@linaro.org> for Linaro.
ead9e293 UH	7	*
1e22a8c6 LW	8	* License terms: GNU General Public License (GPL) version 2
	9	*
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/irqchip/arm-gic.h>
	14	#include <linux/delay.h>
	15	#include <linux/io.h>
ead9e293	16	#include <linux/suspend.h>
1e22a8c6	17	#include <linux/platform_data/arm-ux500-pm.h>
26ef94dc LW	18	#include <linux/of.h>
26ef94dc LW	19	#include <linux/of_address.h>
1e22a8c6	20
174e7796	21	#include "db8500-regs.h"
cd931dcf	22	#include "pm_domains.h"
1e22a8c6 LW	23
	24	/* ARM WFI Standby signal register */
	25	#define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130)
	26	#define PRCM_ARM_WFI_STANDBY_WFI0 0x08
	27	#define PRCM_ARM_WFI_STANDBY_WFI1 0x10
	28	#define PRCM_IOCR (prcmu_base + 0x310)
	29	#define PRCM_IOCR_IOFORCE 0x1
	30
	31	/* Dual A9 core interrupt management unit registers */
	32	#define PRCM_A9_MASK_REQ (prcmu_base + 0x328)
	33	#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1
	34
	35	#define PRCM_A9_MASK_ACK (prcmu_base + 0x32c)
	36	#define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c)
	37	#define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120)
	38	#define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124)
	39	#define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128)
	40	#define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C)
	41	#define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260)
	42	#define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264)
	43	#define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268)
	44	#define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C)
	45
	46	static void __iomem *prcmu_base;
26ef94dc	47	static void __iomem *dist_base;
1e22a8c6 LW	48
	49	/* This function decouple the gic from the prcmu */
	50	int prcmu_gic_decouple(void)
	51	{
	52	u32 val = readl(PRCM_A9_MASK_REQ);
	53
	54	/* Set bit 0 register value to 1 */
	55	writel(val \| PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
	56	PRCM_A9_MASK_REQ);
	57
	58	/* Make sure the register is updated */
	59	readl(PRCM_A9_MASK_REQ);
	60
	61	/* Wait a few cycles for the gic mask completion */
	62	udelay(1);
	63
	64	return 0;
	65	}
	66
	67	/* This function recouple the gic with the prcmu */
	68	int prcmu_gic_recouple(void)
	69	{
	70	u32 val = readl(PRCM_A9_MASK_REQ);
	71
	72	/* Set bit 0 register value to 0 */
	73	writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
	74
	75	return 0;
	76	}
	77
	78	#define PRCMU_GIC_NUMBER_REGS 5
	79
	80	/*
	81	* This function checks if there are pending irq on the gic. It only
	82	* makes sense if the gic has been decoupled before with the
	83	* db8500_prcmu_gic_decouple function. Disabling an interrupt only
	84	* disables the forwarding of the interrupt to any CPU interface. It
	85	* does not prevent the interrupt from changing state, for example
	86	* becoming pending, or active and pending if it is already
	87	* active. Hence, we have to check the interrupt is pending and is
	88	* active.
	89	*/
	90	bool prcmu_gic_pending_irq(void)
	91	{
	92	u32 pr; /* Pending register */
	93	u32 er; /* Enable register */
1e22a8c6 LW	94	int i;
	95
	96	/* 5 registers. STI & PPI not skipped */
	97	for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
	98
	99	pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
	100	er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
	101
	102	if (pr & er)
	103	return true; /* There is a pending interrupt */
	104	}
	105
	106	return false;
	107	}
	108
	109	/*
	110	* This function checks if there are pending interrupt on the
	111	* prcmu which has been delegated to monitor the irqs with the
	112	* db8500_prcmu_copy_gic_settings function.
	113	*/
	114	bool prcmu_pending_irq(void)
	115	{
	116	u32 it, im;
	117	int i;
	118
	119	for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
	120	it = readl(PRCM_ARMITVAL31TO0 + i * 4);
	121	im = readl(PRCM_ARMITMSK31TO0 + i * 4);
	122	if (it & im)
	123	return true; /* There is a pending interrupt */
	124	}
	125
	126	return false;
	127	}
	128
	129	/*
	130	* This function checks if the specified cpu is in in WFI. It's usage
	131	* makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
	132	* function. Of course passing smp_processor_id() to this function will
	133	* always return false...
	134	*/
	135	bool prcmu_is_cpu_in_wfi(int cpu)
	136	{
f0e8faa7 AB	137	return readl(PRCM_ARM_WFI_STANDBY) &
f0e8faa7 AB	138	(cpu ? PRCM_ARM_WFI_STANDBY_WFI1 : PRCM_ARM_WFI_STANDBY_WFI0);
1e22a8c6 LW	139	}
	140
	141	/*
	142	* This function copies the gic SPI settings to the prcmu in order to
	143	* monitor them and abort/finish the retention/off sequence or state.
	144	*/
	145	int prcmu_copy_gic_settings(void)
	146	{
	147	u32 er; /* Enable register */
1e22a8c6 LW	148	int i;
	149
	150	/* We skip the STI and PPI */
	151	for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
	152	er = readl_relaxed(dist_base +
	153	GIC_DIST_ENABLE_SET + (i + 1) * 4);
	154	writel(er, PRCM_ARMITMSK31TO0 + i * 4);
	155	}
	156
	157	return 0;
	158	}
	159
ead9e293 UH	160	#ifdef CONFIG_SUSPEND
	161	static int ux500_suspend_enter(suspend_state_t state)
	162	{
	163	cpu_do_idle();
	164	return 0;
	165	}
	166
	167	static int ux500_suspend_valid(suspend_state_t state)
	168	{
	169	return state == PM_SUSPEND_MEM \|\| state == PM_SUSPEND_STANDBY;
	170	}
	171
	172	static const struct platform_suspend_ops ux500_suspend_ops = {
	173	.enter = ux500_suspend_enter,
	174	.valid = ux500_suspend_valid,
	175	};
	176	#define UX500_SUSPEND_OPS (&ux500_suspend_ops)
	177	#else
	178	#define UX500_SUSPEND_OPS NULL
	179	#endif
	180
1e22a8c6 LW	181	void __init ux500_pm_init(u32 phy_base, u32 size)
1e22a8c6 LW	182	{
26ef94dc LW	183	struct device_node *np;
26ef94dc LW	184
1e22a8c6 LW	185	prcmu_base = ioremap(phy_base, size);
	186	if (!prcmu_base) {
	187	pr_err("could not remap PRCMU for PM functions\n");
	188	return;
	189	}
26ef94dc LW	190	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
	191	dist_base = of_iomap(np, 0);
	192	of_node_put(np);
	193	if (!dist_base) {
	194	pr_err("could not remap GIC dist base for PM functions\n");
	195	return;
	196	}
	197
1e22a8c6 LW	198	/*
	199	* On watchdog reboot the GIC is in some cases decoupled.
	200	* This will make sure that the GIC is correctly configured.
	201	*/
	202	prcmu_gic_recouple();
ead9e293 UH	203
	204	/* Set up ux500 suspend callbacks. */
	205	suspend_set_ops(UX500_SUSPEND_OPS);
cd931dcf UH	206
	207	/* Initialize ux500 power domains */
	208	ux500_pm_domains_init();
1e22a8c6	209	}