[linux-2.6-block.git] / arch / arm / mach-ux500 / db8500-regs.h

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License terms: GNU General Public License (GPL) version 2
 */

#ifndef __MACH_DB8500_REGS_H
#define __MACH_DB8500_REGS_H

/* Base address and bank offsets for ESRAM */
#define U8500_ESRAM_BASE	0x40000000
#define U8500_ESRAM_BANK_SIZE	0x00020000
#define U8500_ESRAM_BANK0	U8500_ESRAM_BASE
#define U8500_ESRAM_BANK1	(U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE)
#define U8500_ESRAM_BANK2	(U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
#define U8500_ESRAM_BANK3	(U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
#define U8500_ESRAM_BANK4	(U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
/*
 * on V1 DMA uses 4KB for logical parameters position is right after the 64KB
 * reserved for security
 */
#define U8500_ESRAM_DMA_LCPA_OFFSET     0x10000

#define U8500_DMA_LCPA_BASE    (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)

/* This address fulfills the 256k alignment requirement of the lcla base */
#define U8500_DMA_LCLA_BASE	U8500_ESRAM_BANK4

#define U8500_PER3_BASE		0x80000000
#define U8500_STM_BASE		0x80100000
#define U8500_STM_REG_BASE	(U8500_STM_BASE + 0xF000)
#define U8500_PER2_BASE		0x80110000
#define U8500_PER1_BASE		0x80120000
#define U8500_B2R2_BASE		0x80130000
#define U8500_HSEM_BASE		0x80140000
#define U8500_PER4_BASE		0x80150000
#define U8500_TPIU_BASE		0x80190000
#define U8500_ICN_BASE		0x81000000

#define U8500_BOOT_ROM_BASE	0x90000000
/* ASIC ID is at 0xbf4 offset within this region */
#define U8500_ASIC_ID_BASE	0x9001D000

#define U8500_PER6_BASE		0xa03c0000
#define U8500_PER7_BASE		0xa03d0000
#define U8500_PER5_BASE		0xa03e0000

#define U8500_SVA_BASE		0xa0100000
#define U8500_SIA_BASE		0xa0200000

#define U8500_SGA_BASE		0xa0300000
#define U8500_MCDE_BASE		0xa0350000
#define U8500_DMA_BASE		0x801C0000	/* v1 */

#define U8500_SBAG_BASE		0xa0390000

#define U8500_SCU_BASE		0xa0410000
#define U8500_GIC_CPU_BASE	0xa0410100
#define U8500_TWD_BASE		0xa0410600
#define U8500_GIC_DIST_BASE	0xa0411000
#define U8500_L2CC_BASE		0xa0412000

#define U8500_MODEM_I2C		0xb7e02000

#define U8500_GPIO0_BASE	(U8500_PER1_BASE + 0xE000)
#define U8500_GPIO1_BASE	(U8500_PER3_BASE + 0xE000)
#define U8500_GPIO2_BASE	(U8500_PER2_BASE + 0xE000)
#define U8500_GPIO3_BASE	(U8500_PER5_BASE + 0x1E000)

#define U8500_UART0_BASE	(U8500_PER1_BASE + 0x0000)
#define U8500_UART1_BASE	(U8500_PER1_BASE + 0x1000)

/* per6 base addresses */
#define U8500_RNG_BASE		(U8500_PER6_BASE + 0x0000)
#define U8500_HASH0_BASE        (U8500_PER6_BASE + 0x1000)
#define U8500_HASH1_BASE        (U8500_PER6_BASE + 0x2000)
#define U8500_PKA_BASE		(U8500_PER6_BASE + 0x4000)
#define U8500_PKAM_BASE		(U8500_PER6_BASE + 0x5100)
#define U8500_MTU0_BASE		(U8500_PER6_BASE + 0x6000) /* v1 */
#define U8500_MTU1_BASE		(U8500_PER6_BASE + 0x7000) /* v1 */
#define U8500_CR_BASE		(U8500_PER6_BASE + 0x8000) /* v1 */
#define U8500_CRYP0_BASE	(U8500_PER6_BASE + 0xa000)
#define U8500_CRYP1_BASE	(U8500_PER6_BASE + 0xb000)
#define U8500_CLKRST6_BASE	(U8500_PER6_BASE + 0xf000)

/* per5 base addresses */
#define U8500_USBOTG_BASE	(U8500_PER5_BASE + 0x00000)
#define U8500_CLKRST5_BASE	(U8500_PER5_BASE + 0x1f000)

/* per4 base addresses */
#define U8500_BACKUPRAM0_BASE	(U8500_PER4_BASE + 0x00000)
#define U8500_BACKUPRAM1_BASE	(U8500_PER4_BASE + 0x01000)
#define U8500_RTT0_BASE		(U8500_PER4_BASE + 0x02000)
#define U8500_RTT1_BASE		(U8500_PER4_BASE + 0x03000)
#define U8500_RTC_BASE		(U8500_PER4_BASE + 0x04000)
#define U8500_SCR_BASE		(U8500_PER4_BASE + 0x05000)
#define U8500_DMC_BASE		(U8500_PER4_BASE + 0x06000)
#define U8500_PRCMU_BASE	(U8500_PER4_BASE + 0x07000)
#define U9540_DMC1_BASE		(U8500_PER4_BASE + 0x0A000)
#define U8500_PRCMU_TCDM_BASE	(U8500_PER4_BASE + 0x68000)
#define U8500_PRCMU_TCPM_BASE   (U8500_PER4_BASE + 0x60000)
#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)

/* per3 base addresses */
#define U8500_FSMC_BASE		(U8500_PER3_BASE + 0x0000)
#define U8500_SSP0_BASE		(U8500_PER3_BASE + 0x2000)
#define U8500_SSP1_BASE		(U8500_PER3_BASE + 0x3000)
#define U8500_I2C0_BASE		(U8500_PER3_BASE + 0x4000)
#define U8500_SDI2_BASE		(U8500_PER3_BASE + 0x5000)
#define U8500_SKE_BASE		(U8500_PER3_BASE + 0x6000)
#define U8500_UART2_BASE	(U8500_PER3_BASE + 0x7000)
#define U8500_SDI5_BASE		(U8500_PER3_BASE + 0x8000)
#define U8500_CLKRST3_BASE	(U8500_PER3_BASE + 0xf000)

/* per2 base addresses */
#define U8500_I2C3_BASE		(U8500_PER2_BASE + 0x0000)
#define U8500_SPI2_BASE		(U8500_PER2_BASE + 0x1000)
#define U8500_SPI1_BASE		(U8500_PER2_BASE + 0x2000)
#define U8500_PWL_BASE		(U8500_PER2_BASE + 0x3000)
#define U8500_SDI4_BASE		(U8500_PER2_BASE + 0x4000)
#define U8500_MSP2_BASE		(U8500_PER2_BASE + 0x7000)
#define U8500_SDI1_BASE		(U8500_PER2_BASE + 0x8000)
#define U8500_SDI3_BASE		(U8500_PER2_BASE + 0x9000)
#define U8500_SPI0_BASE		(U8500_PER2_BASE + 0xa000)
#define U8500_HSIR_BASE		(U8500_PER2_BASE + 0xb000)
#define U8500_HSIT_BASE		(U8500_PER2_BASE + 0xc000)
#define U8500_CLKRST2_BASE	(U8500_PER2_BASE + 0xf000)

/* per1 base addresses */
#define U8500_I2C1_BASE		(U8500_PER1_BASE + 0x2000)
#define U8500_MSP0_BASE		(U8500_PER1_BASE + 0x3000)
#define U8500_MSP1_BASE		(U8500_PER1_BASE + 0x4000)
#define U8500_MSP3_BASE		(U8500_PER1_BASE + 0x5000)
#define U8500_SDI0_BASE		(U8500_PER1_BASE + 0x6000)
#define U8500_I2C2_BASE		(U8500_PER1_BASE + 0x8000)
#define U8500_SPI3_BASE		(U8500_PER1_BASE + 0x9000)
#define U8500_I2C4_BASE		(U8500_PER1_BASE + 0xa000)
#define U8500_SLIM0_BASE	(U8500_PER1_BASE + 0xb000)
#define U8500_CLKRST1_BASE	(U8500_PER1_BASE + 0xf000)

#define U8500_SHRM_GOP_INTERRUPT_BASE	0xB7C00040

#define U8500_GPIOBANK0_BASE	U8500_GPIO0_BASE
#define U8500_GPIOBANK1_BASE	(U8500_GPIO0_BASE + 0x80)
#define U8500_GPIOBANK2_BASE	U8500_GPIO1_BASE
#define U8500_GPIOBANK3_BASE	(U8500_GPIO1_BASE + 0x80)
#define U8500_GPIOBANK4_BASE	(U8500_GPIO1_BASE + 0x100)
#define U8500_GPIOBANK5_BASE	(U8500_GPIO1_BASE + 0x180)
#define U8500_GPIOBANK6_BASE	U8500_GPIO2_BASE
#define U8500_GPIOBANK7_BASE	(U8500_GPIO2_BASE + 0x80)
#define U8500_GPIOBANK8_BASE	U8500_GPIO3_BASE

#define U8500_MCDE_SIZE		0x1000
#define U8500_DSI_LINK_SIZE	0x1000
#define U8500_DSI_LINK1_BASE	(U8500_MCDE_BASE + U8500_MCDE_SIZE)
#define U8500_DSI_LINK2_BASE	(U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
#define U8500_DSI_LINK3_BASE	(U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
#define U8500_DSI_LINK_COUNT	0x3

/* Modem and APE physical addresses */
#define U8500_MODEM_BASE	0xe000000
#define U8500_APE_BASE		0x6000000

/* SoC identification number information */
#define U8500_BB_UID_BASE      (U8500_BACKUPRAM1_BASE + 0xFC0)

/* Offsets to specific addresses in some IP blocks for DMA */
#define MSP_TX_RX_REG_OFFSET	0
#define CRYP1_RX_REG_OFFSET	0x10
#define CRYP1_TX_REG_OFFSET	0x8
#define HASH1_TX_REG_OFFSET	0x4

/*
 * Macros to get at IO space when running virtually
 * We dont map all the peripherals, let ioremap do
 * this for us. We map only very basic peripherals here.
 */
#define U8500_IO_VIRTUAL	0xf0000000
#define U8500_IO_PHYSICAL	0xa0000000
/* This is where we map in the ROM to check ASIC IDs */
#define UX500_VIRT_ROM		IOMEM(0xf0000000)

/* This macro is used in assembly, so no cast */
#define IO_ADDRESS(x)           \
	(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)

/* typesafe io address */
#define __io_address(n)		IOMEM(IO_ADDRESS(n))

/* Used by some plat-nomadik code */
#define io_p2v(n)		__io_address(n)

#define ARRAY_AND_SIZE(x)	(x), ARRAY_SIZE(x)

#endif
Commit	Line	Data
c9c09572 RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License terms: GNU General Public License (GPL) version 2
	5	*/
	6
	7	#ifndef __MACH_DB8500_REGS_H
	8	#define __MACH_DB8500_REGS_H
	9
7b8ddb06 LW	10	/* Base address and bank offsets for ESRAM */
	11	#define U8500_ESRAM_BASE 0x40000000
	12	#define U8500_ESRAM_BANK_SIZE 0x00020000
	13	#define U8500_ESRAM_BANK0 U8500_ESRAM_BASE
	14	#define U8500_ESRAM_BANK1 (U8500_ESRAM_BASE + U8500_ESRAM_BANK_SIZE)
	15	#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
	16	#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
	17	#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
32647406 LW	18	/*
	19	* on V1 DMA uses 4KB for logical parameters position is right after the 64KB
	20	* reserved for security
	21	*/
	22	#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
	23
	24	#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
7b8ddb06	25
ca2ea4e8 LW	26	/* This address fulfills the 256k alignment requirement of the lcla base */
	27	#define U8500_DMA_LCLA_BASE U8500_ESRAM_BANK4
	28
c9c09572 RV	29	#define U8500_PER3_BASE 0x80000000
	30	#define U8500_STM_BASE 0x80100000
	31	#define U8500_STM_REG_BASE (U8500_STM_BASE + 0xF000)
	32	#define U8500_PER2_BASE 0x80110000
	33	#define U8500_PER1_BASE 0x80120000
	34	#define U8500_B2R2_BASE 0x80130000
	35	#define U8500_HSEM_BASE 0x80140000
	36	#define U8500_PER4_BASE 0x80150000
32647406	37	#define U8500_TPIU_BASE 0x80190000
c9c09572 RV	38	#define U8500_ICN_BASE 0x81000000
	39
	40	#define U8500_BOOT_ROM_BASE 0x90000000
32647406 LW	41	/* ASIC ID is at 0xbf4 offset within this region */
32647406 LW	42	#define U8500_ASIC_ID_BASE 0x9001D000
c9c09572 RV	43
c9c09572 RV	44	#define U8500_PER6_BASE 0xa03c0000
ca2ea4e8	45	#define U8500_PER7_BASE 0xa03d0000
c9c09572	46	#define U8500_PER5_BASE 0xa03e0000
c9c09572 RV	47
	48	#define U8500_SVA_BASE 0xa0100000
	49	#define U8500_SIA_BASE 0xa0200000
	50
	51	#define U8500_SGA_BASE 0xa0300000
	52	#define U8500_MCDE_BASE 0xa0350000
c9c09572 RV	53	#define U8500_DMA_BASE 0x801C0000 /* v1 */
	54
	55	#define U8500_SBAG_BASE 0xa0390000
	56
	57	#define U8500_SCU_BASE 0xa0410000
	58	#define U8500_GIC_CPU_BASE 0xa0410100
	59	#define U8500_TWD_BASE 0xa0410600
	60	#define U8500_GIC_DIST_BASE 0xa0411000
	61	#define U8500_L2CC_BASE 0xa0412000
	62
	63	#define U8500_MODEM_I2C 0xb7e02000
	64
	65	#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
	66	#define U8500_GPIO1_BASE (U8500_PER3_BASE + 0xE000)
	67	#define U8500_GPIO2_BASE (U8500_PER2_BASE + 0xE000)
	68	#define U8500_GPIO3_BASE (U8500_PER5_BASE + 0x1E000)
	69
c9c09572 RV	70	#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
	71	#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
	72
25985edc	73	/* per6 base addresses */
c9c09572	74	#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
32647406 LW	75	#define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000)
	76	#define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000)
	77	#define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000)
	78	#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100)
c9c09572 RV	79	#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
	80	#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
	81	#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
32647406 LW	82	#define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000)
32647406 LW	83	#define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000)
c9c09572 RV	84	#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
c9c09572 RV	85
25985edc	86	/* per5 base addresses */
c9c09572 RV	87	#define U8500_USBOTG_BASE (U8500_PER5_BASE + 0x00000)
	88	#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
	89
25985edc	90	/* per4 base addresses */
c9c09572 RV	91	#define U8500_BACKUPRAM0_BASE (U8500_PER4_BASE + 0x00000)
	92	#define U8500_BACKUPRAM1_BASE (U8500_PER4_BASE + 0x01000)
	93	#define U8500_RTT0_BASE (U8500_PER4_BASE + 0x02000)
	94	#define U8500_RTT1_BASE (U8500_PER4_BASE + 0x03000)
	95	#define U8500_RTC_BASE (U8500_PER4_BASE + 0x04000)
	96	#define U8500_SCR_BASE (U8500_PER4_BASE + 0x05000)
	97	#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
	98	#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
bc71c096	99	#define U9540_DMC1_BASE (U8500_PER4_BASE + 0x0A000)
32647406 LW	100	#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
32647406 LW	101	#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000)
c15def1c LW	102	#define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
c15def1c LW	103	#define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
7ed00af7	104
c9c09572 RV	105	/* per3 base addresses */
	106	#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
	107	#define U8500_SSP0_BASE (U8500_PER3_BASE + 0x2000)
	108	#define U8500_SSP1_BASE (U8500_PER3_BASE + 0x3000)
	109	#define U8500_I2C0_BASE (U8500_PER3_BASE + 0x4000)
	110	#define U8500_SDI2_BASE (U8500_PER3_BASE + 0x5000)
	111	#define U8500_SKE_BASE (U8500_PER3_BASE + 0x6000)
	112	#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
	113	#define U8500_SDI5_BASE (U8500_PER3_BASE + 0x8000)
	114	#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
	115
25985edc	116	/* per2 base addresses */
c9c09572 RV	117	#define U8500_I2C3_BASE (U8500_PER2_BASE + 0x0000)
	118	#define U8500_SPI2_BASE (U8500_PER2_BASE + 0x1000)
	119	#define U8500_SPI1_BASE (U8500_PER2_BASE + 0x2000)
	120	#define U8500_PWL_BASE (U8500_PER2_BASE + 0x3000)
	121	#define U8500_SDI4_BASE (U8500_PER2_BASE + 0x4000)
	122	#define U8500_MSP2_BASE (U8500_PER2_BASE + 0x7000)
	123	#define U8500_SDI1_BASE (U8500_PER2_BASE + 0x8000)
	124	#define U8500_SDI3_BASE (U8500_PER2_BASE + 0x9000)
	125	#define U8500_SPI0_BASE (U8500_PER2_BASE + 0xa000)
	126	#define U8500_HSIR_BASE (U8500_PER2_BASE + 0xb000)
	127	#define U8500_HSIT_BASE (U8500_PER2_BASE + 0xc000)
	128	#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
	129
	130	/* per1 base addresses */
	131	#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
	132	#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
	133	#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
32647406	134	#define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000)
c9c09572 RV	135	#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
	136	#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
	137	#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
	138	#define U8500_I2C4_BASE (U8500_PER1_BASE + 0xa000)
	139	#define U8500_SLIM0_BASE (U8500_PER1_BASE + 0xb000)
	140	#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
	141
	142	#define U8500_SHRM_GOP_INTERRUPT_BASE 0xB7C00040
	143
	144	#define U8500_GPIOBANK0_BASE U8500_GPIO0_BASE
	145	#define U8500_GPIOBANK1_BASE (U8500_GPIO0_BASE + 0x80)
	146	#define U8500_GPIOBANK2_BASE U8500_GPIO1_BASE
	147	#define U8500_GPIOBANK3_BASE (U8500_GPIO1_BASE + 0x80)
	148	#define U8500_GPIOBANK4_BASE (U8500_GPIO1_BASE + 0x100)
	149	#define U8500_GPIOBANK5_BASE (U8500_GPIO1_BASE + 0x180)
	150	#define U8500_GPIOBANK6_BASE U8500_GPIO2_BASE
	151	#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
	152	#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE
	153
32647406 LW	154	#define U8500_MCDE_SIZE 0x1000
	155	#define U8500_DSI_LINK_SIZE 0x1000
	156	#define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE)
	157	#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
	158	#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
	159	#define U8500_DSI_LINK_COUNT 0x3
	160
	161	/* Modem and APE physical addresses */
	162	#define U8500_MODEM_BASE 0xe000000
	163	#define U8500_APE_BASE 0x6000000
	164
eda413c2 LJ	165	/* SoC identification number information */
	166	#define U8500_BB_UID_BASE (U8500_BACKUPRAM1_BASE + 0xFC0)
	167
174e7796 LW	168	/* Offsets to specific addresses in some IP blocks for DMA */
	169	#define MSP_TX_RX_REG_OFFSET 0
	170	#define CRYP1_RX_REG_OFFSET 0x10
	171	#define CRYP1_TX_REG_OFFSET 0x8
	172	#define HASH1_TX_REG_OFFSET 0x4
	173
	174	/*
	175	* Macros to get at IO space when running virtually
	176	* We dont map all the peripherals, let ioremap do
	177	* this for us. We map only very basic peripherals here.
	178	*/
	179	#define U8500_IO_VIRTUAL 0xf0000000
	180	#define U8500_IO_PHYSICAL 0xa0000000
	181	/* This is where we map in the ROM to check ASIC IDs */
080e0435	182	#define UX500_VIRT_ROM IOMEM(0xf0000000)
174e7796 LW	183
	184	/* This macro is used in assembly, so no cast */
	185	#define IO_ADDRESS(x) \
	186	(((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + U8500_IO_VIRTUAL)
	187
	188	/* typesafe io address */
	189	#define __io_address(n) IOMEM(IO_ADDRESS(n))
	190
	191	/* Used by some plat-nomadik code */
	192	#define io_p2v(n) __io_address(n)
	193
	194	#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
	195
c9c09572	196	#endif