[linux-2.6-block.git] / arch / arm / mach-ux500 / clock.c

/*
 *  Copyright (C) 2009 ST-Ericsson
 *  Copyright (C) 2009 STMicroelectronics
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/clkdev.h>

#include <plat/mtu.h>
#include <mach/hardware.h>
#include "clock.h"

#define PRCC_PCKEN		0x00
#define PRCC_PCKDIS		0x04
#define PRCC_KCKEN		0x08
#define PRCC_KCKDIS		0x0C

#define PRCM_YYCLKEN0_MGT_SET	0x510
#define PRCM_YYCLKEN1_MGT_SET	0x514
#define PRCM_YYCLKEN0_MGT_CLR	0x518
#define PRCM_YYCLKEN1_MGT_CLR	0x51C
#define PRCM_YYCLKEN0_MGT_VAL	0x520
#define PRCM_YYCLKEN1_MGT_VAL	0x524

#define PRCM_SVAMMDSPCLK_MGT	0x008
#define PRCM_SIAMMDSPCLK_MGT	0x00C
#define PRCM_SGACLK_MGT		0x014
#define PRCM_UARTCLK_MGT	0x018
#define PRCM_MSP02CLK_MGT	0x01C
#define PRCM_MSP1CLK_MGT	0x288
#define PRCM_I2CCLK_MGT		0x020
#define PRCM_SDMMCCLK_MGT	0x024
#define PRCM_SLIMCLK_MGT	0x028
#define PRCM_PER1CLK_MGT	0x02C
#define PRCM_PER2CLK_MGT	0x030
#define PRCM_PER3CLK_MGT	0x034
#define PRCM_PER5CLK_MGT	0x038
#define PRCM_PER6CLK_MGT	0x03C
#define PRCM_PER7CLK_MGT	0x040
#define PRCM_LCDCLK_MGT		0x044
#define PRCM_BMLCLK_MGT		0x04C
#define PRCM_HSITXCLK_MGT	0x050
#define PRCM_HSIRXCLK_MGT	0x054
#define PRCM_HDMICLK_MGT	0x058
#define PRCM_APEATCLK_MGT	0x05C
#define PRCM_APETRACECLK_MGT	0x060
#define PRCM_MCDECLK_MGT	0x064
#define PRCM_IPI2CCLK_MGT	0x068
#define PRCM_DSIALTCLK_MGT	0x06C
#define PRCM_DMACLK_MGT		0x074
#define PRCM_B2R2CLK_MGT	0x078
#define PRCM_TVCLK_MGT		0x07C
#define PRCM_TCR		0x1C8
#define PRCM_TCR_STOPPED	(1 << 16)
#define PRCM_TCR_DOZE_MODE	(1 << 17)
#define PRCM_UNIPROCLK_MGT	0x278
#define PRCM_SSPCLK_MGT		0x280
#define PRCM_RNGCLK_MGT		0x284
#define PRCM_UICCCLK_MGT	0x27C

#define PRCM_MGT_ENABLE		(1 << 8)

static DEFINE_SPINLOCK(clocks_lock);

static void __clk_enable(struct clk *clk)
{
	if (clk->enabled++ == 0) {
		if (clk->parent_cluster)
			__clk_enable(clk->parent_cluster);

		if (clk->parent_periph)
			__clk_enable(clk->parent_periph);

		if (clk->ops && clk->ops->enable)
			clk->ops->enable(clk);
	}
}

int clk_enable(struct clk *clk)
{
	unsigned long flags;

	spin_lock_irqsave(&clocks_lock, flags);
	__clk_enable(clk);
	spin_unlock_irqrestore(&clocks_lock, flags);

	return 0;
}
EXPORT_SYMBOL(clk_enable);

static void __clk_disable(struct clk *clk)
{
	if (--clk->enabled == 0) {
		if (clk->ops && clk->ops->disable)
			clk->ops->disable(clk);

		if (clk->parent_periph)
			__clk_disable(clk->parent_periph);

		if (clk->parent_cluster)
			__clk_disable(clk->parent_cluster);
	}
}

void clk_disable(struct clk *clk)
{
	unsigned long flags;

	WARN_ON(!clk->enabled);

	spin_lock_irqsave(&clocks_lock, flags);
	__clk_disable(clk);
	spin_unlock_irqrestore(&clocks_lock, flags);
}
EXPORT_SYMBOL(clk_disable);

/*
 * The MTU has a separate, rather complex muxing setup
 * with alternative parents (peripheral cluster or
 * ULP or fixed 32768 Hz) depending on settings
 */
static unsigned long clk_mtu_get_rate(struct clk *clk)
{
	void __iomem *addr = __io_address(UX500_PRCMU_BASE)
		+ PRCM_TCR;
	u32 tcr = readl(addr);
	int mtu = (int) clk->data;
	/*
	 * One of these is selected eventually
	 * TODO: Replace the constant with a reference
	 * to the ULP source once this is modeled.
	 */
	unsigned long clk32k = 32768;
	unsigned long mturate;
	unsigned long retclk;

	/* Get the rate from the parent as a default */
	if (clk->parent_periph)
		mturate = clk_get_rate(clk->parent_periph);
	else if (clk->parent_cluster)
		mturate = clk_get_rate(clk->parent_cluster);
	else
		/* We need to be connected SOMEWHERE */
		BUG();

	/*
	 * Are we in doze mode?
	 * In this mode the parent peripheral or the fixed 32768 Hz
	 * clock is fed into the block.
	 */
	if (!(tcr & PRCM_TCR_DOZE_MODE)) {
		/*
		 * Here we're using the clock input from the APE ULP
		 * clock domain. But first: are the timers stopped?
		 */
		if (tcr & PRCM_TCR_STOPPED) {
			clk32k = 0;
			mturate = 0;
		} else {
			/* Else default mode: 0 and 2.4 MHz */
			clk32k = 0;
			if (cpu_is_u5500())
				/* DB5500 divides by 8 */
				mturate /= 8;
			else if (cpu_is_u8500ed()) {
				/*
				 * This clocking setting must not be used
				 * in the ED chip, it is simply not
				 * connected anywhere!
				 */
				mturate = 0;
				BUG();
			} else
				/*
				 * In this mode the ulp38m4 clock is divided
				 * by a factor 16, on the DB8500 typically
				 * 38400000 / 16 ~ 2.4 MHz.
				 * TODO: Replace the constant with a reference
				 * to the ULP source once this is modeled.
				 */
				mturate = 38400000 / 16;
		}
	}

	/* Return the clock selected for this MTU */
	if (tcr & (1 << mtu))
		retclk = clk32k;
	else
		retclk = mturate;

	pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
	return retclk;
}

unsigned long clk_get_rate(struct clk *clk)
{
	unsigned long rate;

	/*
	 * If there is a custom getrate callback for this clock,
	 * it will take precedence.
	 */
	if (clk->get_rate)
		return clk->get_rate(clk);

	if (clk->ops && clk->ops->get_rate)
		return clk->ops->get_rate(clk);

	rate = clk->rate;
	if (!rate) {
		if (clk->parent_periph)
			rate = clk_get_rate(clk->parent_periph);
		else if (clk->parent_cluster)
			rate = clk_get_rate(clk->parent_cluster);
	}

	return rate;
}
EXPORT_SYMBOL(clk_get_rate);

long clk_round_rate(struct clk *clk, unsigned long rate)
{
	/*TODO*/
	return rate;
}
EXPORT_SYMBOL(clk_round_rate);

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	clk->rate = rate;
	return 0;
}
EXPORT_SYMBOL(clk_set_rate);

static void clk_prcmu_enable(struct clk *clk)
{
	void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
				   + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;

	writel(1 << clk->prcmu_cg_bit, cg_set_reg);
}

static void clk_prcmu_disable(struct clk *clk)
{
	void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
				   + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;

	writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
}

/* ED doesn't have the combined set/clr registers */
static void clk_prcmu_ed_enable(struct clk *clk)
{
	void __iomem *addr = __io_address(U8500_PRCMU_BASE)
			     + clk->prcmu_cg_mgt;

	writel(readl(addr) | PRCM_MGT_ENABLE, addr);
}

static void clk_prcmu_ed_disable(struct clk *clk)
{
	void __iomem *addr = __io_address(U8500_PRCMU_BASE)
			     + clk->prcmu_cg_mgt;

	writel(readl(addr) & ~PRCM_MGT_ENABLE, addr);
}

static struct clkops clk_prcmu_ops = {
	.enable = clk_prcmu_enable,
	.disable = clk_prcmu_disable,
};

static unsigned int clkrst_base[] = {
	[1] = U8500_CLKRST1_BASE,
	[2] = U8500_CLKRST2_BASE,
	[3] = U8500_CLKRST3_BASE,
	[5] = U8500_CLKRST5_BASE,
	[6] = U8500_CLKRST6_BASE,
	[7] = U8500_CLKRST7_BASE_ED,
};

static void clk_prcc_enable(struct clk *clk)
{
	void __iomem *addr = __io_address(clkrst_base[clk->cluster]);

	if (clk->prcc_kernel != -1)
		writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);

	if (clk->prcc_bus != -1)
		writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
}

static void clk_prcc_disable(struct clk *clk)
{
	void __iomem *addr = __io_address(clkrst_base[clk->cluster]);

	if (clk->prcc_bus != -1)
		writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);

	if (clk->prcc_kernel != -1)
		writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
}

static struct clkops clk_prcc_ops = {
	.enable = clk_prcc_enable,
	.disable = clk_prcc_disable,
};

static struct clk clk_32khz = {
	.rate = 32000,
};

/*
 * PRCMU level clock gating
 */

/* Bank 0 */
static DEFINE_PRCMU_CLK(svaclk,		0x0, 2, SVAMMDSPCLK);
static DEFINE_PRCMU_CLK(siaclk,		0x0, 3, SIAMMDSPCLK);
static DEFINE_PRCMU_CLK(sgaclk,		0x0, 4, SGACLK);
static DEFINE_PRCMU_CLK_RATE(uartclk,	0x0, 5, UARTCLK, 38400000);
static DEFINE_PRCMU_CLK(msp02clk,	0x0, 6, MSP02CLK);
static DEFINE_PRCMU_CLK(msp1clk,	0x0, 7, MSP1CLK); /* v1 */
static DEFINE_PRCMU_CLK_RATE(i2cclk,	0x0, 8, I2CCLK, 48000000);
static DEFINE_PRCMU_CLK_RATE(sdmmcclk,	0x0, 9, SDMMCCLK, 50000000);
static DEFINE_PRCMU_CLK(slimclk,	0x0, 10, SLIMCLK);
static DEFINE_PRCMU_CLK(per1clk,	0x0, 11, PER1CLK);
static DEFINE_PRCMU_CLK(per2clk,	0x0, 12, PER2CLK);
static DEFINE_PRCMU_CLK(per3clk,	0x0, 13, PER3CLK);
static DEFINE_PRCMU_CLK(per5clk,	0x0, 14, PER5CLK);
static DEFINE_PRCMU_CLK_RATE(per6clk,	0x0, 15, PER6CLK, 133330000);
static DEFINE_PRCMU_CLK_RATE(per7clk,	0x0, 16, PER7CLK, 100000000);
static DEFINE_PRCMU_CLK(lcdclk,		0x0, 17, LCDCLK);
static DEFINE_PRCMU_CLK(bmlclk,		0x0, 18, BMLCLK);
static DEFINE_PRCMU_CLK(hsitxclk,	0x0, 19, HSITXCLK);
static DEFINE_PRCMU_CLK(hsirxclk,	0x0, 20, HSIRXCLK);
static DEFINE_PRCMU_CLK(hdmiclk,	0x0, 21, HDMICLK);
static DEFINE_PRCMU_CLK(apeatclk,	0x0, 22, APEATCLK);
static DEFINE_PRCMU_CLK(apetraceclk,	0x0, 23, APETRACECLK);
static DEFINE_PRCMU_CLK(mcdeclk,	0x0, 24, MCDECLK);
static DEFINE_PRCMU_CLK(ipi2clk,	0x0, 25, IPI2CCLK);
static DEFINE_PRCMU_CLK(dsialtclk,	0x0, 26, DSIALTCLK); /* v1 */
static DEFINE_PRCMU_CLK(dmaclk,		0x0, 27, DMACLK);
static DEFINE_PRCMU_CLK(b2r2clk,	0x0, 28, B2R2CLK);
static DEFINE_PRCMU_CLK(tvclk,		0x0, 29, TVCLK);
static DEFINE_PRCMU_CLK(uniproclk,	0x0, 30, UNIPROCLK); /* v1 */
static DEFINE_PRCMU_CLK_RATE(sspclk,	0x0, 31, SSPCLK, 48000000); /* v1 */

/* Bank 1 */
static DEFINE_PRCMU_CLK(rngclk,		0x4, 0, RNGCLK); /* v1 */
static DEFINE_PRCMU_CLK(uiccclk,	0x4, 1, UICCCLK); /* v1 */

/*
 * PRCC level clock gating
 * Format: per#, clk, PCKEN bit, KCKEN bit, parent
 */

/* Peripheral Cluster #1 */
static DEFINE_PRCC_CLK(1, i2c4, 	10, 9, &clk_i2cclk);
static DEFINE_PRCC_CLK(1, gpio0,	9, -1, NULL);
static DEFINE_PRCC_CLK(1, slimbus0, 	8,  8, &clk_slimclk);
static DEFINE_PRCC_CLK(1, spi3_ed, 	7,  7, NULL);
static DEFINE_PRCC_CLK(1, spi3_v1, 	7, -1, NULL);
static DEFINE_PRCC_CLK(1, i2c2, 	6,  6, &clk_i2cclk);
static DEFINE_PRCC_CLK(1, sdi0,		5,  5, &clk_sdmmcclk);
static DEFINE_PRCC_CLK(1, msp1_ed, 	4,  4, &clk_msp02clk);
static DEFINE_PRCC_CLK(1, msp1_v1, 	4,  4, &clk_msp1clk);
static DEFINE_PRCC_CLK(1, msp0, 	3,  3, &clk_msp02clk);
static DEFINE_PRCC_CLK(1, i2c1, 	2,  2, &clk_i2cclk);
static DEFINE_PRCC_CLK(1, uart1, 	1,  1, &clk_uartclk);
static DEFINE_PRCC_CLK(1, uart0, 	0,  0, &clk_uartclk);

/* Peripheral Cluster #2 */

static DEFINE_PRCC_CLK(2, gpio1_ed,	12, -1, NULL);
static DEFINE_PRCC_CLK(2, ssitx_ed, 	11, -1, NULL);
static DEFINE_PRCC_CLK(2, ssirx_ed, 	10, -1, NULL);
static DEFINE_PRCC_CLK(2, spi0_ed, 	 9, -1, NULL);
static DEFINE_PRCC_CLK(2, sdi3_ed, 	 8,  6, &clk_sdmmcclk);
static DEFINE_PRCC_CLK(2, sdi1_ed, 	 7,  5, &clk_sdmmcclk);
static DEFINE_PRCC_CLK(2, msp2_ed, 	 6,  4, &clk_msp02clk);
static DEFINE_PRCC_CLK(2, sdi4_ed, 	 4,  2, &clk_sdmmcclk);
static DEFINE_PRCC_CLK(2, pwl_ed,	 3,  1, NULL);
static DEFINE_PRCC_CLK(2, spi1_ed, 	 2, -1, NULL);
static DEFINE_PRCC_CLK(2, spi2_ed, 	 1, -1, NULL);
static DEFINE_PRCC_CLK(2, i2c3_ed, 	 0,  0, &clk_i2cclk);

static DEFINE_PRCC_CLK(2, gpio1_v1,	11, -1, NULL);
static DEFINE_PRCC_CLK(2, ssitx_v1, 	10,  7, NULL);
static DEFINE_PRCC_CLK(2, ssirx_v1, 	 9,  6, NULL);
static DEFINE_PRCC_CLK(2, spi0_v1, 	 8, -1, NULL);
static DEFINE_PRCC_CLK(2, sdi3_v1, 	 7,  5, &clk_sdmmcclk);
static DEFINE_PRCC_CLK(2, sdi1_v1, 	 6,  4, &clk_sdmmcclk);
static DEFINE_PRCC_CLK(2, msp2_v1, 	 5,  3, &clk_msp02clk);
static DEFINE_PRCC_CLK(2, sdi4_v1, 	 4,  2, &clk_sdmmcclk);
static DEFINE_PRCC_CLK(2, pwl_v1,	 3,  1, NULL);
static DEFINE_PRCC_CLK(2, spi1_v1, 	 2, -1, NULL);
static DEFINE_PRCC_CLK(2, spi2_v1, 	 1, -1, NULL);
static DEFINE_PRCC_CLK(2, i2c3_v1, 	 0,  0, &clk_i2cclk);

/* Peripheral Cluster #3 */
static DEFINE_PRCC_CLK(3, gpio2, 	8, -1, NULL);
static DEFINE_PRCC_CLK(3, sdi5, 	7,  7, &clk_sdmmcclk);
static DEFINE_PRCC_CLK(3, uart2, 	6,  6, &clk_uartclk);
static DEFINE_PRCC_CLK(3, ske, 		5,  5, &clk_32khz);
static DEFINE_PRCC_CLK(3, sdi2, 	4,  4, &clk_sdmmcclk);
static DEFINE_PRCC_CLK(3, i2c0, 	3,  3, &clk_i2cclk);
static DEFINE_PRCC_CLK(3, ssp1_ed, 	2,  2, &clk_i2cclk);
static DEFINE_PRCC_CLK(3, ssp0_ed, 	1,  1, &clk_i2cclk);
static DEFINE_PRCC_CLK(3, ssp1_v1, 	2,  2, &clk_sspclk);
static DEFINE_PRCC_CLK(3, ssp0_v1, 	1,  1, &clk_sspclk);
static DEFINE_PRCC_CLK(3, fsmc, 	0, -1, NULL);

/* Peripheral Cluster #4 is in the always on domain */

/* Peripheral Cluster #5 */
static DEFINE_PRCC_CLK(5, gpio3, 	1, -1, NULL);
static DEFINE_PRCC_CLK(5, usb_ed, 	0,  0, &clk_i2cclk);
static DEFINE_PRCC_CLK(5, usb_v1, 	0,  0, NULL);

/* Peripheral Cluster #6 */

/* MTU ID in data */
static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1);
static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0);
static DEFINE_PRCC_CLK(6, cfgreg_v1, 	6,  6, NULL);
static DEFINE_PRCC_CLK(6, dmc_ed, 	6,  6, NULL);
static DEFINE_PRCC_CLK(6, hash1, 	5, -1, NULL);
static DEFINE_PRCC_CLK(6, unipro_v1, 	4,  1, &clk_uniproclk);
static DEFINE_PRCC_CLK(6, cryp1_ed, 	4, -1, NULL);
static DEFINE_PRCC_CLK(6, pka, 		3, -1, NULL);
static DEFINE_PRCC_CLK(6, hash0, 	2, -1, NULL);
static DEFINE_PRCC_CLK(6, cryp0, 	1, -1, NULL);
static DEFINE_PRCC_CLK(6, rng_ed, 	0,  0, &clk_i2cclk);
static DEFINE_PRCC_CLK(6, rng_v1, 	0,  0, &clk_rngclk);

/* Peripheral Cluster #7 */

static DEFINE_PRCC_CLK(7, tzpc0_ed, 	4, -1, NULL);
/* MTU ID in data */
static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1);
static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
static DEFINE_PRCC_CLK(7, wdg_ed, 	1, -1, NULL);
static DEFINE_PRCC_CLK(7, cfgreg_ed, 	0, -1, NULL);

static struct clk clk_dummy_apb_pclk;

static struct clk_lookup u8500_common_clks[] = {
	CLK(dummy_apb_pclk, NULL,	"apb_pclk"),

	/* Peripheral Cluster #1 */
	CLK(gpio0,	"gpio.0",	NULL),
	CLK(gpio0,	"gpio.1",	NULL),
	CLK(slimbus0,	"slimbus0",	NULL),
	CLK(i2c2,	"nmk-i2c.2",	NULL),
	CLK(sdi0,	"sdi0",		NULL),
	CLK(msp0,	"msp0",		NULL),
	CLK(i2c1,	"nmk-i2c.1",	NULL),
	CLK(uart1,	"uart1",	NULL),
	CLK(uart0,	"uart0",	NULL),

	/* Peripheral Cluster #3 */
	CLK(gpio2,	"gpio.2",	NULL),
	CLK(gpio2,	"gpio.3",	NULL),
	CLK(gpio2,	"gpio.4",	NULL),
	CLK(gpio2,	"gpio.5",	NULL),
	CLK(sdi5,	"sdi5",		NULL),
	CLK(uart2,	"uart2",	NULL),
	CLK(ske,	"ske",		NULL),
	CLK(ske,	"nmk-ske-keypad",	NULL),
	CLK(sdi2,	"sdi2",		NULL),
	CLK(i2c0,	"nmk-i2c.0",	NULL),
	CLK(fsmc,	"fsmc",		NULL),

	/* Peripheral Cluster #5 */
	CLK(gpio3,	"gpio.8",	NULL),

	/* Peripheral Cluster #6 */
	CLK(hash1,	"hash1",	NULL),
	CLK(pka,	"pka",		NULL),
	CLK(hash0,	"hash0",	NULL),
	CLK(cryp0,	"cryp0",	NULL),

	/* PRCMU level clock gating */

	/* Bank 0 */
	CLK(svaclk,	"sva",		NULL),
	CLK(siaclk,	"sia",		NULL),
	CLK(sgaclk,	"sga",		NULL),
	CLK(slimclk,	"slim",		NULL),
	CLK(lcdclk,	"lcd",		NULL),
	CLK(bmlclk,	"bml",		NULL),
	CLK(hsitxclk,	"stm-hsi.0",	NULL),
	CLK(hsirxclk,	"stm-hsi.1",	NULL),
	CLK(hdmiclk,	"hdmi",		NULL),
	CLK(apeatclk,	"apeat",	NULL),
	CLK(apetraceclk,	"apetrace",	NULL),
	CLK(mcdeclk,	"mcde",		NULL),
	CLK(ipi2clk,	"ipi2",		NULL),
	CLK(dmaclk,	"dma40.0",	NULL),
	CLK(b2r2clk,	"b2r2",		NULL),
	CLK(tvclk,	"tv",		NULL),
};

static struct clk_lookup u8500_ed_clks[] = {
	/* Peripheral Cluster #1 */
	CLK(spi3_ed,	"spi3",		NULL),
	CLK(msp1_ed,	"msp1",		NULL),

	/* Peripheral Cluster #2 */
	CLK(gpio1_ed,	"gpio.6",	NULL),
	CLK(gpio1_ed,	"gpio.7",	NULL),
	CLK(ssitx_ed,	"ssitx",	NULL),
	CLK(ssirx_ed,	"ssirx",	NULL),
	CLK(spi0_ed,	"spi0",		NULL),
	CLK(sdi3_ed,	"sdi3",		NULL),
	CLK(sdi1_ed,	"sdi1",		NULL),
	CLK(msp2_ed,	"msp2",		NULL),
	CLK(sdi4_ed,	"sdi4",		NULL),
	CLK(pwl_ed,	"pwl",		NULL),
	CLK(spi1_ed,	"spi1",		NULL),
	CLK(spi2_ed,	"spi2",		NULL),
	CLK(i2c3_ed,	"nmk-i2c.3",	NULL),

	/* Peripheral Cluster #3 */
	CLK(ssp1_ed,	"ssp1",		NULL),
	CLK(ssp0_ed,	"ssp0",		NULL),

	/* Peripheral Cluster #5 */
	CLK(usb_ed,	"musb_hdrc.0",	"usb"),

	/* Peripheral Cluster #6 */
	CLK(dmc_ed,	"dmc",		NULL),
	CLK(cryp1_ed,	"cryp1",	NULL),
	CLK(rng_ed,	"rng",		NULL),

	/* Peripheral Cluster #7 */
	CLK(tzpc0_ed,	"tzpc0",	NULL),
	CLK(mtu1_ed,	"mtu1",		NULL),
	CLK(mtu0_ed,	"mtu0",		NULL),
	CLK(wdg_ed,	"wdg",		NULL),
	CLK(cfgreg_ed,	"cfgreg",	NULL),
};

static struct clk_lookup u8500_v1_clks[] = {
	/* Peripheral Cluster #1 */
	CLK(i2c4,	"nmk-i2c.4", 	NULL),
	CLK(spi3_v1,	"spi3",		NULL),
	CLK(msp1_v1,	"msp1",		NULL),

	/* Peripheral Cluster #2 */
	CLK(gpio1_v1,	"gpio.6",	NULL),
	CLK(gpio1_v1,	"gpio.7",	NULL),
	CLK(ssitx_v1,	"ssitx",	NULL),
	CLK(ssirx_v1,	"ssirx",	NULL),
	CLK(spi0_v1,	"spi0",		NULL),
	CLK(sdi3_v1,	"sdi3",		NULL),
	CLK(sdi1_v1,	"sdi1",		NULL),
	CLK(msp2_v1,	"msp2",		NULL),
	CLK(sdi4_v1,	"sdi4",		NULL),
	CLK(pwl_v1,	"pwl",		NULL),
	CLK(spi1_v1,	"spi1",		NULL),
	CLK(spi2_v1,	"spi2",		NULL),
	CLK(i2c3_v1,	"nmk-i2c.3",	NULL),

	/* Peripheral Cluster #3 */
	CLK(ssp1_v1,	"ssp1",		NULL),
	CLK(ssp0_v1,	"ssp0",		NULL),

	/* Peripheral Cluster #5 */
	CLK(usb_v1,	"musb_hdrc.0",	"usb"),

	/* Peripheral Cluster #6 */
	CLK(mtu1_v1,	"mtu1",		NULL),
	CLK(mtu0_v1,	"mtu0",		NULL),
	CLK(cfgreg_v1,	"cfgreg",	NULL),
	CLK(hash1,	"hash1",	NULL),
	CLK(unipro_v1,	"unipro",	NULL),
	CLK(rng_v1,	"rng",		NULL),

	/* PRCMU level clock gating */

	/* Bank 0 */
	CLK(uniproclk,	"uniproclk",	NULL),
	CLK(dsialtclk,	"dsialt",	NULL),

	/* Bank 1 */
	CLK(rngclk,	"rng",		NULL),
	CLK(uiccclk,	"uicc",		NULL),
};

int __init clk_init(void)
{
	if (cpu_is_u8500ed()) {
		clk_prcmu_ops.enable = clk_prcmu_ed_enable;
		clk_prcmu_ops.disable = clk_prcmu_ed_disable;
		clk_per6clk.rate = 100000000;
	} else if (cpu_is_u5500()) {
		/* Clock tree for U5500 not implemented yet */
		clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
		clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
		clk_per6clk.rate = 26000000;
	}

	clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
	if (cpu_is_u8500ed())
		clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
	else
		clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));

	return 0;
}
Commit	Line	Data
c6b503ca SK	1	/*
c6b503ca SK	2	* Copyright (C) 2009 ST-Ericsson
1df20afc	3	* Copyright (C) 2009 STMicroelectronics
c6b503ca SK	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*/
	9	#include <linux/module.h>
	10	#include <linux/kernel.h>
	11	#include <linux/list.h>
	12	#include <linux/errno.h>
	13	#include <linux/err.h>
	14	#include <linux/clk.h>
1df20afc	15	#include <linux/io.h>
6d803ba7	16	#include <linux/clkdev.h>
c6b503ca	17
ba327b1e	18	#include <plat/mtu.h>
1df20afc RV	19	#include <mach/hardware.h>
	20	#include "clock.h"
	21
	22	#define PRCC_PCKEN 0x00
	23	#define PRCC_PCKDIS 0x04
	24	#define PRCC_KCKEN 0x08
	25	#define PRCC_KCKDIS 0x0C
	26
	27	#define PRCM_YYCLKEN0_MGT_SET 0x510
	28	#define PRCM_YYCLKEN1_MGT_SET 0x514
	29	#define PRCM_YYCLKEN0_MGT_CLR 0x518
	30	#define PRCM_YYCLKEN1_MGT_CLR 0x51C
	31	#define PRCM_YYCLKEN0_MGT_VAL 0x520
	32	#define PRCM_YYCLKEN1_MGT_VAL 0x524
	33
	34	#define PRCM_SVAMMDSPCLK_MGT 0x008
	35	#define PRCM_SIAMMDSPCLK_MGT 0x00C
	36	#define PRCM_SGACLK_MGT 0x014
	37	#define PRCM_UARTCLK_MGT 0x018
	38	#define PRCM_MSP02CLK_MGT 0x01C
	39	#define PRCM_MSP1CLK_MGT 0x288
	40	#define PRCM_I2CCLK_MGT 0x020
	41	#define PRCM_SDMMCCLK_MGT 0x024
	42	#define PRCM_SLIMCLK_MGT 0x028
	43	#define PRCM_PER1CLK_MGT 0x02C
	44	#define PRCM_PER2CLK_MGT 0x030
	45	#define PRCM_PER3CLK_MGT 0x034
	46	#define PRCM_PER5CLK_MGT 0x038
	47	#define PRCM_PER6CLK_MGT 0x03C
	48	#define PRCM_PER7CLK_MGT 0x040
	49	#define PRCM_LCDCLK_MGT 0x044
	50	#define PRCM_BMLCLK_MGT 0x04C
	51	#define PRCM_HSITXCLK_MGT 0x050
	52	#define PRCM_HSIRXCLK_MGT 0x054
	53	#define PRCM_HDMICLK_MGT 0x058
	54	#define PRCM_APEATCLK_MGT 0x05C
	55	#define PRCM_APETRACECLK_MGT 0x060
	56	#define PRCM_MCDECLK_MGT 0x064
	57	#define PRCM_IPI2CCLK_MGT 0x068
	58	#define PRCM_DSIALTCLK_MGT 0x06C
	59	#define PRCM_DMACLK_MGT 0x074
	60	#define PRCM_B2R2CLK_MGT 0x078
	61	#define PRCM_TVCLK_MGT 0x07C
ba327b1e LW	62	#define PRCM_TCR 0x1C8
	63	#define PRCM_TCR_STOPPED (1 << 16)
	64	#define PRCM_TCR_DOZE_MODE (1 << 17)
1df20afc RV	65	#define PRCM_UNIPROCLK_MGT 0x278
	66	#define PRCM_SSPCLK_MGT 0x280
	67	#define PRCM_RNGCLK_MGT 0x284
	68	#define PRCM_UICCCLK_MGT 0x27C
	69
	70	#define PRCM_MGT_ENABLE (1 << 8)
	71
	72	static DEFINE_SPINLOCK(clocks_lock);
	73
	74	static void __clk_enable(struct clk *clk)
	75	{
	76	if (clk->enabled++ == 0) {
	77	if (clk->parent_cluster)
	78	__clk_enable(clk->parent_cluster);
	79
	80	if (clk->parent_periph)
	81	__clk_enable(clk->parent_periph);
	82
	83	if (clk->ops && clk->ops->enable)
	84	clk->ops->enable(clk);
	85	}
	86	}
c6b503ca SK	87
	88	int clk_enable(struct clk *clk)
	89	{
1df20afc RV	90	unsigned long flags;
	91
	92	spin_lock_irqsave(&clocks_lock, flags);
	93	__clk_enable(clk);
	94	spin_unlock_irqrestore(&clocks_lock, flags);
	95
c6b503ca SK	96	return 0;
	97	}
	98	EXPORT_SYMBOL(clk_enable);
	99
1df20afc RV	100	static void __clk_disable(struct clk *clk)
	101	{
	102	if (--clk->enabled == 0) {
	103	if (clk->ops && clk->ops->disable)
	104	clk->ops->disable(clk);
	105
	106	if (clk->parent_periph)
	107	__clk_disable(clk->parent_periph);
	108
	109	if (clk->parent_cluster)
	110	__clk_disable(clk->parent_cluster);
	111	}
	112	}
	113
c6b503ca SK	114	void clk_disable(struct clk *clk)
c6b503ca SK	115	{
1df20afc RV	116	unsigned long flags;
	117
	118	WARN_ON(!clk->enabled);
	119
	120	spin_lock_irqsave(&clocks_lock, flags);
	121	__clk_disable(clk);
	122	spin_unlock_irqrestore(&clocks_lock, flags);
c6b503ca SK	123	}
	124	EXPORT_SYMBOL(clk_disable);
	125
ba327b1e LW	126	/*
	127	* The MTU has a separate, rather complex muxing setup
	128	* with alternative parents (peripheral cluster or
	129	* ULP or fixed 32768 Hz) depending on settings
	130	*/
	131	static unsigned long clk_mtu_get_rate(struct clk *clk)
	132	{
d9e38040	133	void __iomem *addr = __io_address(UX500_PRCMU_BASE)
ba327b1e LW	134	+ PRCM_TCR;
	135	u32 tcr = readl(addr);
	136	int mtu = (int) clk->data;
	137	/*
	138	* One of these is selected eventually
	139	* TODO: Replace the constant with a reference
	140	* to the ULP source once this is modeled.
	141	*/
	142	unsigned long clk32k = 32768;
	143	unsigned long mturate;
	144	unsigned long retclk;
	145
	146	/* Get the rate from the parent as a default */
	147	if (clk->parent_periph)
	148	mturate = clk_get_rate(clk->parent_periph);
	149	else if (clk->parent_cluster)
	150	mturate = clk_get_rate(clk->parent_cluster);
	151	else
	152	/* We need to be connected SOMEWHERE */
	153	BUG();
	154
	155	/*
	156	* Are we in doze mode?
	157	* In this mode the parent peripheral or the fixed 32768 Hz
	158	* clock is fed into the block.
	159	*/
	160	if (!(tcr & PRCM_TCR_DOZE_MODE)) {
	161	/*
	162	* Here we're using the clock input from the APE ULP
	163	* clock domain. But first: are the timers stopped?
	164	*/
	165	if (tcr & PRCM_TCR_STOPPED) {
	166	clk32k = 0;
	167	mturate = 0;
	168	} else {
	169	/* Else default mode: 0 and 2.4 MHz */
	170	clk32k = 0;
	171	if (cpu_is_u5500())
	172	/* DB5500 divides by 8 */
	173	mturate /= 8;
	174	else if (cpu_is_u8500ed()) {
	175	/*
	176	* This clocking setting must not be used
	177	* in the ED chip, it is simply not
	178	* connected anywhere!
	179	*/
	180	mturate = 0;
	181	BUG();
	182	} else
	183	/*
	184	* In this mode the ulp38m4 clock is divided
	185	* by a factor 16, on the DB8500 typically
	186	* 38400000 / 16 ~ 2.4 MHz.
	187	* TODO: Replace the constant with a reference
	188	* to the ULP source once this is modeled.
	189	*/
	190	mturate = 38400000 / 16;
	191	}
	192	}
	193
	194	/* Return the clock selected for this MTU */
	195	if (tcr & (1 << mtu))
	196	retclk = clk32k;
	197	else
198	retclk = mturate;
199
200	pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
201	return retclk;
202	}
203
c6b503ca SK	204	unsigned long clk_get_rate(struct clk *clk)
c6b503ca SK	205	{
1df20afc RV	206	unsigned long rate;
1df20afc RV	207
ba327b1e LW	208	/*
	209	* If there is a custom getrate callback for this clock,
	210	* it will take precedence.
	211	*/
	212	if (clk->get_rate)
	213	return clk->get_rate(clk);
	214
1df20afc RV	215	if (clk->ops && clk->ops->get_rate)
	216	return clk->ops->get_rate(clk);
	217
	218	rate = clk->rate;
	219	if (!rate) {
	220	if (clk->parent_periph)
	221	rate = clk_get_rate(clk->parent_periph);
	222	else if (clk->parent_cluster)
	223	rate = clk_get_rate(clk->parent_cluster);
	224	}
	225
	226	return rate;
c6b503ca SK	227	}
	228	EXPORT_SYMBOL(clk_get_rate);
	229
	230	long clk_round_rate(struct clk *clk, unsigned long rate)
	231	{
	232	/TODO/
	233	return rate;
	234	}
	235	EXPORT_SYMBOL(clk_round_rate);
	236
	237	int clk_set_rate(struct clk *clk, unsigned long rate)
	238	{
	239	clk->rate = rate;
	240	return 0;
	241	}
	242	EXPORT_SYMBOL(clk_set_rate);
	243
1df20afc RV	244	static void clk_prcmu_enable(struct clk *clk)
	245	{
	246	void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
	247	+ PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
	248
	249	writel(1 << clk->prcmu_cg_bit, cg_set_reg);
	250	}
	251
	252	static void clk_prcmu_disable(struct clk *clk)
	253	{
	254	void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
	255	+ PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
	256
	257	writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
	258	}
	259
	260	/* ED doesn't have the combined set/clr registers */
	261	static void clk_prcmu_ed_enable(struct clk *clk)
	262	{
	263	void __iomem *addr = __io_address(U8500_PRCMU_BASE)
	264	+ clk->prcmu_cg_mgt;
	265
	266	writel(readl(addr) \| PRCM_MGT_ENABLE, addr);
	267	}
	268
	269	static void clk_prcmu_ed_disable(struct clk *clk)
	270	{
	271	void __iomem *addr = __io_address(U8500_PRCMU_BASE)
	272	+ clk->prcmu_cg_mgt;
	273
	274	writel(readl(addr) & ~PRCM_MGT_ENABLE, addr);
	275	}
	276
	277	static struct clkops clk_prcmu_ops = {
	278	.enable = clk_prcmu_enable,
	279	.disable = clk_prcmu_disable,
c6b503ca SK	280	};
c6b503ca SK	281
1df20afc RV	282	static unsigned int clkrst_base[] = {
	283	[1] = U8500_CLKRST1_BASE,
	284	[2] = U8500_CLKRST2_BASE,
	285	[3] = U8500_CLKRST3_BASE,
	286	[5] = U8500_CLKRST5_BASE,
	287	[6] = U8500_CLKRST6_BASE,
	288	[7] = U8500_CLKRST7_BASE_ED,
c6b503ca SK	289	};
c6b503ca SK	290
1df20afc RV	291	static void clk_prcc_enable(struct clk *clk)
	292	{
	293	void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
	294
	295	if (clk->prcc_kernel != -1)
	296	writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
	297
	298	if (clk->prcc_bus != -1)
	299	writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
	300	}
	301
	302	static void clk_prcc_disable(struct clk *clk)
	303	{
	304	void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
	305
	306	if (clk->prcc_bus != -1)
	307	writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
	308
	309	if (clk->prcc_kernel != -1)
	310	writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
	311	}
	312
	313	static struct clkops clk_prcc_ops = {
	314	.enable = clk_prcc_enable,
	315	.disable = clk_prcc_disable,
	316	};
	317
	318	static struct clk clk_32khz = {
	319	.rate = 32000,
	320	};
	321
	322	/*
	323	* PRCMU level clock gating
	324	*/
	325
	326	/* Bank 0 */
	327	static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK);
	328	static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK);
	329	static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK);
	330	static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000);
	331	static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK);
	332	static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */
	333	static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000);
	334	static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 50000000);
	335	static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK);
	336	static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK);
	337	static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK);
	338	static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK);
	339	static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK);
	340	static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000);
	341	static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000);
	342	static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK);
	343	static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK);
	344	static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK);
	345	static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK);
	346	static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK);
	347	static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK);
	348	static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK);
	349	static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK);
	350	static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK);
	351	static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */
	352	static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK);
	353	static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK);
	354	static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK);
355	static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */
356	static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */
357
358	/* Bank 1 */
359	static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */
360	static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
361
362	/*
363	* PRCC level clock gating
364	* Format: per#, clk, PCKEN bit, KCKEN bit, parent
365	*/
366
367	/* Peripheral Cluster #1 */
368	static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
369	static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
370	static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
371	static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL);
372	static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL);
373	static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk);
374	static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk);
375	static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk);
376	static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk);
377	static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk);
378	static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk);
379	static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk);
380	static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk);
381
382	/* Peripheral Cluster #2 */
383
384	static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL);
385	static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL);
386	static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL);
387	static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL);
388	static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk);
389	static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk);
390	static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk);
391	static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk);
392	static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL);
393	static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL);
394	static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL);
395	static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk);
396
397	static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL);
398	static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL);
399	static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL);
400	static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL);
401	static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk);
402	static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk);
403	static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk);
404	static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk);
405	static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL);
406	static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL);
407	static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL);
408	static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk);
409
410	/* Peripheral Cluster #3 */
411	static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL);
412	static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk);
413	static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk);
414	static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz);
415	static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk);
416	static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk);
417	static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk);
418	static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk);
419	static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk);
420	static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk);
421	static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL);
422
423	/* Peripheral Cluster #4 is in the always on domain */
424
425	/* Peripheral Cluster #5 */
426	static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL);
427	static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk);
428	static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL);
429
430	/* Peripheral Cluster #6 */
431
ba327b1e LW	432	/* MTU ID in data */
	433	static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1);
	434	static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0);
1df20afc RV	435	static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL);
	436	static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL);
	437	static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL);
	438	static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk);
	439	static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL);
	440	static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL);
	441	static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL);
	442	static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL);
	443	static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk);
	444	static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk);
	445
	446	/* Peripheral Cluster #7 */
	447
	448	static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL);
ba327b1e LW	449	/* MTU ID in data */
	450	static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1);
	451	static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
1df20afc RV	452	static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL);
	453	static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL);
	454
3126c7bc RK	455	static struct clk clk_dummy_apb_pclk;
3126c7bc RK	456
1df20afc	457	static struct clk_lookup u8500_common_clks[] = {
3126c7bc RK	458	CLK(dummy_apb_pclk, NULL, "apb_pclk"),
3126c7bc RK	459
1df20afc	460	/* Peripheral Cluster #1 */
af7dc228 RV	461	CLK(gpio0, "gpio.0", NULL),
af7dc228 RV	462	CLK(gpio0, "gpio.1", NULL),
1df20afc RV	463	CLK(slimbus0, "slimbus0", NULL),
	464	CLK(i2c2, "nmk-i2c.2", NULL),
	465	CLK(sdi0, "sdi0", NULL),
	466	CLK(msp0, "msp0", NULL),
	467	CLK(i2c1, "nmk-i2c.1", NULL),
	468	CLK(uart1, "uart1", NULL),
	469	CLK(uart0, "uart0", NULL),
	470
	471	/* Peripheral Cluster #3 */
af7dc228 RV	472	CLK(gpio2, "gpio.2", NULL),
	473	CLK(gpio2, "gpio.3", NULL),
	474	CLK(gpio2, "gpio.4", NULL),
	475	CLK(gpio2, "gpio.5", NULL),
1df20afc RV	476	CLK(sdi5, "sdi5", NULL),
	477	CLK(uart2, "uart2", NULL),
	478	CLK(ske, "ske", NULL),
4c61c845	479	CLK(ske, "nmk-ske-keypad", NULL),
1df20afc RV	480	CLK(sdi2, "sdi2", NULL),
	481	CLK(i2c0, "nmk-i2c.0", NULL),
	482	CLK(fsmc, "fsmc", NULL),
	483
	484	/* Peripheral Cluster #5 */
af7dc228	485	CLK(gpio3, "gpio.8", NULL),
1df20afc RV	486
	487	/* Peripheral Cluster #6 */
	488	CLK(hash1, "hash1", NULL),
	489	CLK(pka, "pka", NULL),
	490	CLK(hash0, "hash0", NULL),
	491	CLK(cryp0, "cryp0", NULL),
	492
	493	/* PRCMU level clock gating */
	494
	495	/* Bank 0 */
	496	CLK(svaclk, "sva", NULL),
	497	CLK(siaclk, "sia", NULL),
	498	CLK(sgaclk, "sga", NULL),
	499	CLK(slimclk, "slim", NULL),
	500	CLK(lcdclk, "lcd", NULL),
	501	CLK(bmlclk, "bml", NULL),
	502	CLK(hsitxclk, "stm-hsi.0", NULL),
	503	CLK(hsirxclk, "stm-hsi.1", NULL),
	504	CLK(hdmiclk, "hdmi", NULL),
	505	CLK(apeatclk, "apeat", NULL),
	506	CLK(apetraceclk, "apetrace", NULL),
	507	CLK(mcdeclk, "mcde", NULL),
	508	CLK(ipi2clk, "ipi2", NULL),
7b8ddb06	509	CLK(dmaclk, "dma40.0", NULL),
1df20afc RV	510	CLK(b2r2clk, "b2r2", NULL),
	511	CLK(tvclk, "tv", NULL),
	512	};
	513
	514	static struct clk_lookup u8500_ed_clks[] = {
	515	/* Peripheral Cluster #1 */
	516	CLK(spi3_ed, "spi3", NULL),
	517	CLK(msp1_ed, "msp1", NULL),
	518
	519	/* Peripheral Cluster #2 */
af7dc228 RV	520	CLK(gpio1_ed, "gpio.6", NULL),
af7dc228 RV	521	CLK(gpio1_ed, "gpio.7", NULL),
1df20afc RV	522	CLK(ssitx_ed, "ssitx", NULL),
	523	CLK(ssirx_ed, "ssirx", NULL),
	524	CLK(spi0_ed, "spi0", NULL),
	525	CLK(sdi3_ed, "sdi3", NULL),
	526	CLK(sdi1_ed, "sdi1", NULL),
	527	CLK(msp2_ed, "msp2", NULL),
	528	CLK(sdi4_ed, "sdi4", NULL),
	529	CLK(pwl_ed, "pwl", NULL),
	530	CLK(spi1_ed, "spi1", NULL),
	531	CLK(spi2_ed, "spi2", NULL),
	532	CLK(i2c3_ed, "nmk-i2c.3", NULL),
	533
	534	/* Peripheral Cluster #3 */
	535	CLK(ssp1_ed, "ssp1", NULL),
	536	CLK(ssp0_ed, "ssp0", NULL),
	537
	538	/* Peripheral Cluster #5 */
	539	CLK(usb_ed, "musb_hdrc.0", "usb"),
	540
	541	/* Peripheral Cluster #6 */
	542	CLK(dmc_ed, "dmc", NULL),
	543	CLK(cryp1_ed, "cryp1", NULL),
	544	CLK(rng_ed, "rng", NULL),
	545
	546	/* Peripheral Cluster #7 */
	547	CLK(tzpc0_ed, "tzpc0", NULL),
	548	CLK(mtu1_ed, "mtu1", NULL),
	549	CLK(mtu0_ed, "mtu0", NULL),
	550	CLK(wdg_ed, "wdg", NULL),
	551	CLK(cfgreg_ed, "cfgreg", NULL),
	552	};
	553
	554	static struct clk_lookup u8500_v1_clks[] = {
	555	/* Peripheral Cluster #1 */
	556	CLK(i2c4, "nmk-i2c.4", NULL),
	557	CLK(spi3_v1, "spi3", NULL),
	558	CLK(msp1_v1, "msp1", NULL),
	559
	560	/* Peripheral Cluster #2 */
af7dc228 RV	561	CLK(gpio1_v1, "gpio.6", NULL),
af7dc228 RV	562	CLK(gpio1_v1, "gpio.7", NULL),
1df20afc RV	563	CLK(ssitx_v1, "ssitx", NULL),
	564	CLK(ssirx_v1, "ssirx", NULL),
	565	CLK(spi0_v1, "spi0", NULL),
	566	CLK(sdi3_v1, "sdi3", NULL),
	567	CLK(sdi1_v1, "sdi1", NULL),
	568	CLK(msp2_v1, "msp2", NULL),
	569	CLK(sdi4_v1, "sdi4", NULL),
	570	CLK(pwl_v1, "pwl", NULL),
	571	CLK(spi1_v1, "spi1", NULL),
	572	CLK(spi2_v1, "spi2", NULL),
	573	CLK(i2c3_v1, "nmk-i2c.3", NULL),
	574
	575	/* Peripheral Cluster #3 */
	576	CLK(ssp1_v1, "ssp1", NULL),
	577	CLK(ssp0_v1, "ssp0", NULL),
	578
	579	/* Peripheral Cluster #5 */
	580	CLK(usb_v1, "musb_hdrc.0", "usb"),
	581
	582	/* Peripheral Cluster #6 */
	583	CLK(mtu1_v1, "mtu1", NULL),
	584	CLK(mtu0_v1, "mtu0", NULL),
	585	CLK(cfgreg_v1, "cfgreg", NULL),
	586	CLK(hash1, "hash1", NULL),
	587	CLK(unipro_v1, "unipro", NULL),
	588	CLK(rng_v1, "rng", NULL),
	589
	590	/* PRCMU level clock gating */
	591
	592	/* Bank 0 */
	593	CLK(uniproclk, "uniproclk", NULL),
	594	CLK(dsialtclk, "dsialt", NULL),
	595
	596	/* Bank 1 */
	597	CLK(rngclk, "rng", NULL),
	598	CLK(uiccclk, "uicc", NULL),
c6b503ca SK	599	};
c6b503ca SK	600
ba327b1e	601	int __init clk_init(void)
c6b503ca	602	{
1df20afc RV	603	if (cpu_is_u8500ed()) {
	604	clk_prcmu_ops.enable = clk_prcmu_ed_enable;
	605	clk_prcmu_ops.disable = clk_prcmu_ed_disable;
ba327b1e	606	clk_per6clk.rate = 100000000;
591d8dd7 RV	607	} else if (cpu_is_u5500()) {
	608	/* Clock tree for U5500 not implemented yet */
	609	clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
	610	clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
ba327b1e	611	clk_per6clk.rate = 26000000;
1df20afc RV	612	}
	613
	614	clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
	615	if (cpu_is_u8500ed())
	616	clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
	617	else
	618	clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
	619
c6b503ca SK	620	return 0;
c6b503ca SK	621	}