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d9cc6f76 PDS |
1 | /* |
2 | * arch/arm/mach-tegra/tegra30_clocks.c | |
3 | * | |
88e790a4 | 4 | * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. |
d9cc6f76 PDS |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/spinlock.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/clk.h> | |
29 | #include <linux/cpufreq.h> | |
30 | #include <linux/syscore_ops.h> | |
31 | ||
32 | #include <asm/clkdev.h> | |
33 | ||
34 | #include <mach/iomap.h> | |
35 | ||
36 | #include "clock.h" | |
37 | #include "fuse.h" | |
dab403ef | 38 | #include "tegra_cpu_car.h" |
d9cc6f76 PDS |
39 | |
40 | #define USE_PLL_LOCK_BITS 0 | |
41 | ||
42 | #define RST_DEVICES_L 0x004 | |
43 | #define RST_DEVICES_H 0x008 | |
44 | #define RST_DEVICES_U 0x00C | |
45 | #define RST_DEVICES_V 0x358 | |
46 | #define RST_DEVICES_W 0x35C | |
47 | #define RST_DEVICES_SET_L 0x300 | |
48 | #define RST_DEVICES_CLR_L 0x304 | |
49 | #define RST_DEVICES_SET_V 0x430 | |
50 | #define RST_DEVICES_CLR_V 0x434 | |
51 | #define RST_DEVICES_NUM 5 | |
52 | ||
53 | #define CLK_OUT_ENB_L 0x010 | |
54 | #define CLK_OUT_ENB_H 0x014 | |
55 | #define CLK_OUT_ENB_U 0x018 | |
56 | #define CLK_OUT_ENB_V 0x360 | |
57 | #define CLK_OUT_ENB_W 0x364 | |
58 | #define CLK_OUT_ENB_SET_L 0x320 | |
59 | #define CLK_OUT_ENB_CLR_L 0x324 | |
60 | #define CLK_OUT_ENB_SET_V 0x440 | |
61 | #define CLK_OUT_ENB_CLR_V 0x444 | |
62 | #define CLK_OUT_ENB_NUM 5 | |
63 | ||
64 | #define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1) | |
65 | #define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1) | |
66 | ||
67 | #define PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32)) | |
68 | #define PERIPH_CLK_TO_RST_REG(c) \ | |
69 | periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4) | |
70 | #define PERIPH_CLK_TO_RST_SET_REG(c) \ | |
71 | periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8) | |
72 | #define PERIPH_CLK_TO_RST_CLR_REG(c) \ | |
73 | periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8) | |
74 | ||
75 | #define PERIPH_CLK_TO_ENB_REG(c) \ | |
76 | periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4) | |
77 | #define PERIPH_CLK_TO_ENB_SET_REG(c) \ | |
78 | periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8) | |
79 | #define PERIPH_CLK_TO_ENB_CLR_REG(c) \ | |
80 | periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8) | |
81 | ||
82 | #define CLK_MASK_ARM 0x44 | |
83 | #define MISC_CLK_ENB 0x48 | |
84 | ||
85 | #define OSC_CTRL 0x50 | |
86 | #define OSC_CTRL_OSC_FREQ_MASK (0xF<<28) | |
87 | #define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28) | |
88 | #define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28) | |
89 | #define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28) | |
90 | #define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28) | |
91 | #define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28) | |
92 | #define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28) | |
93 | #define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28) | |
94 | #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) | |
95 | ||
96 | #define OSC_CTRL_PLL_REF_DIV_MASK (3<<26) | |
97 | #define OSC_CTRL_PLL_REF_DIV_1 (0<<26) | |
98 | #define OSC_CTRL_PLL_REF_DIV_2 (1<<26) | |
99 | #define OSC_CTRL_PLL_REF_DIV_4 (2<<26) | |
100 | ||
101 | #define OSC_FREQ_DET 0x58 | |
102 | #define OSC_FREQ_DET_TRIG (1<<31) | |
103 | ||
104 | #define OSC_FREQ_DET_STATUS 0x5C | |
105 | #define OSC_FREQ_DET_BUSY (1<<31) | |
106 | #define OSC_FREQ_DET_CNT_MASK 0xFFFF | |
107 | ||
108 | #define PERIPH_CLK_SOURCE_I2S1 0x100 | |
109 | #define PERIPH_CLK_SOURCE_EMC 0x19c | |
110 | #define PERIPH_CLK_SOURCE_OSC 0x1fc | |
111 | #define PERIPH_CLK_SOURCE_NUM1 \ | |
112 | ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4) | |
113 | ||
114 | #define PERIPH_CLK_SOURCE_G3D2 0x3b0 | |
115 | #define PERIPH_CLK_SOURCE_SE 0x42c | |
116 | #define PERIPH_CLK_SOURCE_NUM2 \ | |
117 | ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1) | |
118 | ||
119 | #define AUDIO_DLY_CLK 0x49c | |
120 | #define AUDIO_SYNC_CLK_SPDIF 0x4b4 | |
121 | #define PERIPH_CLK_SOURCE_NUM3 \ | |
122 | ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1) | |
123 | ||
124 | #define PERIPH_CLK_SOURCE_NUM (PERIPH_CLK_SOURCE_NUM1 + \ | |
125 | PERIPH_CLK_SOURCE_NUM2 + \ | |
126 | PERIPH_CLK_SOURCE_NUM3) | |
127 | ||
128 | #define CPU_SOFTRST_CTRL 0x380 | |
129 | ||
130 | #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF | |
131 | #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF | |
132 | #define PERIPH_CLK_SOURCE_DIV_SHIFT 0 | |
133 | #define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8 | |
134 | #define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50 | |
135 | #define PERIPH_CLK_UART_DIV_ENB (1<<24) | |
136 | #define PERIPH_CLK_VI_SEL_EX_SHIFT 24 | |
137 | #define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT) | |
138 | #define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8) | |
139 | #define PERIPH_CLK_DTV_POLARITY_INV (1<<25) | |
140 | ||
141 | #define AUDIO_SYNC_SOURCE_MASK 0x0F | |
142 | #define AUDIO_SYNC_DISABLE_BIT 0x10 | |
143 | #define AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4) | |
144 | ||
145 | #define PLL_BASE 0x0 | |
146 | #define PLL_BASE_BYPASS (1<<31) | |
147 | #define PLL_BASE_ENABLE (1<<30) | |
148 | #define PLL_BASE_REF_ENABLE (1<<29) | |
149 | #define PLL_BASE_OVERRIDE (1<<28) | |
150 | #define PLL_BASE_LOCK (1<<27) | |
151 | #define PLL_BASE_DIVP_MASK (0x7<<20) | |
152 | #define PLL_BASE_DIVP_SHIFT 20 | |
153 | #define PLL_BASE_DIVN_MASK (0x3FF<<8) | |
154 | #define PLL_BASE_DIVN_SHIFT 8 | |
155 | #define PLL_BASE_DIVM_MASK (0x1F) | |
156 | #define PLL_BASE_DIVM_SHIFT 0 | |
157 | ||
158 | #define PLL_OUT_RATIO_MASK (0xFF<<8) | |
159 | #define PLL_OUT_RATIO_SHIFT 8 | |
160 | #define PLL_OUT_OVERRIDE (1<<2) | |
161 | #define PLL_OUT_CLKEN (1<<1) | |
162 | #define PLL_OUT_RESET_DISABLE (1<<0) | |
163 | ||
164 | #define PLL_MISC(c) \ | |
165 | (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) | |
166 | #define PLL_MISC_LOCK_ENABLE(c) \ | |
167 | (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18)) | |
168 | ||
169 | #define PLL_MISC_DCCON_SHIFT 20 | |
170 | #define PLL_MISC_CPCON_SHIFT 8 | |
171 | #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT) | |
172 | #define PLL_MISC_LFCON_SHIFT 4 | |
173 | #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT) | |
174 | #define PLL_MISC_VCOCON_SHIFT 0 | |
175 | #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT) | |
176 | #define PLLD_MISC_CLKENABLE (1<<30) | |
177 | ||
178 | #define PLLU_BASE_POST_DIV (1<<20) | |
179 | ||
180 | #define PLLD_BASE_DSIB_MUX_SHIFT 25 | |
181 | #define PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT) | |
182 | #define PLLD_BASE_CSI_CLKENABLE (1<<26) | |
183 | #define PLLD_MISC_DSI_CLKENABLE (1<<30) | |
184 | #define PLLD_MISC_DIV_RST (1<<23) | |
185 | #define PLLD_MISC_DCCON_SHIFT 12 | |
186 | ||
187 | #define PLLDU_LFCON_SET_DIVN 600 | |
188 | ||
189 | /* FIXME: OUT_OF_TABLE_CPCON per pll */ | |
190 | #define OUT_OF_TABLE_CPCON 0x8 | |
191 | ||
192 | #define SUPER_CLK_MUX 0x00 | |
193 | #define SUPER_STATE_SHIFT 28 | |
194 | #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT) | |
195 | #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT) | |
196 | #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT) | |
197 | #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT) | |
198 | #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT) | |
199 | #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT) | |
200 | #define SUPER_LP_DIV2_BYPASS (0x1 << 16) | |
201 | #define SUPER_SOURCE_MASK 0xF | |
202 | #define SUPER_FIQ_SOURCE_SHIFT 12 | |
203 | #define SUPER_IRQ_SOURCE_SHIFT 8 | |
204 | #define SUPER_RUN_SOURCE_SHIFT 4 | |
205 | #define SUPER_IDLE_SOURCE_SHIFT 0 | |
206 | ||
207 | #define SUPER_CLK_DIVIDER 0x04 | |
208 | #define SUPER_CLOCK_DIV_U71_SHIFT 16 | |
209 | #define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT) | |
210 | /* guarantees safe cpu backup */ | |
211 | #define SUPER_CLOCK_DIV_U71_MIN 0x2 | |
212 | ||
213 | #define BUS_CLK_DISABLE (1<<3) | |
214 | #define BUS_CLK_DIV_MASK 0x3 | |
215 | ||
216 | #define PMC_CTRL 0x0 | |
217 | #define PMC_CTRL_BLINK_ENB (1 << 7) | |
218 | ||
219 | #define PMC_DPD_PADS_ORIDE 0x1c | |
220 | #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20) | |
221 | ||
222 | #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0 | |
223 | #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff | |
224 | #define PMC_BLINK_TIMER_ENB (1 << 15) | |
225 | #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16 | |
226 | #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff | |
227 | ||
228 | #define PMC_PLLP_WB0_OVERRIDE 0xf8 | |
229 | #define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12) | |
230 | ||
231 | #define UTMIP_PLL_CFG2 0x488 | |
232 | #define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6) | |
233 | #define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18) | |
234 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) | |
235 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) | |
236 | #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4) | |
237 | ||
238 | #define UTMIP_PLL_CFG1 0x484 | |
239 | #define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) | |
240 | #define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0) | |
241 | #define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14) | |
242 | #define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12) | |
243 | #define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16) | |
244 | ||
245 | #define PLLE_BASE_CML_ENABLE (1<<31) | |
246 | #define PLLE_BASE_ENABLE (1<<30) | |
247 | #define PLLE_BASE_DIVCML_SHIFT 24 | |
248 | #define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT) | |
249 | #define PLLE_BASE_DIVP_SHIFT 16 | |
250 | #define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT) | |
251 | #define PLLE_BASE_DIVN_SHIFT 8 | |
252 | #define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT) | |
253 | #define PLLE_BASE_DIVM_SHIFT 0 | |
254 | #define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT) | |
255 | #define PLLE_BASE_DIV_MASK \ | |
256 | (PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \ | |
257 | PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK) | |
258 | #define PLLE_BASE_DIV(m, n, p, cml) \ | |
259 | (((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \ | |
260 | ((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT)) | |
261 | ||
262 | #define PLLE_MISC_SETUP_BASE_SHIFT 16 | |
263 | #define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT) | |
264 | #define PLLE_MISC_READY (1<<15) | |
265 | #define PLLE_MISC_LOCK (1<<11) | |
266 | #define PLLE_MISC_LOCK_ENABLE (1<<9) | |
267 | #define PLLE_MISC_SETUP_EX_SHIFT 2 | |
268 | #define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT) | |
269 | #define PLLE_MISC_SETUP_MASK \ | |
270 | (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK) | |
271 | #define PLLE_MISC_SETUP_VALUE \ | |
272 | ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT)) | |
273 | ||
274 | #define PLLE_SS_CTRL 0x68 | |
275 | #define PLLE_SS_INCINTRV_SHIFT 24 | |
276 | #define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT) | |
277 | #define PLLE_SS_INC_SHIFT 16 | |
278 | #define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT) | |
279 | #define PLLE_SS_MAX_SHIFT 0 | |
280 | #define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT) | |
281 | #define PLLE_SS_COEFFICIENTS_MASK \ | |
282 | (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK) | |
283 | #define PLLE_SS_COEFFICIENTS_12MHZ \ | |
284 | ((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \ | |
285 | (0x24<<PLLE_SS_MAX_SHIFT)) | |
286 | #define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10)) | |
287 | ||
288 | #define PLLE_AUX 0x48c | |
289 | #define PLLE_AUX_PLLP_SEL (1<<2) | |
290 | #define PLLE_AUX_CML_SATA_ENABLE (1<<1) | |
291 | #define PLLE_AUX_CML_PCIE_ENABLE (1<<0) | |
292 | ||
293 | #define PMC_SATA_PWRGT 0x1ac | |
294 | #define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5) | |
295 | #define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4) | |
296 | ||
297 | #define ROUND_DIVIDER_UP 0 | |
298 | #define ROUND_DIVIDER_DOWN 1 | |
299 | ||
300 | /* FIXME: recommended safety delay after lock is detected */ | |
301 | #define PLL_POST_LOCK_DELAY 100 | |
302 | ||
dab403ef JL |
303 | /* Tegra CPU clock and reset control regs */ |
304 | #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c | |
305 | #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340 | |
306 | #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344 | |
307 | #define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c | |
308 | #define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 | |
309 | ||
310 | #define CPU_CLOCK(cpu) (0x1 << (8 + cpu)) | |
311 | #define CPU_RESET(cpu) (0x1111ul << (cpu)) | |
312 | ||
d9cc6f76 PDS |
313 | /** |
314 | * Structure defining the fields for USB UTMI clocks Parameters. | |
315 | */ | |
316 | struct utmi_clk_param { | |
317 | /* Oscillator Frequency in KHz */ | |
318 | u32 osc_frequency; | |
319 | /* UTMIP PLL Enable Delay Count */ | |
320 | u8 enable_delay_count; | |
321 | /* UTMIP PLL Stable count */ | |
322 | u8 stable_count; | |
323 | /* UTMIP PLL Active delay count */ | |
324 | u8 active_delay_count; | |
325 | /* UTMIP PLL Xtal frequency count */ | |
326 | u8 xtal_freq_count; | |
327 | }; | |
328 | ||
329 | static const struct utmi_clk_param utmi_parameters[] = { | |
330 | { | |
331 | .osc_frequency = 13000000, | |
332 | .enable_delay_count = 0x02, | |
333 | .stable_count = 0x33, | |
334 | .active_delay_count = 0x05, | |
335 | .xtal_freq_count = 0x7F | |
336 | }, | |
337 | { | |
338 | .osc_frequency = 19200000, | |
339 | .enable_delay_count = 0x03, | |
340 | .stable_count = 0x4B, | |
341 | .active_delay_count = 0x06, | |
342 | .xtal_freq_count = 0xBB}, | |
343 | { | |
344 | .osc_frequency = 12000000, | |
345 | .enable_delay_count = 0x02, | |
346 | .stable_count = 0x2F, | |
347 | .active_delay_count = 0x04, | |
348 | .xtal_freq_count = 0x76 | |
349 | }, | |
350 | { | |
351 | .osc_frequency = 26000000, | |
352 | .enable_delay_count = 0x04, | |
353 | .stable_count = 0x66, | |
354 | .active_delay_count = 0x09, | |
355 | .xtal_freq_count = 0xFE | |
356 | }, | |
357 | { | |
358 | .osc_frequency = 16800000, | |
359 | .enable_delay_count = 0x03, | |
360 | .stable_count = 0x41, | |
361 | .active_delay_count = 0x0A, | |
362 | .xtal_freq_count = 0xA4 | |
363 | }, | |
364 | }; | |
365 | ||
366 | static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); | |
367 | static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); | |
368 | static void __iomem *misc_gp_hidrev_base = IO_ADDRESS(TEGRA_APB_MISC_BASE); | |
369 | ||
370 | #define MISC_GP_HIDREV 0x804 | |
371 | ||
372 | /* | |
373 | * Some peripheral clocks share an enable bit, so refcount the enable bits | |
374 | * in registers CLK_ENABLE_L, ... CLK_ENABLE_W | |
375 | */ | |
376 | static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32]; | |
377 | ||
378 | #define clk_writel(value, reg) \ | |
fa67ccb6 | 379 | __raw_writel(value, reg_clk_base + (reg)) |
d9cc6f76 | 380 | #define clk_readl(reg) \ |
fa67ccb6 | 381 | __raw_readl(reg_clk_base + (reg)) |
d9cc6f76 | 382 | #define pmc_writel(value, reg) \ |
fa67ccb6 | 383 | __raw_writel(value, reg_pmc_base + (reg)) |
d9cc6f76 | 384 | #define pmc_readl(reg) \ |
fa67ccb6 | 385 | __raw_readl(reg_pmc_base + (reg)) |
d9cc6f76 | 386 | #define chipid_readl() \ |
fa67ccb6 | 387 | __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV) |
d9cc6f76 PDS |
388 | |
389 | #define clk_writel_delay(value, reg) \ | |
390 | do { \ | |
fa67ccb6 | 391 | __raw_writel((value), reg_clk_base + (reg)); \ |
d9cc6f76 PDS |
392 | udelay(2); \ |
393 | } while (0) | |
394 | ||
92fe58f0 | 395 | static inline int clk_set_div(struct clk_tegra *c, u32 n) |
d9cc6f76 | 396 | { |
92fe58f0 PG |
397 | struct clk *clk = c->hw.clk; |
398 | ||
399 | return clk_set_rate(clk, | |
400 | (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n); | |
d9cc6f76 PDS |
401 | } |
402 | ||
403 | static inline u32 periph_clk_to_reg( | |
92fe58f0 | 404 | struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs) |
d9cc6f76 PDS |
405 | { |
406 | u32 reg = c->u.periph.clk_num / 32; | |
407 | BUG_ON(reg >= RST_DEVICES_NUM); | |
408 | if (reg < 3) | |
409 | reg = reg_L + (reg * offs); | |
410 | else | |
411 | reg = reg_V + ((reg - 3) * offs); | |
412 | return reg; | |
413 | } | |
414 | ||
415 | static unsigned long clk_measure_input_freq(void) | |
416 | { | |
417 | u32 clock_autodetect; | |
418 | clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); | |
419 | do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY); | |
420 | clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS); | |
421 | if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) { | |
422 | return 12000000; | |
423 | } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) { | |
424 | return 13000000; | |
425 | } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) { | |
426 | return 19200000; | |
427 | } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) { | |
428 | return 26000000; | |
429 | } else if (clock_autodetect >= 1025 - 3 && clock_autodetect <= 1025 + 3) { | |
430 | return 16800000; | |
431 | } else if (clock_autodetect >= 2344 - 3 && clock_autodetect <= 2344 + 3) { | |
432 | return 38400000; | |
433 | } else if (clock_autodetect >= 2928 - 3 && clock_autodetect <= 2928 + 3) { | |
434 | return 48000000; | |
435 | } else { | |
436 | pr_err("%s: Unexpected clock autodetect value %d", __func__, | |
437 | clock_autodetect); | |
438 | BUG(); | |
439 | return 0; | |
440 | } | |
441 | } | |
442 | ||
443 | static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate, | |
444 | u32 flags, u32 round_mode) | |
445 | { | |
446 | s64 divider_u71 = parent_rate; | |
447 | if (!rate) | |
448 | return -EINVAL; | |
449 | ||
450 | if (!(flags & DIV_U71_INT)) | |
451 | divider_u71 *= 2; | |
452 | if (round_mode == ROUND_DIVIDER_UP) | |
453 | divider_u71 += rate - 1; | |
454 | do_div(divider_u71, rate); | |
455 | if (flags & DIV_U71_INT) | |
456 | divider_u71 *= 2; | |
457 | ||
458 | if (divider_u71 - 2 < 0) | |
459 | return 0; | |
460 | ||
461 | if (divider_u71 - 2 > 255) | |
462 | return -EINVAL; | |
463 | ||
464 | return divider_u71 - 2; | |
465 | } | |
466 | ||
467 | static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate) | |
468 | { | |
469 | s64 divider_u16; | |
470 | ||
471 | divider_u16 = parent_rate; | |
472 | if (!rate) | |
473 | return -EINVAL; | |
474 | divider_u16 += rate - 1; | |
475 | do_div(divider_u16, rate); | |
476 | ||
477 | if (divider_u16 - 1 < 0) | |
478 | return 0; | |
479 | ||
480 | if (divider_u16 - 1 > 0xFFFF) | |
481 | return -EINVAL; | |
482 | ||
483 | return divider_u16 - 1; | |
484 | } | |
485 | ||
92fe58f0 PG |
486 | static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw, |
487 | unsigned long parent_rate) | |
488 | { | |
489 | return to_clk_tegra(hw)->fixed_rate; | |
490 | } | |
491 | ||
b78c030c | 492 | struct clk_ops tegra30_clk_32k_ops = { |
92fe58f0 PG |
493 | .recalc_rate = tegra30_clk_fixed_recalc_rate, |
494 | }; | |
495 | ||
d9cc6f76 | 496 | /* clk_m functions */ |
92fe58f0 PG |
497 | static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw, |
498 | unsigned long parent_rate) | |
499 | { | |
500 | if (!to_clk_tegra(hw)->fixed_rate) | |
501 | to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq(); | |
502 | return to_clk_tegra(hw)->fixed_rate; | |
503 | } | |
504 | ||
505 | static void tegra30_clk_m_init(struct clk_hw *hw) | |
d9cc6f76 PDS |
506 | { |
507 | u32 osc_ctrl = clk_readl(OSC_CTRL); | |
508 | u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK; | |
509 | u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; | |
510 | ||
92fe58f0 | 511 | switch (to_clk_tegra(hw)->fixed_rate) { |
d9cc6f76 PDS |
512 | case 12000000: |
513 | auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; | |
514 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
515 | break; | |
516 | case 13000000: | |
517 | auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; | |
518 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
519 | break; | |
520 | case 19200000: | |
521 | auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ; | |
522 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
523 | break; | |
524 | case 26000000: | |
525 | auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; | |
526 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
527 | break; | |
528 | case 16800000: | |
529 | auto_clock_control |= OSC_CTRL_OSC_FREQ_16_8MHZ; | |
530 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); | |
531 | break; | |
532 | case 38400000: | |
533 | auto_clock_control |= OSC_CTRL_OSC_FREQ_38_4MHZ; | |
534 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_2); | |
535 | break; | |
536 | case 48000000: | |
537 | auto_clock_control |= OSC_CTRL_OSC_FREQ_48MHZ; | |
538 | BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4); | |
539 | break; | |
540 | default: | |
92fe58f0 PG |
541 | pr_err("%s: Unexpected clock rate %ld", __func__, |
542 | to_clk_tegra(hw)->fixed_rate); | |
d9cc6f76 PDS |
543 | BUG(); |
544 | } | |
545 | clk_writel(auto_clock_control, OSC_CTRL); | |
d9cc6f76 PDS |
546 | } |
547 | ||
92fe58f0 PG |
548 | struct clk_ops tegra30_clk_m_ops = { |
549 | .init = tegra30_clk_m_init, | |
550 | .recalc_rate = tegra30_clk_m_recalc_rate, | |
551 | }; | |
d9cc6f76 | 552 | |
92fe58f0 PG |
553 | static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw, |
554 | unsigned long parent_rate) | |
d9cc6f76 | 555 | { |
92fe58f0 PG |
556 | struct clk_tegra *c = to_clk_tegra(hw); |
557 | u64 rate = parent_rate; | |
d9cc6f76 | 558 | |
92fe58f0 PG |
559 | if (c->mul != 0 && c->div != 0) { |
560 | rate *= c->mul; | |
561 | rate += c->div - 1; /* round up */ | |
562 | do_div(rate, c->div); | |
563 | } | |
d9cc6f76 | 564 | |
92fe58f0 PG |
565 | return rate; |
566 | } | |
d9cc6f76 | 567 | |
88e790a4 | 568 | struct clk_ops tegra_clk_m_div_ops = { |
92fe58f0 | 569 | .recalc_rate = tegra30_clk_m_div_recalc_rate, |
d9cc6f76 PDS |
570 | }; |
571 | ||
572 | /* PLL reference divider functions */ | |
92fe58f0 PG |
573 | static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw, |
574 | unsigned long parent_rate) | |
d9cc6f76 | 575 | { |
92fe58f0 PG |
576 | struct clk_tegra *c = to_clk_tegra(hw); |
577 | unsigned long rate = parent_rate; | |
d9cc6f76 | 578 | u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK; |
d9cc6f76 PDS |
579 | |
580 | switch (pll_ref_div) { | |
581 | case OSC_CTRL_PLL_REF_DIV_1: | |
582 | c->div = 1; | |
583 | break; | |
584 | case OSC_CTRL_PLL_REF_DIV_2: | |
585 | c->div = 2; | |
586 | break; | |
587 | case OSC_CTRL_PLL_REF_DIV_4: | |
588 | c->div = 4; | |
589 | break; | |
590 | default: | |
591 | pr_err("%s: Invalid pll ref divider %d", __func__, pll_ref_div); | |
592 | BUG(); | |
593 | } | |
594 | c->mul = 1; | |
92fe58f0 PG |
595 | |
596 | if (c->mul != 0 && c->div != 0) { | |
597 | rate *= c->mul; | |
598 | rate += c->div - 1; /* round up */ | |
599 | do_div(rate, c->div); | |
600 | } | |
601 | ||
602 | return rate; | |
d9cc6f76 PDS |
603 | } |
604 | ||
88e790a4 | 605 | struct clk_ops tegra_pll_ref_ops = { |
92fe58f0 | 606 | .recalc_rate = tegra30_pll_ref_recalc_rate, |
d9cc6f76 PDS |
607 | }; |
608 | ||
609 | /* super clock functions */ | |
610 | /* "super clocks" on tegra30 have two-stage muxes, fractional 7.1 divider and | |
611 | * clock skipping super divider. We will ignore the clock skipping divider, | |
612 | * since we can't lower the voltage when using the clock skip, but we can if | |
613 | * we lower the PLL frequency. We will use 7.1 divider for CPU super-clock | |
614 | * only when its parent is a fixed rate PLL, since we can't change PLL rate | |
615 | * in this case. | |
616 | */ | |
92fe58f0 | 617 | static void tegra30_super_clk_init(struct clk_hw *hw) |
d9cc6f76 | 618 | { |
92fe58f0 PG |
619 | struct clk_tegra *c = to_clk_tegra(hw); |
620 | struct clk_tegra *p = | |
621 | to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk))); | |
d9cc6f76 | 622 | |
92fe58f0 | 623 | c->state = ON; |
d9cc6f76 PDS |
624 | if (c->flags & DIV_U71) { |
625 | /* Init safe 7.1 divider value (does not affect PLLX path) */ | |
626 | clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT, | |
627 | c->reg + SUPER_CLK_DIVIDER); | |
628 | c->mul = 2; | |
629 | c->div = 2; | |
92fe58f0 | 630 | if (!(p->flags & PLLX)) |
d9cc6f76 PDS |
631 | c->div += SUPER_CLOCK_DIV_U71_MIN; |
632 | } else | |
633 | clk_writel(0, c->reg + SUPER_CLK_DIVIDER); | |
634 | } | |
635 | ||
92fe58f0 | 636 | static u8 tegra30_super_clk_get_parent(struct clk_hw *hw) |
d9cc6f76 | 637 | { |
92fe58f0 PG |
638 | struct clk_tegra *c = to_clk_tegra(hw); |
639 | u32 val; | |
640 | int source; | |
641 | int shift; | |
d9cc6f76 | 642 | |
92fe58f0 PG |
643 | val = clk_readl(c->reg + SUPER_CLK_MUX); |
644 | BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && | |
645 | ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); | |
646 | shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? | |
647 | SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; | |
648 | source = (val >> shift) & SUPER_SOURCE_MASK; | |
649 | if (c->flags & DIV_2) | |
650 | source |= val & SUPER_LP_DIV2_BYPASS; | |
651 | ||
652 | return source; | |
d9cc6f76 PDS |
653 | } |
654 | ||
92fe58f0 | 655 | static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index) |
d9cc6f76 | 656 | { |
92fe58f0 PG |
657 | struct clk_tegra *c = to_clk_tegra(hw); |
658 | struct clk_tegra *p = | |
659 | to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk))); | |
d9cc6f76 | 660 | u32 val; |
d9cc6f76 PDS |
661 | int shift; |
662 | ||
663 | val = clk_readl(c->reg + SUPER_CLK_MUX); | |
664 | BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && | |
665 | ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); | |
666 | shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? | |
667 | SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; | |
d9cc6f76 | 668 | |
92fe58f0 PG |
669 | /* For LP mode super-clock switch between PLLX direct |
670 | and divided-by-2 outputs is allowed only when other | |
671 | than PLLX clock source is current parent */ | |
672 | if ((c->flags & DIV_2) && (p->flags & PLLX) && | |
673 | ((index ^ val) & SUPER_LP_DIV2_BYPASS)) { | |
674 | if (p->flags & PLLX) | |
675 | return -EINVAL; | |
676 | val ^= SUPER_LP_DIV2_BYPASS; | |
677 | clk_writel_delay(val, c->reg); | |
678 | } | |
679 | val &= ~(SUPER_SOURCE_MASK << shift); | |
680 | val |= (index & SUPER_SOURCE_MASK) << shift; | |
d9cc6f76 | 681 | |
92fe58f0 PG |
682 | /* 7.1 divider for CPU super-clock does not affect |
683 | PLLX path */ | |
684 | if (c->flags & DIV_U71) { | |
685 | u32 div = 0; | |
686 | if (!(p->flags & PLLX)) { | |
687 | div = clk_readl(c->reg + | |
688 | SUPER_CLK_DIVIDER); | |
689 | div &= SUPER_CLOCK_DIV_U71_MASK; | |
690 | div >>= SUPER_CLOCK_DIV_U71_SHIFT; | |
d9cc6f76 | 691 | } |
92fe58f0 PG |
692 | c->div = div + 2; |
693 | c->mul = 2; | |
d9cc6f76 | 694 | } |
92fe58f0 PG |
695 | clk_writel_delay(val, c->reg); |
696 | ||
697 | return 0; | |
d9cc6f76 PDS |
698 | } |
699 | ||
700 | /* | |
701 | * Do not use super clocks "skippers", since dividing using a clock skipper | |
702 | * does not allow the voltage to be scaled down. Instead adjust the rate of | |
703 | * the parent clock. This requires that the parent of a super clock have no | |
704 | * other children, otherwise the rate will change underneath the other | |
705 | * children. Special case: if fixed rate PLL is CPU super clock parent the | |
706 | * rate of this PLL can't be changed, and it has many other children. In | |
707 | * this case use 7.1 fractional divider to adjust the super clock rate. | |
708 | */ | |
92fe58f0 PG |
709 | static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
710 | unsigned long parent_rate) | |
d9cc6f76 | 711 | { |
92fe58f0 PG |
712 | struct clk_tegra *c = to_clk_tegra(hw); |
713 | struct clk *parent = __clk_get_parent(hw->clk); | |
714 | struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent)); | |
715 | ||
716 | if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) { | |
717 | int div = clk_div71_get_divider(parent_rate, | |
d9cc6f76 PDS |
718 | rate, c->flags, ROUND_DIVIDER_DOWN); |
719 | div = max(div, SUPER_CLOCK_DIV_U71_MIN); | |
720 | ||
721 | clk_writel(div << SUPER_CLOCK_DIV_U71_SHIFT, | |
722 | c->reg + SUPER_CLK_DIVIDER); | |
723 | c->div = div + 2; | |
724 | c->mul = 2; | |
725 | return 0; | |
726 | } | |
92fe58f0 PG |
727 | return 0; |
728 | } | |
729 | ||
730 | static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw, | |
731 | unsigned long parent_rate) | |
732 | { | |
733 | struct clk_tegra *c = to_clk_tegra(hw); | |
734 | u64 rate = parent_rate; | |
735 | ||
736 | if (c->mul != 0 && c->div != 0) { | |
737 | rate *= c->mul; | |
738 | rate += c->div - 1; /* round up */ | |
739 | do_div(rate, c->div); | |
740 | } | |
741 | ||
742 | return rate; | |
743 | } | |
744 | ||
745 | static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |
746 | unsigned long *prate) | |
747 | { | |
748 | struct clk_tegra *c = to_clk_tegra(hw); | |
749 | struct clk *parent = __clk_get_parent(hw->clk); | |
750 | struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent)); | |
751 | int mul = 2; | |
752 | int div; | |
753 | ||
754 | if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) { | |
755 | div = clk_div71_get_divider(*prate, | |
756 | rate, c->flags, ROUND_DIVIDER_DOWN); | |
757 | div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2; | |
758 | rate = *prate * mul; | |
759 | rate += div - 1; /* round up */ | |
760 | do_div(rate, c->div); | |
761 | ||
762 | return rate; | |
763 | } | |
764 | return *prate; | |
d9cc6f76 PDS |
765 | } |
766 | ||
88e790a4 | 767 | struct clk_ops tegra30_super_ops = { |
92fe58f0 PG |
768 | .init = tegra30_super_clk_init, |
769 | .set_parent = tegra30_super_clk_set_parent, | |
770 | .get_parent = tegra30_super_clk_get_parent, | |
771 | .recalc_rate = tegra30_super_clk_recalc_rate, | |
772 | .round_rate = tegra30_super_clk_round_rate, | |
773 | .set_rate = tegra30_super_clk_set_rate, | |
d9cc6f76 PDS |
774 | }; |
775 | ||
92fe58f0 PG |
776 | static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw, |
777 | unsigned long parent_rate) | |
d9cc6f76 | 778 | { |
92fe58f0 PG |
779 | struct clk_tegra *c = to_clk_tegra(hw); |
780 | u64 rate = parent_rate; | |
781 | ||
782 | if (c->mul != 0 && c->div != 0) { | |
783 | rate *= c->mul; | |
784 | rate += c->div - 1; /* round up */ | |
785 | do_div(rate, c->div); | |
786 | } | |
787 | ||
788 | return rate; | |
d9cc6f76 PDS |
789 | } |
790 | ||
88e790a4 | 791 | struct clk_ops tegra30_twd_ops = { |
92fe58f0 | 792 | .recalc_rate = tegra30_twd_clk_recalc_rate, |
d9cc6f76 PDS |
793 | }; |
794 | ||
795 | /* Blink output functions */ | |
92fe58f0 | 796 | static int tegra30_blink_clk_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 797 | { |
92fe58f0 | 798 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
799 | u32 val; |
800 | ||
801 | val = pmc_readl(PMC_CTRL); | |
802 | c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; | |
92fe58f0 | 803 | return c->state; |
d9cc6f76 PDS |
804 | } |
805 | ||
92fe58f0 | 806 | static int tegra30_blink_clk_enable(struct clk_hw *hw) |
d9cc6f76 PDS |
807 | { |
808 | u32 val; | |
809 | ||
810 | val = pmc_readl(PMC_DPD_PADS_ORIDE); | |
811 | pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); | |
812 | ||
813 | val = pmc_readl(PMC_CTRL); | |
814 | pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL); | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
92fe58f0 | 819 | static void tegra30_blink_clk_disable(struct clk_hw *hw) |
d9cc6f76 PDS |
820 | { |
821 | u32 val; | |
822 | ||
823 | val = pmc_readl(PMC_CTRL); | |
824 | pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL); | |
825 | ||
826 | val = pmc_readl(PMC_DPD_PADS_ORIDE); | |
827 | pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); | |
828 | } | |
829 | ||
92fe58f0 PG |
830 | static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
831 | unsigned long parent_rate) | |
d9cc6f76 | 832 | { |
92fe58f0 PG |
833 | struct clk_tegra *c = to_clk_tegra(hw); |
834 | ||
d9cc6f76 PDS |
835 | if (rate >= parent_rate) { |
836 | c->div = 1; | |
837 | pmc_writel(0, c->reg); | |
838 | } else { | |
839 | unsigned int on_off; | |
840 | u32 val; | |
841 | ||
842 | on_off = DIV_ROUND_UP(parent_rate / 8, rate); | |
843 | c->div = on_off * 8; | |
844 | ||
845 | val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) << | |
846 | PMC_BLINK_TIMER_DATA_ON_SHIFT; | |
847 | on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK; | |
848 | on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT; | |
849 | val |= on_off; | |
850 | val |= PMC_BLINK_TIMER_ENB; | |
851 | pmc_writel(val, c->reg); | |
852 | } | |
853 | ||
854 | return 0; | |
855 | } | |
856 | ||
92fe58f0 PG |
857 | static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw, |
858 | unsigned long parent_rate) | |
859 | { | |
860 | struct clk_tegra *c = to_clk_tegra(hw); | |
861 | u64 rate = parent_rate; | |
862 | u32 val; | |
863 | u32 mul; | |
864 | u32 div; | |
865 | u32 on_off; | |
d9cc6f76 | 866 | |
92fe58f0 PG |
867 | mul = 1; |
868 | val = pmc_readl(c->reg); | |
869 | ||
870 | if (val & PMC_BLINK_TIMER_ENB) { | |
871 | on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) & | |
872 | PMC_BLINK_TIMER_DATA_ON_MASK; | |
873 | val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT; | |
874 | val &= PMC_BLINK_TIMER_DATA_OFF_MASK; | |
875 | on_off += val; | |
876 | /* each tick in the blink timer is 4 32KHz clocks */ | |
877 | div = on_off * 4; | |
878 | } else { | |
879 | div = 1; | |
880 | } | |
881 | ||
882 | if (mul != 0 && div != 0) { | |
883 | rate *= mul; | |
884 | rate += div - 1; /* round up */ | |
885 | do_div(rate, div); | |
886 | } | |
887 | return rate; | |
888 | } | |
889 | ||
890 | static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate, | |
891 | unsigned long *prate) | |
d9cc6f76 | 892 | { |
92fe58f0 PG |
893 | int div; |
894 | int mul; | |
895 | long round_rate = *prate; | |
896 | ||
897 | mul = 1; | |
898 | ||
899 | if (rate >= *prate) { | |
900 | div = 1; | |
901 | } else { | |
902 | div = DIV_ROUND_UP(*prate / 8, rate); | |
903 | div *= 8; | |
d9cc6f76 | 904 | } |
d9cc6f76 | 905 | |
92fe58f0 PG |
906 | round_rate *= mul; |
907 | round_rate += div - 1; | |
908 | do_div(round_rate, div); | |
909 | ||
910 | return round_rate; | |
d9cc6f76 PDS |
911 | } |
912 | ||
92fe58f0 PG |
913 | struct clk_ops tegra30_blink_clk_ops = { |
914 | .is_enabled = tegra30_blink_clk_is_enabled, | |
915 | .enable = tegra30_blink_clk_enable, | |
916 | .disable = tegra30_blink_clk_disable, | |
917 | .recalc_rate = tegra30_blink_clk_recalc_rate, | |
918 | .round_rate = tegra30_blink_clk_round_rate, | |
919 | .set_rate = tegra30_blink_clk_set_rate, | |
920 | }; | |
921 | ||
922 | static void tegra30_utmi_param_configure(struct clk_hw *hw) | |
d9cc6f76 | 923 | { |
92fe58f0 PG |
924 | unsigned long main_rate = |
925 | __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk))); | |
d9cc6f76 PDS |
926 | u32 reg; |
927 | int i; | |
d9cc6f76 PDS |
928 | |
929 | for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { | |
930 | if (main_rate == utmi_parameters[i].osc_frequency) | |
931 | break; | |
932 | } | |
933 | ||
934 | if (i >= ARRAY_SIZE(utmi_parameters)) { | |
935 | pr_err("%s: Unexpected main rate %lu\n", __func__, main_rate); | |
936 | return; | |
937 | } | |
938 | ||
939 | reg = clk_readl(UTMIP_PLL_CFG2); | |
940 | ||
941 | /* Program UTMIP PLL stable and active counts */ | |
942 | /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */ | |
943 | reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); | |
944 | reg |= UTMIP_PLL_CFG2_STABLE_COUNT( | |
945 | utmi_parameters[i].stable_count); | |
946 | ||
947 | reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); | |
948 | ||
949 | reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( | |
950 | utmi_parameters[i].active_delay_count); | |
951 | ||
952 | /* Remove power downs from UTMIP PLL control bits */ | |
953 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; | |
954 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; | |
955 | reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; | |
956 | ||
957 | clk_writel(reg, UTMIP_PLL_CFG2); | |
958 | ||
959 | /* Program UTMIP PLL delay and oscillator frequency counts */ | |
960 | reg = clk_readl(UTMIP_PLL_CFG1); | |
961 | reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); | |
962 | ||
963 | reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( | |
964 | utmi_parameters[i].enable_delay_count); | |
965 | ||
966 | reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); | |
967 | reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( | |
968 | utmi_parameters[i].xtal_freq_count); | |
969 | ||
970 | /* Remove power downs from UTMIP PLL control bits */ | |
971 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; | |
972 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; | |
973 | reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; | |
974 | ||
975 | clk_writel(reg, UTMIP_PLL_CFG1); | |
976 | } | |
977 | ||
92fe58f0 PG |
978 | /* PLL Functions */ |
979 | static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg, | |
980 | u32 lock_bit) | |
981 | { | |
982 | int ret = 0; | |
983 | ||
984 | #if USE_PLL_LOCK_BITS | |
985 | int i; | |
986 | for (i = 0; i < c->u.pll.lock_delay; i++) { | |
987 | if (clk_readl(lock_reg) & lock_bit) { | |
988 | udelay(PLL_POST_LOCK_DELAY); | |
989 | return 0; | |
990 | } | |
991 | udelay(2); /* timeout = 2 * lock time */ | |
992 | } | |
993 | pr_err("Timed out waiting for lock bit on pll %s", | |
994 | __clk_get_name(hw->clk)); | |
995 | ret = -1; | |
996 | #else | |
997 | udelay(c->u.pll.lock_delay); | |
998 | #endif | |
999 | return ret; | |
1000 | } | |
1001 | ||
1002 | static int tegra30_pll_clk_is_enabled(struct clk_hw *hw) | |
d9cc6f76 | 1003 | { |
92fe58f0 | 1004 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1005 | u32 val = clk_readl(c->reg + PLL_BASE); |
1006 | ||
1007 | c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; | |
92fe58f0 PG |
1008 | return c->state; |
1009 | } | |
d9cc6f76 | 1010 | |
92fe58f0 PG |
1011 | static void tegra30_pll_clk_init(struct clk_hw *hw) |
1012 | { | |
1013 | struct clk_tegra *c = to_clk_tegra(hw); | |
d9cc6f76 PDS |
1014 | |
1015 | if (c->flags & PLLU) | |
92fe58f0 | 1016 | tegra30_utmi_param_configure(hw); |
d9cc6f76 PDS |
1017 | } |
1018 | ||
92fe58f0 | 1019 | static int tegra30_pll_clk_enable(struct clk_hw *hw) |
d9cc6f76 | 1020 | { |
92fe58f0 | 1021 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 1022 | u32 val; |
92fe58f0 | 1023 | pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); |
d9cc6f76 PDS |
1024 | |
1025 | #if USE_PLL_LOCK_BITS | |
1026 | val = clk_readl(c->reg + PLL_MISC(c)); | |
1027 | val |= PLL_MISC_LOCK_ENABLE(c); | |
1028 | clk_writel(val, c->reg + PLL_MISC(c)); | |
1029 | #endif | |
1030 | val = clk_readl(c->reg + PLL_BASE); | |
1031 | val &= ~PLL_BASE_BYPASS; | |
1032 | val |= PLL_BASE_ENABLE; | |
1033 | clk_writel(val, c->reg + PLL_BASE); | |
1034 | ||
1035 | if (c->flags & PLLM) { | |
1036 | val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); | |
1037 | val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; | |
1038 | pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); | |
1039 | } | |
1040 | ||
1041 | tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_BASE, PLL_BASE_LOCK); | |
1042 | ||
1043 | return 0; | |
1044 | } | |
1045 | ||
92fe58f0 | 1046 | static void tegra30_pll_clk_disable(struct clk_hw *hw) |
d9cc6f76 | 1047 | { |
92fe58f0 | 1048 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 1049 | u32 val; |
92fe58f0 | 1050 | pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk)); |
d9cc6f76 PDS |
1051 | |
1052 | val = clk_readl(c->reg); | |
1053 | val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); | |
1054 | clk_writel(val, c->reg); | |
1055 | ||
1056 | if (c->flags & PLLM) { | |
1057 | val = pmc_readl(PMC_PLLP_WB0_OVERRIDE); | |
1058 | val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE; | |
1059 | pmc_writel(val, PMC_PLLP_WB0_OVERRIDE); | |
1060 | } | |
1061 | } | |
1062 | ||
92fe58f0 PG |
1063 | static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
1064 | unsigned long parent_rate) | |
d9cc6f76 | 1065 | { |
92fe58f0 | 1066 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1067 | u32 val, p_div, old_base; |
1068 | unsigned long input_rate; | |
1069 | const struct clk_pll_freq_table *sel; | |
1070 | struct clk_pll_freq_table cfg; | |
1071 | ||
d9cc6f76 PDS |
1072 | if (c->flags & PLL_FIXED) { |
1073 | int ret = 0; | |
1074 | if (rate != c->u.pll.fixed_rate) { | |
1075 | pr_err("%s: Can not change %s fixed rate %lu to %lu\n", | |
92fe58f0 PG |
1076 | __func__, __clk_get_name(hw->clk), |
1077 | c->u.pll.fixed_rate, rate); | |
d9cc6f76 PDS |
1078 | ret = -EINVAL; |
1079 | } | |
1080 | return ret; | |
1081 | } | |
1082 | ||
1083 | if (c->flags & PLLM) { | |
92fe58f0 | 1084 | if (rate != __clk_get_rate(hw->clk)) { |
d9cc6f76 | 1085 | pr_err("%s: Can not change memory %s rate in flight\n", |
92fe58f0 | 1086 | __func__, __clk_get_name(hw->clk)); |
d9cc6f76 PDS |
1087 | return -EINVAL; |
1088 | } | |
d9cc6f76 PDS |
1089 | } |
1090 | ||
1091 | p_div = 0; | |
92fe58f0 | 1092 | input_rate = parent_rate; |
d9cc6f76 PDS |
1093 | |
1094 | /* Check if the target rate is tabulated */ | |
1095 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { | |
1096 | if (sel->input_rate == input_rate && sel->output_rate == rate) { | |
1097 | if (c->flags & PLLU) { | |
1098 | BUG_ON(sel->p < 1 || sel->p > 2); | |
1099 | if (sel->p == 1) | |
1100 | p_div = PLLU_BASE_POST_DIV; | |
1101 | } else { | |
1102 | BUG_ON(sel->p < 1); | |
1103 | for (val = sel->p; val > 1; val >>= 1) | |
1104 | p_div++; | |
1105 | p_div <<= PLL_BASE_DIVP_SHIFT; | |
1106 | } | |
1107 | break; | |
1108 | } | |
1109 | } | |
1110 | ||
1111 | /* Configure out-of-table rate */ | |
1112 | if (sel->input_rate == 0) { | |
1113 | unsigned long cfreq; | |
1114 | BUG_ON(c->flags & PLLU); | |
1115 | sel = &cfg; | |
1116 | ||
1117 | switch (input_rate) { | |
1118 | case 12000000: | |
1119 | case 26000000: | |
1120 | cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; | |
1121 | break; | |
1122 | case 13000000: | |
1123 | cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; | |
1124 | break; | |
1125 | case 16800000: | |
1126 | case 19200000: | |
1127 | cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; | |
1128 | break; | |
1129 | default: | |
1130 | pr_err("%s: Unexpected reference rate %lu\n", | |
1131 | __func__, input_rate); | |
1132 | BUG(); | |
1133 | } | |
1134 | ||
1135 | /* Raise VCO to guarantee 0.5% accuracy */ | |
1136 | for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq; | |
1137 | cfg.output_rate <<= 1) | |
1138 | p_div++; | |
1139 | ||
1140 | cfg.p = 0x1 << p_div; | |
1141 | cfg.m = input_rate / cfreq; | |
1142 | cfg.n = cfg.output_rate / cfreq; | |
1143 | cfg.cpcon = OUT_OF_TABLE_CPCON; | |
1144 | ||
1145 | if ((cfg.m > (PLL_BASE_DIVM_MASK >> PLL_BASE_DIVM_SHIFT)) || | |
1146 | (cfg.n > (PLL_BASE_DIVN_MASK >> PLL_BASE_DIVN_SHIFT)) || | |
1147 | (p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) || | |
1148 | (cfg.output_rate > c->u.pll.vco_max)) { | |
1149 | pr_err("%s: Failed to set %s out-of-table rate %lu\n", | |
92fe58f0 | 1150 | __func__, __clk_get_name(hw->clk), rate); |
d9cc6f76 PDS |
1151 | return -EINVAL; |
1152 | } | |
1153 | p_div <<= PLL_BASE_DIVP_SHIFT; | |
1154 | } | |
1155 | ||
1156 | c->mul = sel->n; | |
1157 | c->div = sel->m * sel->p; | |
1158 | ||
1159 | old_base = val = clk_readl(c->reg + PLL_BASE); | |
1160 | val &= ~(PLL_BASE_DIVM_MASK | PLL_BASE_DIVN_MASK | | |
1161 | ((c->flags & PLLU) ? PLLU_BASE_POST_DIV : PLL_BASE_DIVP_MASK)); | |
1162 | val |= (sel->m << PLL_BASE_DIVM_SHIFT) | | |
1163 | (sel->n << PLL_BASE_DIVN_SHIFT) | p_div; | |
1164 | if (val == old_base) | |
1165 | return 0; | |
1166 | ||
1167 | if (c->state == ON) { | |
92fe58f0 | 1168 | tegra30_pll_clk_disable(hw); |
d9cc6f76 PDS |
1169 | val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); |
1170 | } | |
1171 | clk_writel(val, c->reg + PLL_BASE); | |
1172 | ||
1173 | if (c->flags & PLL_HAS_CPCON) { | |
1174 | val = clk_readl(c->reg + PLL_MISC(c)); | |
1175 | val &= ~PLL_MISC_CPCON_MASK; | |
1176 | val |= sel->cpcon << PLL_MISC_CPCON_SHIFT; | |
1177 | if (c->flags & (PLLU | PLLD)) { | |
1178 | val &= ~PLL_MISC_LFCON_MASK; | |
1179 | if (sel->n >= PLLDU_LFCON_SET_DIVN) | |
1180 | val |= 0x1 << PLL_MISC_LFCON_SHIFT; | |
1181 | } else if (c->flags & (PLLX | PLLM)) { | |
1182 | val &= ~(0x1 << PLL_MISC_DCCON_SHIFT); | |
1183 | if (rate >= (c->u.pll.vco_max >> 1)) | |
1184 | val |= 0x1 << PLL_MISC_DCCON_SHIFT; | |
1185 | } | |
1186 | clk_writel(val, c->reg + PLL_MISC(c)); | |
1187 | } | |
1188 | ||
1189 | if (c->state == ON) | |
92fe58f0 | 1190 | tegra30_pll_clk_enable(hw); |
d9cc6f76 | 1191 | |
92fe58f0 | 1192 | c->u.pll.fixed_rate = rate; |
d9cc6f76 | 1193 | |
d9cc6f76 PDS |
1194 | return 0; |
1195 | } | |
1196 | ||
92fe58f0 PG |
1197 | static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
1198 | unsigned long *prate) | |
d9cc6f76 | 1199 | { |
92fe58f0 PG |
1200 | struct clk_tegra *c = to_clk_tegra(hw); |
1201 | unsigned long input_rate = *prate; | |
78662130 | 1202 | u64 output_rate = *prate; |
92fe58f0 PG |
1203 | const struct clk_pll_freq_table *sel; |
1204 | struct clk_pll_freq_table cfg; | |
1205 | int mul; | |
1206 | int div; | |
1207 | u32 p_div; | |
d9cc6f76 PDS |
1208 | u32 val; |
1209 | ||
92fe58f0 PG |
1210 | if (c->flags & PLL_FIXED) |
1211 | return c->u.pll.fixed_rate; | |
d9cc6f76 | 1212 | |
92fe58f0 PG |
1213 | if (c->flags & PLLM) |
1214 | return __clk_get_rate(hw->clk); | |
d9cc6f76 | 1215 | |
92fe58f0 PG |
1216 | p_div = 0; |
1217 | /* Check if the target rate is tabulated */ | |
1218 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { | |
1219 | if (sel->input_rate == input_rate && sel->output_rate == rate) { | |
1220 | if (c->flags & PLLU) { | |
1221 | BUG_ON(sel->p < 1 || sel->p > 2); | |
1222 | if (sel->p == 1) | |
1223 | p_div = PLLU_BASE_POST_DIV; | |
1224 | } else { | |
1225 | BUG_ON(sel->p < 1); | |
1226 | for (val = sel->p; val > 1; val >>= 1) | |
1227 | p_div++; | |
1228 | p_div <<= PLL_BASE_DIVP_SHIFT; | |
1229 | } | |
1230 | break; | |
1231 | } | |
1232 | } | |
d9cc6f76 | 1233 | |
92fe58f0 PG |
1234 | if (sel->input_rate == 0) { |
1235 | unsigned long cfreq; | |
1236 | BUG_ON(c->flags & PLLU); | |
1237 | sel = &cfg; | |
1238 | ||
1239 | switch (input_rate) { | |
1240 | case 12000000: | |
1241 | case 26000000: | |
1242 | cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; | |
1243 | break; | |
1244 | case 13000000: | |
1245 | cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; | |
1246 | break; | |
1247 | case 16800000: | |
1248 | case 19200000: | |
1249 | cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; | |
1250 | break; | |
1251 | default: | |
1252 | pr_err("%s: Unexpected reference rate %lu\n", | |
1253 | __func__, input_rate); | |
1254 | BUG(); | |
1255 | } | |
1256 | ||
1257 | /* Raise VCO to guarantee 0.5% accuracy */ | |
1258 | for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq; | |
1259 | cfg.output_rate <<= 1) | |
1260 | p_div++; | |
1261 | ||
1262 | cfg.p = 0x1 << p_div; | |
1263 | cfg.m = input_rate / cfreq; | |
1264 | cfg.n = cfg.output_rate / cfreq; | |
1265 | } | |
1266 | ||
1267 | mul = sel->n; | |
1268 | div = sel->m * sel->p; | |
1269 | ||
1270 | output_rate *= mul; | |
1271 | output_rate += div - 1; /* round up */ | |
1272 | do_div(output_rate, div); | |
1273 | ||
1274 | return output_rate; | |
1275 | } | |
1276 | ||
1277 | static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw, | |
1278 | unsigned long parent_rate) | |
1279 | { | |
1280 | struct clk_tegra *c = to_clk_tegra(hw); | |
1281 | u64 rate = parent_rate; | |
1282 | u32 val = clk_readl(c->reg + PLL_BASE); | |
1283 | ||
1284 | if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { | |
1285 | const struct clk_pll_freq_table *sel; | |
1286 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { | |
1287 | if (sel->input_rate == parent_rate && | |
1288 | sel->output_rate == c->u.pll.fixed_rate) { | |
1289 | c->mul = sel->n; | |
1290 | c->div = sel->m * sel->p; | |
1291 | break; | |
1292 | } | |
1293 | } | |
1294 | pr_err("Clock %s has unknown fixed frequency\n", | |
1295 | __clk_get_name(hw->clk)); | |
1296 | BUG(); | |
1297 | } else if (val & PLL_BASE_BYPASS) { | |
1298 | c->mul = 1; | |
1299 | c->div = 1; | |
1300 | } else { | |
1301 | c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; | |
1302 | c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; | |
1303 | if (c->flags & PLLU) | |
1304 | c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2; | |
1305 | else | |
1306 | c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >> | |
1307 | PLL_BASE_DIVP_SHIFT)); | |
1308 | } | |
1309 | ||
1310 | if (c->mul != 0 && c->div != 0) { | |
1311 | rate *= c->mul; | |
1312 | rate += c->div - 1; /* round up */ | |
1313 | do_div(rate, c->div); | |
1314 | } | |
1315 | ||
1316 | return rate; | |
1317 | } | |
1318 | ||
1319 | struct clk_ops tegra30_pll_ops = { | |
1320 | .is_enabled = tegra30_pll_clk_is_enabled, | |
1321 | .init = tegra30_pll_clk_init, | |
1322 | .enable = tegra30_pll_clk_enable, | |
1323 | .disable = tegra30_pll_clk_disable, | |
1324 | .recalc_rate = tegra30_pll_recalc_rate, | |
1325 | .round_rate = tegra30_pll_round_rate, | |
1326 | .set_rate = tegra30_pll_clk_set_rate, | |
1327 | }; | |
1328 | ||
1329 | int tegra30_plld_clk_cfg_ex(struct clk_hw *hw, | |
1330 | enum tegra_clk_ex_param p, u32 setting) | |
1331 | { | |
1332 | struct clk_tegra *c = to_clk_tegra(hw); | |
1333 | u32 val, mask, reg; | |
1334 | ||
1335 | switch (p) { | |
1336 | case TEGRA_CLK_PLLD_CSI_OUT_ENB: | |
1337 | mask = PLLD_BASE_CSI_CLKENABLE; | |
1338 | reg = c->reg + PLL_BASE; | |
1339 | break; | |
1340 | case TEGRA_CLK_PLLD_DSI_OUT_ENB: | |
1341 | mask = PLLD_MISC_DSI_CLKENABLE; | |
1342 | reg = c->reg + PLL_MISC(c); | |
1343 | break; | |
1344 | case TEGRA_CLK_PLLD_MIPI_MUX_SEL: | |
1345 | if (!(c->flags & PLL_ALT_MISC_REG)) { | |
1346 | mask = PLLD_BASE_DSIB_MUX_MASK; | |
1347 | reg = c->reg + PLL_BASE; | |
1348 | break; | |
1349 | } | |
1350 | /* fall through - error since PLLD2 does not have MUX_SEL control */ | |
1351 | default: | |
1352 | return -EINVAL; | |
1353 | } | |
1354 | ||
1355 | val = clk_readl(reg); | |
1356 | if (setting) | |
1357 | val |= mask; | |
1358 | else | |
1359 | val &= ~mask; | |
1360 | clk_writel(val, reg); | |
1361 | return 0; | |
1362 | } | |
1363 | ||
1364 | static int tegra30_plle_clk_is_enabled(struct clk_hw *hw) | |
1365 | { | |
1366 | struct clk_tegra *c = to_clk_tegra(hw); | |
1367 | u32 val; | |
1368 | ||
1369 | val = clk_readl(c->reg + PLL_BASE); | |
1370 | c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF; | |
1371 | return c->state; | |
1372 | } | |
1373 | ||
1374 | static void tegra30_plle_clk_disable(struct clk_hw *hw) | |
1375 | { | |
1376 | struct clk_tegra *c = to_clk_tegra(hw); | |
1377 | u32 val; | |
1378 | ||
1379 | val = clk_readl(c->reg + PLL_BASE); | |
1380 | val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); | |
1381 | clk_writel(val, c->reg + PLL_BASE); | |
1382 | } | |
d9cc6f76 | 1383 | |
92fe58f0 | 1384 | static void tegra30_plle_training(struct clk_tegra *c) |
d9cc6f76 PDS |
1385 | { |
1386 | u32 val; | |
1387 | ||
1388 | /* PLLE is already disabled, and setup cleared; | |
1389 | * create falling edge on PLLE IDDQ input */ | |
1390 | val = pmc_readl(PMC_SATA_PWRGT); | |
1391 | val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; | |
1392 | pmc_writel(val, PMC_SATA_PWRGT); | |
1393 | ||
1394 | val = pmc_readl(PMC_SATA_PWRGT); | |
1395 | val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL; | |
1396 | pmc_writel(val, PMC_SATA_PWRGT); | |
1397 | ||
1398 | val = pmc_readl(PMC_SATA_PWRGT); | |
1399 | val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE; | |
1400 | pmc_writel(val, PMC_SATA_PWRGT); | |
1401 | ||
1402 | do { | |
1403 | val = clk_readl(c->reg + PLL_MISC(c)); | |
1404 | } while (!(val & PLLE_MISC_READY)); | |
1405 | } | |
1406 | ||
92fe58f0 | 1407 | static int tegra30_plle_configure(struct clk_hw *hw, bool force_training) |
d9cc6f76 | 1408 | { |
92fe58f0 PG |
1409 | struct clk_tegra *c = to_clk_tegra(hw); |
1410 | struct clk *parent = __clk_get_parent(hw->clk); | |
d9cc6f76 | 1411 | const struct clk_pll_freq_table *sel; |
92fe58f0 PG |
1412 | u32 val; |
1413 | ||
d9cc6f76 | 1414 | unsigned long rate = c->u.pll.fixed_rate; |
92fe58f0 | 1415 | unsigned long input_rate = __clk_get_rate(parent); |
d9cc6f76 PDS |
1416 | |
1417 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { | |
1418 | if (sel->input_rate == input_rate && sel->output_rate == rate) | |
1419 | break; | |
1420 | } | |
1421 | ||
1422 | if (sel->input_rate == 0) | |
1423 | return -ENOSYS; | |
1424 | ||
1425 | /* disable PLLE, clear setup fiels */ | |
92fe58f0 | 1426 | tegra30_plle_clk_disable(hw); |
d9cc6f76 PDS |
1427 | |
1428 | val = clk_readl(c->reg + PLL_MISC(c)); | |
1429 | val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK); | |
1430 | clk_writel(val, c->reg + PLL_MISC(c)); | |
1431 | ||
1432 | /* training */ | |
1433 | val = clk_readl(c->reg + PLL_MISC(c)); | |
1434 | if (force_training || (!(val & PLLE_MISC_READY))) | |
1435 | tegra30_plle_training(c); | |
1436 | ||
1437 | /* configure dividers, setup, disable SS */ | |
1438 | val = clk_readl(c->reg + PLL_BASE); | |
1439 | val &= ~PLLE_BASE_DIV_MASK; | |
1440 | val |= PLLE_BASE_DIV(sel->m, sel->n, sel->p, sel->cpcon); | |
1441 | clk_writel(val, c->reg + PLL_BASE); | |
1442 | c->mul = sel->n; | |
1443 | c->div = sel->m * sel->p; | |
1444 | ||
1445 | val = clk_readl(c->reg + PLL_MISC(c)); | |
1446 | val |= PLLE_MISC_SETUP_VALUE; | |
1447 | val |= PLLE_MISC_LOCK_ENABLE; | |
1448 | clk_writel(val, c->reg + PLL_MISC(c)); | |
1449 | ||
1450 | val = clk_readl(PLLE_SS_CTRL); | |
1451 | val |= PLLE_SS_DISABLE; | |
1452 | clk_writel(val, PLLE_SS_CTRL); | |
1453 | ||
1454 | /* enable and lock PLLE*/ | |
1455 | val = clk_readl(c->reg + PLL_BASE); | |
1456 | val |= (PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE); | |
1457 | clk_writel(val, c->reg + PLL_BASE); | |
1458 | ||
1459 | tegra30_pll_clk_wait_for_lock(c, c->reg + PLL_MISC(c), PLLE_MISC_LOCK); | |
1460 | ||
1461 | return 0; | |
1462 | } | |
1463 | ||
92fe58f0 | 1464 | static int tegra30_plle_clk_enable(struct clk_hw *hw) |
d9cc6f76 | 1465 | { |
92fe58f0 PG |
1466 | struct clk_tegra *c = to_clk_tegra(hw); |
1467 | ||
1468 | return tegra30_plle_configure(hw, !c->set); | |
1469 | } | |
1470 | ||
1471 | static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw, | |
1472 | unsigned long parent_rate) | |
1473 | { | |
1474 | struct clk_tegra *c = to_clk_tegra(hw); | |
1475 | unsigned long rate = parent_rate; | |
1476 | u32 val; | |
1477 | ||
1478 | val = clk_readl(c->reg + PLL_BASE); | |
1479 | c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT; | |
1480 | c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT; | |
1481 | c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT; | |
1482 | ||
1483 | if (c->mul != 0 && c->div != 0) { | |
1484 | rate *= c->mul; | |
1485 | rate += c->div - 1; /* round up */ | |
1486 | do_div(rate, c->div); | |
1487 | } | |
1488 | return rate; | |
d9cc6f76 PDS |
1489 | } |
1490 | ||
88e790a4 | 1491 | struct clk_ops tegra30_plle_ops = { |
92fe58f0 PG |
1492 | .is_enabled = tegra30_plle_clk_is_enabled, |
1493 | .enable = tegra30_plle_clk_enable, | |
1494 | .disable = tegra30_plle_clk_disable, | |
1495 | .recalc_rate = tegra30_plle_clk_recalc_rate, | |
d9cc6f76 PDS |
1496 | }; |
1497 | ||
1498 | /* Clock divider ops */ | |
92fe58f0 | 1499 | static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 1500 | { |
92fe58f0 PG |
1501 | struct clk_tegra *c = to_clk_tegra(hw); |
1502 | ||
d9cc6f76 | 1503 | if (c->flags & DIV_U71) { |
d9cc6f76 PDS |
1504 | u32 val = clk_readl(c->reg); |
1505 | val >>= c->reg_shift; | |
1506 | c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; | |
1507 | if (!(val & PLL_OUT_RESET_DISABLE)) | |
1508 | c->state = OFF; | |
d9cc6f76 PDS |
1509 | } else { |
1510 | c->state = ON; | |
d9cc6f76 | 1511 | } |
92fe58f0 | 1512 | return c->state; |
d9cc6f76 PDS |
1513 | } |
1514 | ||
92fe58f0 | 1515 | static int tegra30_pll_div_clk_enable(struct clk_hw *hw) |
d9cc6f76 | 1516 | { |
92fe58f0 | 1517 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1518 | u32 val; |
1519 | u32 new_val; | |
1520 | ||
92fe58f0 | 1521 | pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk)); |
d9cc6f76 PDS |
1522 | if (c->flags & DIV_U71) { |
1523 | val = clk_readl(c->reg); | |
1524 | new_val = val >> c->reg_shift; | |
1525 | new_val &= 0xFFFF; | |
1526 | ||
1527 | new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; | |
1528 | ||
1529 | val &= ~(0xFFFF << c->reg_shift); | |
1530 | val |= new_val << c->reg_shift; | |
1531 | clk_writel_delay(val, c->reg); | |
1532 | return 0; | |
1533 | } else if (c->flags & DIV_2) { | |
1534 | return 0; | |
1535 | } | |
1536 | return -EINVAL; | |
1537 | } | |
1538 | ||
92fe58f0 | 1539 | static void tegra30_pll_div_clk_disable(struct clk_hw *hw) |
d9cc6f76 | 1540 | { |
92fe58f0 | 1541 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1542 | u32 val; |
1543 | u32 new_val; | |
1544 | ||
92fe58f0 | 1545 | pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk)); |
d9cc6f76 PDS |
1546 | if (c->flags & DIV_U71) { |
1547 | val = clk_readl(c->reg); | |
1548 | new_val = val >> c->reg_shift; | |
1549 | new_val &= 0xFFFF; | |
1550 | ||
1551 | new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE); | |
1552 | ||
1553 | val &= ~(0xFFFF << c->reg_shift); | |
1554 | val |= new_val << c->reg_shift; | |
1555 | clk_writel_delay(val, c->reg); | |
1556 | } | |
1557 | } | |
1558 | ||
92fe58f0 PG |
1559 | static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
1560 | unsigned long parent_rate) | |
d9cc6f76 | 1561 | { |
92fe58f0 | 1562 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1563 | u32 val; |
1564 | u32 new_val; | |
1565 | int divider_u71; | |
d9cc6f76 | 1566 | |
d9cc6f76 PDS |
1567 | if (c->flags & DIV_U71) { |
1568 | divider_u71 = clk_div71_get_divider( | |
1569 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | |
1570 | if (divider_u71 >= 0) { | |
1571 | val = clk_readl(c->reg); | |
1572 | new_val = val >> c->reg_shift; | |
1573 | new_val &= 0xFFFF; | |
1574 | if (c->flags & DIV_U71_FIXED) | |
1575 | new_val |= PLL_OUT_OVERRIDE; | |
1576 | new_val &= ~PLL_OUT_RATIO_MASK; | |
1577 | new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT; | |
1578 | ||
1579 | val &= ~(0xFFFF << c->reg_shift); | |
1580 | val |= new_val << c->reg_shift; | |
1581 | clk_writel_delay(val, c->reg); | |
1582 | c->div = divider_u71 + 2; | |
1583 | c->mul = 2; | |
92fe58f0 | 1584 | c->fixed_rate = rate; |
d9cc6f76 PDS |
1585 | return 0; |
1586 | } | |
92fe58f0 PG |
1587 | } else if (c->flags & DIV_2) { |
1588 | c->fixed_rate = rate; | |
1589 | return 0; | |
1590 | } | |
d9cc6f76 PDS |
1591 | |
1592 | return -EINVAL; | |
1593 | } | |
1594 | ||
92fe58f0 PG |
1595 | static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw, |
1596 | unsigned long parent_rate) | |
1597 | { | |
1598 | struct clk_tegra *c = to_clk_tegra(hw); | |
1599 | u64 rate = parent_rate; | |
1600 | ||
1601 | if (c->flags & DIV_U71) { | |
1602 | u32 divu71; | |
1603 | u32 val = clk_readl(c->reg); | |
1604 | val >>= c->reg_shift; | |
1605 | ||
1606 | divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; | |
1607 | c->div = (divu71 + 2); | |
1608 | c->mul = 2; | |
1609 | } else if (c->flags & DIV_2) { | |
1610 | if (c->flags & (PLLD | PLLX)) { | |
1611 | c->div = 2; | |
1612 | c->mul = 1; | |
1613 | } else | |
1614 | BUG(); | |
1615 | } else { | |
1616 | c->div = 1; | |
1617 | c->mul = 1; | |
1618 | } | |
1619 | if (c->mul != 0 && c->div != 0) { | |
1620 | rate *= c->mul; | |
1621 | rate += c->div - 1; /* round up */ | |
1622 | do_div(rate, c->div); | |
1623 | } | |
1624 | ||
1625 | return rate; | |
1626 | } | |
1627 | ||
1628 | static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw, | |
1629 | unsigned long rate, unsigned long *prate) | |
d9cc6f76 | 1630 | { |
92fe58f0 PG |
1631 | struct clk_tegra *c = to_clk_tegra(hw); |
1632 | unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk)); | |
d9cc6f76 | 1633 | int divider; |
92fe58f0 PG |
1634 | |
1635 | if (prate) | |
1636 | parent_rate = *prate; | |
d9cc6f76 PDS |
1637 | |
1638 | if (c->flags & DIV_U71) { | |
1639 | divider = clk_div71_get_divider( | |
1640 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | |
1641 | if (divider < 0) | |
1642 | return divider; | |
1643 | return DIV_ROUND_UP(parent_rate * 2, divider + 2); | |
92fe58f0 PG |
1644 | } else if (c->flags & DIV_2) { |
1645 | *prate = rate * 2; | |
d9cc6f76 | 1646 | return rate; |
92fe58f0 | 1647 | } |
d9cc6f76 PDS |
1648 | |
1649 | return -EINVAL; | |
1650 | } | |
1651 | ||
88e790a4 | 1652 | struct clk_ops tegra30_pll_div_ops = { |
92fe58f0 PG |
1653 | .is_enabled = tegra30_pll_div_clk_is_enabled, |
1654 | .enable = tegra30_pll_div_clk_enable, | |
1655 | .disable = tegra30_pll_div_clk_disable, | |
1656 | .set_rate = tegra30_pll_div_clk_set_rate, | |
1657 | .recalc_rate = tegra30_pll_div_clk_recalc_rate, | |
1658 | .round_rate = tegra30_pll_div_clk_round_rate, | |
d9cc6f76 PDS |
1659 | }; |
1660 | ||
1661 | /* Periph clk ops */ | |
92fe58f0 | 1662 | static inline u32 periph_clk_source_mask(struct clk_tegra *c) |
d9cc6f76 PDS |
1663 | { |
1664 | if (c->flags & MUX8) | |
1665 | return 7 << 29; | |
1666 | else if (c->flags & MUX_PWM) | |
1667 | return 3 << 28; | |
1668 | else if (c->flags & MUX_CLK_OUT) | |
1669 | return 3 << (c->u.periph.clk_num + 4); | |
1670 | else if (c->flags & PLLD) | |
1671 | return PLLD_BASE_DSIB_MUX_MASK; | |
1672 | else | |
1673 | return 3 << 30; | |
1674 | } | |
1675 | ||
92fe58f0 | 1676 | static inline u32 periph_clk_source_shift(struct clk_tegra *c) |
d9cc6f76 PDS |
1677 | { |
1678 | if (c->flags & MUX8) | |
1679 | return 29; | |
1680 | else if (c->flags & MUX_PWM) | |
1681 | return 28; | |
1682 | else if (c->flags & MUX_CLK_OUT) | |
1683 | return c->u.periph.clk_num + 4; | |
1684 | else if (c->flags & PLLD) | |
1685 | return PLLD_BASE_DSIB_MUX_SHIFT; | |
1686 | else | |
1687 | return 30; | |
1688 | } | |
1689 | ||
92fe58f0 | 1690 | static int tegra30_periph_clk_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 1691 | { |
92fe58f0 | 1692 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1693 | |
1694 | c->state = ON; | |
1695 | if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) | |
1696 | c->state = OFF; | |
1697 | if (!(c->flags & PERIPH_NO_RESET)) | |
1698 | if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c)) | |
1699 | c->state = OFF; | |
92fe58f0 | 1700 | return c->state; |
d9cc6f76 PDS |
1701 | } |
1702 | ||
92fe58f0 | 1703 | static int tegra30_periph_clk_enable(struct clk_hw *hw) |
d9cc6f76 | 1704 | { |
92fe58f0 | 1705 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1706 | |
1707 | tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; | |
1708 | if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1) | |
1709 | return 0; | |
1710 | ||
1711 | clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_SET_REG(c)); | |
1712 | if (!(c->flags & PERIPH_NO_RESET) && | |
1713 | !(c->flags & PERIPH_MANUAL_RESET)) { | |
1714 | if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & | |
1715 | PERIPH_CLK_TO_BIT(c)) { | |
1716 | udelay(5); /* reset propagation delay */ | |
1717 | clk_writel(PERIPH_CLK_TO_BIT(c), | |
1718 | PERIPH_CLK_TO_RST_CLR_REG(c)); | |
1719 | } | |
1720 | } | |
1721 | return 0; | |
1722 | } | |
1723 | ||
92fe58f0 | 1724 | static void tegra30_periph_clk_disable(struct clk_hw *hw) |
d9cc6f76 | 1725 | { |
92fe58f0 | 1726 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 1727 | unsigned long val; |
d9cc6f76 | 1728 | |
92fe58f0 | 1729 | tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; |
d9cc6f76 | 1730 | |
92fe58f0 PG |
1731 | if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0) |
1732 | return; | |
d9cc6f76 | 1733 | |
92fe58f0 PG |
1734 | /* If peripheral is in the APB bus then read the APB bus to |
1735 | * flush the write operation in apb bus. This will avoid the | |
1736 | * peripheral access after disabling clock*/ | |
1737 | if (c->flags & PERIPH_ON_APB) | |
1738 | val = chipid_readl(); | |
1739 | ||
1740 | clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c)); | |
d9cc6f76 PDS |
1741 | } |
1742 | ||
92fe58f0 | 1743 | void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert) |
d9cc6f76 | 1744 | { |
92fe58f0 | 1745 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 1746 | unsigned long val; |
d9cc6f76 PDS |
1747 | |
1748 | if (!(c->flags & PERIPH_NO_RESET)) { | |
1749 | if (assert) { | |
1750 | /* If peripheral is in the APB bus then read the APB | |
1751 | * bus to flush the write operation in apb bus. This | |
1752 | * will avoid the peripheral access after disabling | |
1753 | * clock */ | |
1754 | if (c->flags & PERIPH_ON_APB) | |
1755 | val = chipid_readl(); | |
1756 | ||
1757 | clk_writel(PERIPH_CLK_TO_BIT(c), | |
1758 | PERIPH_CLK_TO_RST_SET_REG(c)); | |
1759 | } else | |
1760 | clk_writel(PERIPH_CLK_TO_BIT(c), | |
1761 | PERIPH_CLK_TO_RST_CLR_REG(c)); | |
1762 | } | |
1763 | } | |
1764 | ||
92fe58f0 | 1765 | static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index) |
d9cc6f76 | 1766 | { |
92fe58f0 | 1767 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 1768 | u32 val; |
d9cc6f76 PDS |
1769 | |
1770 | if (!(c->flags & MUX)) | |
92fe58f0 | 1771 | return (index == 0) ? 0 : (-EINVAL); |
d9cc6f76 | 1772 | |
92fe58f0 PG |
1773 | val = clk_readl(c->reg); |
1774 | val &= ~periph_clk_source_mask(c); | |
1775 | val |= (index << periph_clk_source_shift(c)); | |
1776 | clk_writel_delay(val, c->reg); | |
1777 | return 0; | |
1778 | } | |
d9cc6f76 | 1779 | |
92fe58f0 PG |
1780 | static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw) |
1781 | { | |
1782 | struct clk_tegra *c = to_clk_tegra(hw); | |
1783 | u32 val = clk_readl(c->reg); | |
1784 | int source = (val & periph_clk_source_mask(c)) >> | |
1785 | periph_clk_source_shift(c); | |
d9cc6f76 | 1786 | |
92fe58f0 PG |
1787 | if (!(c->flags & MUX)) |
1788 | return 0; | |
d9cc6f76 | 1789 | |
92fe58f0 | 1790 | return source; |
d9cc6f76 PDS |
1791 | } |
1792 | ||
92fe58f0 PG |
1793 | static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
1794 | unsigned long parent_rate) | |
d9cc6f76 | 1795 | { |
92fe58f0 | 1796 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1797 | u32 val; |
1798 | int divider; | |
d9cc6f76 PDS |
1799 | |
1800 | if (c->flags & DIV_U71) { | |
1801 | divider = clk_div71_get_divider( | |
1802 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | |
1803 | if (divider >= 0) { | |
1804 | val = clk_readl(c->reg); | |
1805 | val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK; | |
1806 | val |= divider; | |
1807 | if (c->flags & DIV_U71_UART) { | |
1808 | if (divider) | |
1809 | val |= PERIPH_CLK_UART_DIV_ENB; | |
1810 | else | |
1811 | val &= ~PERIPH_CLK_UART_DIV_ENB; | |
1812 | } | |
1813 | clk_writel_delay(val, c->reg); | |
1814 | c->div = divider + 2; | |
1815 | c->mul = 2; | |
1816 | return 0; | |
1817 | } | |
1818 | } else if (c->flags & DIV_U16) { | |
1819 | divider = clk_div16_get_divider(parent_rate, rate); | |
1820 | if (divider >= 0) { | |
1821 | val = clk_readl(c->reg); | |
1822 | val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; | |
1823 | val |= divider; | |
1824 | clk_writel_delay(val, c->reg); | |
1825 | c->div = divider + 1; | |
1826 | c->mul = 1; | |
1827 | return 0; | |
1828 | } | |
1829 | } else if (parent_rate <= rate) { | |
1830 | c->div = 1; | |
1831 | c->mul = 1; | |
1832 | return 0; | |
1833 | } | |
1834 | return -EINVAL; | |
1835 | } | |
1836 | ||
92fe58f0 PG |
1837 | static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
1838 | unsigned long *prate) | |
d9cc6f76 | 1839 | { |
92fe58f0 PG |
1840 | struct clk_tegra *c = to_clk_tegra(hw); |
1841 | unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk)); | |
d9cc6f76 | 1842 | int divider; |
92fe58f0 PG |
1843 | |
1844 | if (prate) | |
1845 | parent_rate = *prate; | |
d9cc6f76 PDS |
1846 | |
1847 | if (c->flags & DIV_U71) { | |
1848 | divider = clk_div71_get_divider( | |
1849 | parent_rate, rate, c->flags, ROUND_DIVIDER_UP); | |
1850 | if (divider < 0) | |
1851 | return divider; | |
1852 | ||
1853 | return DIV_ROUND_UP(parent_rate * 2, divider + 2); | |
1854 | } else if (c->flags & DIV_U16) { | |
1855 | divider = clk_div16_get_divider(parent_rate, rate); | |
1856 | if (divider < 0) | |
1857 | return divider; | |
1858 | return DIV_ROUND_UP(parent_rate, divider + 1); | |
1859 | } | |
1860 | return -EINVAL; | |
1861 | } | |
1862 | ||
92fe58f0 PG |
1863 | static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw, |
1864 | unsigned long parent_rate) | |
1865 | { | |
1866 | struct clk_tegra *c = to_clk_tegra(hw); | |
1867 | u64 rate = parent_rate; | |
1868 | u32 val = clk_readl(c->reg); | |
1869 | ||
1870 | if (c->flags & DIV_U71) { | |
1871 | u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; | |
1872 | if ((c->flags & DIV_U71_UART) && | |
1873 | (!(val & PERIPH_CLK_UART_DIV_ENB))) { | |
1874 | divu71 = 0; | |
1875 | } | |
1876 | if (c->flags & DIV_U71_IDLE) { | |
1877 | val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK << | |
1878 | PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); | |
1879 | val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL << | |
1880 | PERIPH_CLK_SOURCE_DIVIDLE_SHIFT); | |
1881 | clk_writel(val, c->reg); | |
1882 | } | |
1883 | c->div = divu71 + 2; | |
1884 | c->mul = 2; | |
1885 | } else if (c->flags & DIV_U16) { | |
1886 | u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; | |
1887 | c->div = divu16 + 1; | |
1888 | c->mul = 1; | |
1889 | } else { | |
1890 | c->div = 1; | |
1891 | c->mul = 1; | |
1892 | } | |
1893 | ||
1894 | if (c->mul != 0 && c->div != 0) { | |
1895 | rate *= c->mul; | |
1896 | rate += c->div - 1; /* round up */ | |
1897 | do_div(rate, c->div); | |
1898 | } | |
1899 | return rate; | |
1900 | } | |
1901 | ||
88e790a4 | 1902 | struct clk_ops tegra30_periph_clk_ops = { |
92fe58f0 PG |
1903 | .is_enabled = tegra30_periph_clk_is_enabled, |
1904 | .enable = tegra30_periph_clk_enable, | |
1905 | .disable = tegra30_periph_clk_disable, | |
1906 | .set_parent = tegra30_periph_clk_set_parent, | |
1907 | .get_parent = tegra30_periph_clk_get_parent, | |
1908 | .set_rate = tegra30_periph_clk_set_rate, | |
1909 | .round_rate = tegra30_periph_clk_round_rate, | |
1910 | .recalc_rate = tegra30_periph_clk_recalc_rate, | |
1911 | }; | |
1912 | ||
1913 | static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index) | |
1914 | { | |
1915 | struct clk *d = clk_get_sys(NULL, "pll_d"); | |
6e25e1b1 | 1916 | /* The DSIB parent selection bit is in PLLD base register */ |
92fe58f0 PG |
1917 | tegra_clk_cfg_ex( |
1918 | d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index); | |
1919 | ||
1920 | return 0; | |
1921 | } | |
1922 | ||
1923 | struct clk_ops tegra30_dsib_clk_ops = { | |
1924 | .is_enabled = tegra30_periph_clk_is_enabled, | |
d9cc6f76 PDS |
1925 | .enable = &tegra30_periph_clk_enable, |
1926 | .disable = &tegra30_periph_clk_disable, | |
92fe58f0 PG |
1927 | .set_parent = &tegra30_dsib_clk_set_parent, |
1928 | .get_parent = &tegra30_periph_clk_get_parent, | |
d9cc6f76 PDS |
1929 | .set_rate = &tegra30_periph_clk_set_rate, |
1930 | .round_rate = &tegra30_periph_clk_round_rate, | |
92fe58f0 | 1931 | .recalc_rate = &tegra30_periph_clk_recalc_rate, |
d9cc6f76 PDS |
1932 | }; |
1933 | ||
d9cc6f76 | 1934 | /* Periph extended clock configuration ops */ |
92fe58f0 PG |
1935 | int tegra30_vi_clk_cfg_ex(struct clk_hw *hw, |
1936 | enum tegra_clk_ex_param p, u32 setting) | |
d9cc6f76 | 1937 | { |
92fe58f0 PG |
1938 | struct clk_tegra *c = to_clk_tegra(hw); |
1939 | ||
d9cc6f76 PDS |
1940 | if (p == TEGRA_CLK_VI_INP_SEL) { |
1941 | u32 val = clk_readl(c->reg); | |
1942 | val &= ~PERIPH_CLK_VI_SEL_EX_MASK; | |
1943 | val |= (setting << PERIPH_CLK_VI_SEL_EX_SHIFT) & | |
1944 | PERIPH_CLK_VI_SEL_EX_MASK; | |
1945 | clk_writel(val, c->reg); | |
1946 | return 0; | |
1947 | } | |
1948 | return -EINVAL; | |
1949 | } | |
1950 | ||
92fe58f0 PG |
1951 | int tegra30_nand_clk_cfg_ex(struct clk_hw *hw, |
1952 | enum tegra_clk_ex_param p, u32 setting) | |
d9cc6f76 | 1953 | { |
92fe58f0 PG |
1954 | struct clk_tegra *c = to_clk_tegra(hw); |
1955 | ||
d9cc6f76 PDS |
1956 | if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) { |
1957 | u32 val = clk_readl(c->reg); | |
1958 | if (setting) | |
1959 | val |= PERIPH_CLK_NAND_DIV_EX_ENB; | |
1960 | else | |
1961 | val &= ~PERIPH_CLK_NAND_DIV_EX_ENB; | |
1962 | clk_writel(val, c->reg); | |
1963 | return 0; | |
1964 | } | |
1965 | return -EINVAL; | |
1966 | } | |
1967 | ||
92fe58f0 PG |
1968 | int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw, |
1969 | enum tegra_clk_ex_param p, u32 setting) | |
d9cc6f76 | 1970 | { |
92fe58f0 PG |
1971 | struct clk_tegra *c = to_clk_tegra(hw); |
1972 | ||
d9cc6f76 PDS |
1973 | if (p == TEGRA_CLK_DTV_INVERT) { |
1974 | u32 val = clk_readl(c->reg); | |
1975 | if (setting) | |
1976 | val |= PERIPH_CLK_DTV_POLARITY_INV; | |
1977 | else | |
1978 | val &= ~PERIPH_CLK_DTV_POLARITY_INV; | |
1979 | clk_writel(val, c->reg); | |
1980 | return 0; | |
1981 | } | |
1982 | return -EINVAL; | |
1983 | } | |
1984 | ||
d9cc6f76 PDS |
1985 | /* Output clock ops */ |
1986 | ||
1987 | static DEFINE_SPINLOCK(clk_out_lock); | |
1988 | ||
92fe58f0 | 1989 | static int tegra30_clk_out_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 1990 | { |
92fe58f0 | 1991 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
1992 | u32 val = pmc_readl(c->reg); |
1993 | ||
1994 | c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF; | |
1995 | c->mul = 1; | |
1996 | c->div = 1; | |
92fe58f0 | 1997 | return c->state; |
d9cc6f76 PDS |
1998 | } |
1999 | ||
92fe58f0 | 2000 | static int tegra30_clk_out_enable(struct clk_hw *hw) |
d9cc6f76 | 2001 | { |
92fe58f0 | 2002 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2003 | u32 val; |
2004 | unsigned long flags; | |
2005 | ||
d9cc6f76 PDS |
2006 | spin_lock_irqsave(&clk_out_lock, flags); |
2007 | val = pmc_readl(c->reg); | |
2008 | val |= (0x1 << c->u.periph.clk_num); | |
2009 | pmc_writel(val, c->reg); | |
2010 | spin_unlock_irqrestore(&clk_out_lock, flags); | |
2011 | ||
2012 | return 0; | |
2013 | } | |
2014 | ||
92fe58f0 | 2015 | static void tegra30_clk_out_disable(struct clk_hw *hw) |
d9cc6f76 | 2016 | { |
92fe58f0 | 2017 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2018 | u32 val; |
2019 | unsigned long flags; | |
2020 | ||
d9cc6f76 PDS |
2021 | spin_lock_irqsave(&clk_out_lock, flags); |
2022 | val = pmc_readl(c->reg); | |
2023 | val &= ~(0x1 << c->u.periph.clk_num); | |
2024 | pmc_writel(val, c->reg); | |
2025 | spin_unlock_irqrestore(&clk_out_lock, flags); | |
2026 | } | |
2027 | ||
92fe58f0 | 2028 | static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index) |
d9cc6f76 | 2029 | { |
92fe58f0 | 2030 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2031 | u32 val; |
2032 | unsigned long flags; | |
d9cc6f76 | 2033 | |
92fe58f0 PG |
2034 | spin_lock_irqsave(&clk_out_lock, flags); |
2035 | val = pmc_readl(c->reg); | |
2036 | val &= ~periph_clk_source_mask(c); | |
2037 | val |= (index << periph_clk_source_shift(c)); | |
2038 | pmc_writel(val, c->reg); | |
2039 | spin_unlock_irqrestore(&clk_out_lock, flags); | |
d9cc6f76 | 2040 | |
92fe58f0 PG |
2041 | return 0; |
2042 | } | |
d9cc6f76 | 2043 | |
92fe58f0 PG |
2044 | static u8 tegra30_clk_out_get_parent(struct clk_hw *hw) |
2045 | { | |
2046 | struct clk_tegra *c = to_clk_tegra(hw); | |
2047 | u32 val = pmc_readl(c->reg); | |
2048 | int source; | |
d9cc6f76 | 2049 | |
92fe58f0 PG |
2050 | source = (val & periph_clk_source_mask(c)) >> |
2051 | periph_clk_source_shift(c); | |
2052 | return source; | |
d9cc6f76 PDS |
2053 | } |
2054 | ||
88e790a4 | 2055 | struct clk_ops tegra_clk_out_ops = { |
92fe58f0 PG |
2056 | .is_enabled = tegra30_clk_out_is_enabled, |
2057 | .enable = tegra30_clk_out_enable, | |
2058 | .disable = tegra30_clk_out_disable, | |
2059 | .set_parent = tegra30_clk_out_set_parent, | |
2060 | .get_parent = tegra30_clk_out_get_parent, | |
2061 | .recalc_rate = tegra30_clk_fixed_recalc_rate, | |
d9cc6f76 PDS |
2062 | }; |
2063 | ||
d9cc6f76 | 2064 | /* Clock doubler ops */ |
92fe58f0 | 2065 | static int tegra30_clk_double_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 2066 | { |
92fe58f0 PG |
2067 | struct clk_tegra *c = to_clk_tegra(hw); |
2068 | ||
d9cc6f76 PDS |
2069 | c->state = ON; |
2070 | if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c))) | |
2071 | c->state = OFF; | |
92fe58f0 | 2072 | return c->state; |
d9cc6f76 PDS |
2073 | }; |
2074 | ||
92fe58f0 PG |
2075 | static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate, |
2076 | unsigned long parent_rate) | |
d9cc6f76 | 2077 | { |
92fe58f0 | 2078 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 2079 | u32 val; |
92fe58f0 | 2080 | |
d9cc6f76 PDS |
2081 | if (rate == parent_rate) { |
2082 | val = clk_readl(c->reg) | (0x1 << c->reg_shift); | |
2083 | clk_writel(val, c->reg); | |
2084 | c->mul = 1; | |
2085 | c->div = 1; | |
2086 | return 0; | |
2087 | } else if (rate == 2 * parent_rate) { | |
2088 | val = clk_readl(c->reg) & (~(0x1 << c->reg_shift)); | |
2089 | clk_writel(val, c->reg); | |
2090 | c->mul = 2; | |
2091 | c->div = 1; | |
2092 | return 0; | |
2093 | } | |
2094 | return -EINVAL; | |
2095 | } | |
2096 | ||
92fe58f0 PG |
2097 | static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw, |
2098 | unsigned long parent_rate) | |
2099 | { | |
2100 | struct clk_tegra *c = to_clk_tegra(hw); | |
2101 | u64 rate = parent_rate; | |
d9cc6f76 | 2102 | |
92fe58f0 PG |
2103 | u32 val = clk_readl(c->reg); |
2104 | c->mul = val & (0x1 << c->reg_shift) ? 1 : 2; | |
2105 | c->div = 1; | |
2106 | ||
2107 | if (c->mul != 0 && c->div != 0) { | |
2108 | rate *= c->mul; | |
2109 | rate += c->div - 1; /* round up */ | |
2110 | do_div(rate, c->div); | |
2111 | } | |
2112 | ||
2113 | return rate; | |
2114 | } | |
2115 | ||
2116 | static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate, | |
2117 | unsigned long *prate) | |
d9cc6f76 | 2118 | { |
92fe58f0 PG |
2119 | unsigned long output_rate = *prate; |
2120 | ||
2121 | do_div(output_rate, 2); | |
2122 | return output_rate; | |
d9cc6f76 PDS |
2123 | } |
2124 | ||
92fe58f0 PG |
2125 | struct clk_ops tegra30_clk_double_ops = { |
2126 | .is_enabled = tegra30_clk_double_is_enabled, | |
2127 | .enable = tegra30_periph_clk_enable, | |
2128 | .disable = tegra30_periph_clk_disable, | |
2129 | .recalc_rate = tegra30_clk_double_recalc_rate, | |
2130 | .round_rate = tegra30_clk_double_round_rate, | |
2131 | .set_rate = tegra30_clk_double_set_rate, | |
2132 | }; | |
2133 | ||
2134 | /* Audio sync clock ops */ | |
88e790a4 | 2135 | struct clk_ops tegra_sync_source_ops = { |
92fe58f0 | 2136 | .recalc_rate = tegra30_clk_fixed_recalc_rate, |
d9cc6f76 PDS |
2137 | }; |
2138 | ||
92fe58f0 | 2139 | static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 2140 | { |
92fe58f0 | 2141 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2142 | u32 val = clk_readl(c->reg); |
2143 | c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON; | |
92fe58f0 | 2144 | return c->state; |
d9cc6f76 PDS |
2145 | } |
2146 | ||
92fe58f0 | 2147 | static int tegra30_audio_sync_clk_enable(struct clk_hw *hw) |
d9cc6f76 | 2148 | { |
92fe58f0 | 2149 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2150 | u32 val = clk_readl(c->reg); |
2151 | clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg); | |
2152 | return 0; | |
2153 | } | |
2154 | ||
92fe58f0 | 2155 | static void tegra30_audio_sync_clk_disable(struct clk_hw *hw) |
d9cc6f76 | 2156 | { |
92fe58f0 | 2157 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2158 | u32 val = clk_readl(c->reg); |
2159 | clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg); | |
2160 | } | |
2161 | ||
92fe58f0 | 2162 | static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index) |
d9cc6f76 | 2163 | { |
92fe58f0 | 2164 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 | 2165 | u32 val; |
d9cc6f76 | 2166 | |
92fe58f0 PG |
2167 | val = clk_readl(c->reg); |
2168 | val &= ~AUDIO_SYNC_SOURCE_MASK; | |
2169 | val |= index; | |
d9cc6f76 | 2170 | |
92fe58f0 PG |
2171 | clk_writel(val, c->reg); |
2172 | return 0; | |
2173 | } | |
d9cc6f76 | 2174 | |
92fe58f0 PG |
2175 | static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw) |
2176 | { | |
2177 | struct clk_tegra *c = to_clk_tegra(hw); | |
2178 | u32 val = clk_readl(c->reg); | |
2179 | int source; | |
d9cc6f76 | 2180 | |
92fe58f0 PG |
2181 | source = val & AUDIO_SYNC_SOURCE_MASK; |
2182 | return source; | |
d9cc6f76 PDS |
2183 | } |
2184 | ||
88e790a4 | 2185 | struct clk_ops tegra30_audio_sync_clk_ops = { |
92fe58f0 PG |
2186 | .is_enabled = tegra30_audio_sync_clk_is_enabled, |
2187 | .enable = tegra30_audio_sync_clk_enable, | |
2188 | .disable = tegra30_audio_sync_clk_disable, | |
d9cc6f76 | 2189 | .set_parent = tegra30_audio_sync_clk_set_parent, |
92fe58f0 PG |
2190 | .get_parent = tegra30_audio_sync_clk_get_parent, |
2191 | .recalc_rate = tegra30_clk_fixed_recalc_rate, | |
d9cc6f76 PDS |
2192 | }; |
2193 | ||
2194 | /* cml0 (pcie), and cml1 (sata) clock ops */ | |
92fe58f0 | 2195 | static int tegra30_cml_clk_is_enabled(struct clk_hw *hw) |
d9cc6f76 | 2196 | { |
92fe58f0 | 2197 | struct clk_tegra *c = to_clk_tegra(hw); |
d9cc6f76 PDS |
2198 | u32 val = clk_readl(c->reg); |
2199 | c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF; | |
92fe58f0 | 2200 | return c->state; |
d9cc6f76 PDS |
2201 | } |
2202 | ||
92fe58f0 | 2203 | static int tegra30_cml_clk_enable(struct clk_hw *hw) |
d9cc6f76 | 2204 | { |
92fe58f0 PG |
2205 | struct clk_tegra *c = to_clk_tegra(hw); |
2206 | ||
d9cc6f76 PDS |
2207 | u32 val = clk_readl(c->reg); |
2208 | val |= (0x1 << c->u.periph.clk_num); | |
2209 | clk_writel(val, c->reg); | |
92fe58f0 | 2210 | |
d9cc6f76 PDS |
2211 | return 0; |
2212 | } | |
2213 | ||
92fe58f0 | 2214 | static void tegra30_cml_clk_disable(struct clk_hw *hw) |
d9cc6f76 | 2215 | { |
92fe58f0 PG |
2216 | struct clk_tegra *c = to_clk_tegra(hw); |
2217 | ||
d9cc6f76 PDS |
2218 | u32 val = clk_readl(c->reg); |
2219 | val &= ~(0x1 << c->u.periph.clk_num); | |
2220 | clk_writel(val, c->reg); | |
2221 | } | |
2222 | ||
88e790a4 | 2223 | struct clk_ops tegra_cml_clk_ops = { |
92fe58f0 PG |
2224 | .is_enabled = tegra30_cml_clk_is_enabled, |
2225 | .enable = tegra30_cml_clk_enable, | |
2226 | .disable = tegra30_cml_clk_disable, | |
2227 | .recalc_rate = tegra30_clk_fixed_recalc_rate, | |
2228 | }; | |
2229 | ||
2230 | struct clk_ops tegra_pciex_clk_ops = { | |
2231 | .recalc_rate = tegra30_clk_fixed_recalc_rate, | |
d9cc6f76 | 2232 | }; |
dab403ef JL |
2233 | |
2234 | /* Tegra30 CPU clock and reset control functions */ | |
2235 | static void tegra30_wait_cpu_in_reset(u32 cpu) | |
2236 | { | |
2237 | unsigned int reg; | |
2238 | ||
2239 | do { | |
2240 | reg = readl(reg_clk_base + | |
2241 | TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); | |
2242 | cpu_relax(); | |
2243 | } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ | |
2244 | ||
2245 | return; | |
2246 | } | |
2247 | ||
2248 | static void tegra30_put_cpu_in_reset(u32 cpu) | |
2249 | { | |
2250 | writel(CPU_RESET(cpu), | |
2251 | reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); | |
2252 | dmb(); | |
2253 | } | |
2254 | ||
2255 | static void tegra30_cpu_out_of_reset(u32 cpu) | |
2256 | { | |
2257 | writel(CPU_RESET(cpu), | |
2258 | reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); | |
2259 | wmb(); | |
2260 | } | |
2261 | ||
2262 | static void tegra30_enable_cpu_clock(u32 cpu) | |
2263 | { | |
2264 | unsigned int reg; | |
2265 | ||
2266 | writel(CPU_CLOCK(cpu), | |
2267 | reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); | |
2268 | reg = readl(reg_clk_base + | |
2269 | TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); | |
2270 | } | |
2271 | ||
2272 | static void tegra30_disable_cpu_clock(u32 cpu) | |
2273 | { | |
2274 | ||
2275 | unsigned int reg; | |
2276 | ||
2277 | reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); | |
2278 | writel(reg | CPU_CLOCK(cpu), | |
2279 | reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX); | |
2280 | } | |
2281 | ||
2282 | static struct tegra_cpu_car_ops tegra30_cpu_car_ops = { | |
2283 | .wait_for_reset = tegra30_wait_cpu_in_reset, | |
2284 | .put_in_reset = tegra30_put_cpu_in_reset, | |
2285 | .out_of_reset = tegra30_cpu_out_of_reset, | |
2286 | .enable_clock = tegra30_enable_cpu_clock, | |
2287 | .disable_clock = tegra30_disable_cpu_clock, | |
2288 | }; | |
2289 | ||
2290 | void __init tegra30_cpu_car_ops_init(void) | |
2291 | { | |
2292 | tegra_cpu_car_ops = &tegra30_cpu_car_ops; | |
2293 | } |