Commit | Line | Data |
---|---|---|
8e267f3d | 1 | /* |
1b14f3a5 | 2 | * NVIDIA Tegra SoC device tree board support |
8e267f3d | 3 | * |
1b14f3a5 | 4 | * Copyright (C) 2011, 2013, NVIDIA Corporation |
8e267f3d GL |
5 | * Copyright (C) 2010 Secret Lab Technologies, Ltd. |
6 | * Copyright (C) 2010 Google, Inc. | |
7 | * | |
8 | * This software is licensed under the terms of the GNU General Public | |
9 | * License version 2, as published by the Free Software Foundation, and | |
10 | * may be copied, distributed, and modified under those terms. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | */ | |
18 | ||
8e267f3d | 19 | #include <linux/clk.h> |
a0524acc | 20 | #include <linux/clk/tegra.h> |
8e267f3d | 21 | #include <linux/dma-mapping.h> |
a0524acc TR |
22 | #include <linux/init.h> |
23 | #include <linux/io.h> | |
24 | #include <linux/irqchip.h> | |
8e267f3d | 25 | #include <linux/irqdomain.h> |
a0524acc | 26 | #include <linux/kernel.h> |
8e267f3d GL |
27 | #include <linux/of_address.h> |
28 | #include <linux/of_fdt.h> | |
a0524acc | 29 | #include <linux/of.h> |
8e267f3d GL |
30 | #include <linux/of_platform.h> |
31 | #include <linux/pda_power.h> | |
a0524acc TR |
32 | #include <linux/platform_device.h> |
33 | #include <linux/serial_8250.h> | |
d591fdf8 DH |
34 | #include <linux/slab.h> |
35 | #include <linux/sys_soc.h> | |
bab53ce3 | 36 | #include <linux/usb/tegra_usb_phy.h> |
8e267f3d | 37 | |
304664ea | 38 | #include <soc/tegra/fuse.h> |
7232398a | 39 | #include <soc/tegra/pmc.h> |
304664ea | 40 | |
51100bdc | 41 | #include <asm/hardware/cache-l2x0.h> |
8e267f3d GL |
42 | #include <asm/mach/arch.h> |
43 | #include <asm/mach/time.h> | |
a0524acc | 44 | #include <asm/mach-types.h> |
8e267f3d | 45 | #include <asm/setup.h> |
1a5de3ae | 46 | #include <asm/trusted_foundations.h> |
8e267f3d | 47 | |
8e267f3d | 48 | #include "board.h" |
a1725732 | 49 | #include "common.h" |
51100bdc | 50 | #include "cpuidle.h" |
2be39c07 | 51 | #include "iomap.h" |
51100bdc | 52 | #include "irq.h" |
51100bdc SW |
53 | #include "pm.h" |
54 | #include "reset.h" | |
55 | #include "sleep.h" | |
56 | ||
57 | /* | |
58 | * Storage for debug-macro.S's state. | |
59 | * | |
60 | * This must be in .data not .bss so that it gets initialized each time the | |
61 | * kernel is loaded. The data is declared here rather than debug-macro.S so | |
62 | * that multiple inclusions of debug-macro.S point at the same data. | |
63 | */ | |
2f1d70af | 64 | u32 tegra_uart_config[3] = { |
51100bdc SW |
65 | /* Debug UART initialization required */ |
66 | 1, | |
67 | /* Debug UART physical address */ | |
68 | 0, | |
69 | /* Debug UART virtual address */ | |
70 | 0, | |
51100bdc SW |
71 | }; |
72 | ||
51100bdc SW |
73 | static void __init tegra_init_early(void) |
74 | { | |
1a5de3ae | 75 | of_register_trusted_foundations(); |
cd198d6d | 76 | tegra_cpu_reset_handler_init(); |
51100bdc SW |
77 | } |
78 | ||
79 | static void __init tegra_dt_init_irq(void) | |
80 | { | |
51100bdc SW |
81 | tegra_init_irq(); |
82 | irqchip_init(); | |
51100bdc | 83 | } |
bab53ce3 | 84 | |
8e267f3d GL |
85 | static void __init tegra_dt_init(void) |
86 | { | |
d591fdf8 DH |
87 | struct soc_device_attribute *soc_dev_attr; |
88 | struct soc_device *soc_dev; | |
89 | struct device *parent = NULL; | |
90 | ||
91 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | |
92 | if (!soc_dev_attr) | |
93 | goto out; | |
94 | ||
95 | soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra"); | |
783c8f4c PDS |
96 | soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", |
97 | tegra_sku_info.revision); | |
304664ea | 98 | soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); |
d591fdf8 DH |
99 | |
100 | soc_dev = soc_device_register(soc_dev_attr); | |
101 | if (IS_ERR(soc_dev)) { | |
102 | kfree(soc_dev_attr->family); | |
103 | kfree(soc_dev_attr->revision); | |
104 | kfree(soc_dev_attr->soc_id); | |
105 | kfree(soc_dev_attr); | |
106 | goto out; | |
107 | } | |
108 | ||
109 | parent = soc_device_to_device(soc_dev); | |
110 | ||
a58116f3 SW |
111 | /* |
112 | * Finished with the static registrations now; fill in the missing | |
113 | * devices | |
114 | */ | |
d591fdf8 | 115 | out: |
435ebcbc | 116 | of_platform_default_populate(NULL, NULL, parent); |
8e267f3d GL |
117 | } |
118 | ||
c554dee3 SW |
119 | static void __init tegra_dt_init_late(void) |
120 | { | |
51100bdc SW |
121 | tegra_init_suspend(); |
122 | tegra_cpuidle_init(); | |
c554dee3 | 123 | |
da35cbca AB |
124 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && |
125 | of_machine_is_compatible("compal,paz00")) | |
126 | tegra_paz00_wifikill_init(); | |
c554dee3 SW |
127 | } |
128 | ||
1b14f3a5 | 129 | static const char * const tegra_dt_board_compat[] = { |
73944475 | 130 | "nvidia,tegra124", |
1b14f3a5 HD |
131 | "nvidia,tegra114", |
132 | "nvidia,tegra30", | |
c5444f39 | 133 | "nvidia,tegra20", |
8e267f3d GL |
134 | NULL |
135 | }; | |
136 | ||
1b14f3a5 | 137 | DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)") |
00123d9a RK |
138 | .l2c_aux_val = 0x3c400001, |
139 | .l2c_aux_mask = 0xc20fc3fe, | |
a1725732 | 140 | .smp = smp_ops(tegra_smp_ops), |
00123d9a | 141 | .map_io = tegra_map_common_io, |
7469688e | 142 | .init_early = tegra_init_early, |
0d4f7479 | 143 | .init_irq = tegra_dt_init_irq, |
8e267f3d | 144 | .init_machine = tegra_dt_init, |
c554dee3 | 145 | .init_late = tegra_dt_init_late, |
1b14f3a5 | 146 | .dt_compat = tegra_dt_board_compat, |
8e267f3d | 147 | MACHINE_END |