[linux-2.6-block.git] / arch / arm / mach-tegra / reset.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * arch/arm/mach-tegra/reset.c
 *
 * Copyright (C) 2011,2012 NVIDIA Corporation.
 */

#include <linux/bitops.h>
#include <linux/cpumask.h>
#include <linux/init.h>
#include <linux/io.h>

#include <linux/firmware/trusted_foundations.h>

#include <soc/tegra/fuse.h>

#include <asm/cacheflush.h>
#include <asm/firmware.h>
#include <asm/hardware/cache-l2x0.h>

#include "iomap.h"
#include "irammap.h"
#include "reset.h"
#include "sleep.h"

#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
				TEGRA_IRAM_RESET_HANDLER_OFFSET)

static bool is_enabled;

static void __init tegra_cpu_reset_handler_set(const u32 reset_address)
{
	void __iomem *evp_cpu_reset =
		IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
	void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
	u32 reg;

	/*
	 * NOTE: This must be the one and only write to the EVP CPU reset
	 *       vector in the entire system.
	 */
	writel(reset_address, evp_cpu_reset);
	wmb();
	reg = readl(evp_cpu_reset);

	/*
	 * Prevent further modifications to the physical reset vector.
	 *  NOTE: Has no effect on chips prior to Tegra30.
	 */
	reg = readl(sb_ctrl);
	reg |= 2;
	writel(reg, sb_ctrl);
	wmb();
}

static void __init tegra_cpu_reset_handler_enable(void)
{
	void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
	const u32 reset_address = TEGRA_IRAM_RESET_BASE +
						tegra_cpu_reset_handler_offset;
	int err;

	BUG_ON(is_enabled);
	BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);

	memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
			tegra_cpu_reset_handler_size);

	err = call_firmware_op(set_cpu_boot_addr, 0, reset_address);
	switch (err) {
	case -ENOSYS:
		tegra_cpu_reset_handler_set(reset_address);
		/* fall through */
	case 0:
		is_enabled = true;
		break;
	default:
		pr_crit("Cannot set CPU reset handler: %d\n", err);
		BUG();
	}
}

void __init tegra_cpu_reset_handler_init(void)
{
	__tegra_cpu_reset_handler_data[TEGRA_RESET_TF_PRESENT] =
		trusted_foundations_registered();

#ifdef CONFIG_SMP
	__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
		*((u32 *)cpu_possible_mask);
	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
		__pa_symbol((void *)secondary_startup);
#endif

#ifdef CONFIG_PM_SLEEP
	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
		TEGRA_IRAM_LPx_RESUME_AREA;
	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
		__pa_symbol((void *)tegra_resume);
#endif

	tegra_cpu_reset_handler_enable();
}
Commit	Line	Data
9c92ab61	1	// SPDX-License-Identifier: GPL-2.0-only
b36ab975 PDS	2	/*
	3	* arch/arm/mach-tegra/reset.c
	4	*
	5	* Copyright (C) 2011,2012 NVIDIA Corporation.
b36ab975 PDS	6	*/
b36ab975 PDS	7
a0524acc TR	8	#include <linux/bitops.h>
a0524acc TR	9	#include <linux/cpumask.h>
b36ab975 PDS	10	#include <linux/init.h>
b36ab975 PDS	11	#include <linux/io.h>
b36ab975	12
4cb5d9ec TR	13	#include <linux/firmware/trusted_foundations.h>
4cb5d9ec TR	14
304664ea TR	15	#include <soc/tegra/fuse.h>
304664ea TR	16
b36ab975	17	#include <asm/cacheflush.h>
265c89c9	18	#include <asm/firmware.h>
a0524acc	19	#include <asm/hardware/cache-l2x0.h>
b36ab975	20
2be39c07	21	#include "iomap.h"
bb1de887	22	#include "irammap.h"
b36ab975	23	#include "reset.h"
d3f29365	24	#include "sleep.h"
b36ab975 PDS	25
	26	#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
	27	TEGRA_IRAM_RESET_HANDLER_OFFSET)
	28
	29	static bool is_enabled;
	30
ad14ecee	31	static void __init tegra_cpu_reset_handler_set(const u32 reset_address)
b36ab975	32	{
b36ab975 PDS	33	void __iomem *evp_cpu_reset =
	34	IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
	35	void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
	36	u32 reg;
	37
b36ab975 PDS	38	/*
	39	* NOTE: This must be the one and only write to the EVP CPU reset
	40	* vector in the entire system.
	41	*/
ad14ecee	42	writel(reset_address, evp_cpu_reset);
b36ab975 PDS	43	wmb();
	44	reg = readl(evp_cpu_reset);
	45
	46	/*
	47	* Prevent further modifications to the physical reset vector.
	48	* NOTE: Has no effect on chips prior to Tegra30.
	49	*/
c090e111 TR	50	reg = readl(sb_ctrl);
	51	reg \|= 2;
	52	writel(reg, sb_ctrl);
	53	wmb();
ad14ecee AC	54	}
	55
	56	static void __init tegra_cpu_reset_handler_enable(void)
	57	{
	58	void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
	59	const u32 reset_address = TEGRA_IRAM_RESET_BASE +
	60	tegra_cpu_reset_handler_offset;
265c89c9	61	int err;
ad14ecee AC	62
	63	BUG_ON(is_enabled);
	64	BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
	65
	66	memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
	67	tegra_cpu_reset_handler_size);
	68
265c89c9 AC	69	err = call_firmware_op(set_cpu_boot_addr, 0, reset_address);
	70	switch (err) {
	71	case -ENOSYS:
	72	tegra_cpu_reset_handler_set(reset_address);
9b76ad3a	73	/* fall through */
265c89c9 AC	74	case 0:
	75	is_enabled = true;
	76	break;
	77	default:
	78	pr_crit("Cannot set CPU reset handler: %d\n", err);
	79	BUG();
	80	}
b36ab975 PDS	81	}
	82
	83	void __init tegra_cpu_reset_handler_init(void)
	84	{
2af6597a DO	85	__tegra_cpu_reset_handler_data[TEGRA_RESET_TF_PRESENT] =
2af6597a DO	86	trusted_foundations_registered();
b36ab975 PDS	87
	88	#ifdef CONFIG_SMP
	89	__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
9e32366f	90	((u32 )cpu_possible_mask);
b36ab975	91	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
64fc2a94	92	__pa_symbol((void *)secondary_startup);
b36ab975 PDS	93	#endif
b36ab975 PDS	94
d3f29365	95	#ifdef CONFIG_PM_SLEEP
5b795d05	96	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
fddb770d	97	TEGRA_IRAM_LPx_RESUME_AREA;
d3f29365	98	__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
64fc2a94	99	__pa_symbol((void *)tegra_resume);
d3f29365 JL	100	#endif
d3f29365 JL	101
b36ab975 PDS	102	tegra_cpu_reset_handler_enable();
b36ab975 PDS	103	}