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9952f691 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d457ef35 JL |
2 | /* |
3 | * CPU complex suspend & resume functions for Tegra SoCs | |
4 | * | |
5 | * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved. | |
d457ef35 JL |
6 | */ |
7 | ||
a0524acc | 8 | #include <linux/clk/tegra.h> |
d457ef35 | 9 | #include <linux/cpumask.h> |
d552920a | 10 | #include <linux/cpu_pm.h> |
a0524acc | 11 | #include <linux/delay.h> |
d552920a | 12 | #include <linux/err.h> |
a0524acc TR |
13 | #include <linux/io.h> |
14 | #include <linux/kernel.h> | |
1ff6bbfd | 15 | #include <linux/slab.h> |
a0524acc TR |
16 | #include <linux/spinlock.h> |
17 | #include <linux/suspend.h> | |
d552920a | 18 | |
4cb5d9ec TR |
19 | #include <linux/firmware/trusted_foundations.h> |
20 | ||
7e10cf74 | 21 | #include <soc/tegra/flowctrl.h> |
304664ea | 22 | #include <soc/tegra/fuse.h> |
7232398a TR |
23 | #include <soc/tegra/pm.h> |
24 | #include <soc/tegra/pmc.h> | |
304664ea | 25 | |
d552920a | 26 | #include <asm/cacheflush.h> |
78ee399f | 27 | #include <asm/firmware.h> |
d552920a JL |
28 | #include <asm/idmap.h> |
29 | #include <asm/proc-fns.h> | |
a0524acc TR |
30 | #include <asm/smp_plat.h> |
31 | #include <asm/suspend.h> | |
d552920a | 32 | #include <asm/tlbflush.h> |
d457ef35 | 33 | |
a0524acc | 34 | #include "iomap.h" |
a0524acc TR |
35 | #include "pm.h" |
36 | #include "reset.h" | |
d552920a | 37 | #include "sleep.h" |
d552920a | 38 | |
d457ef35 | 39 | #ifdef CONFIG_PM_SLEEP |
d457ef35 | 40 | static DEFINE_SPINLOCK(tegra_lp2_lock); |
95872f42 JL |
41 | static u32 iram_save_size; |
42 | static void *iram_save_addr; | |
43 | struct tegra_lp1_iram tegra_lp1_iram; | |
d552920a | 44 | void (*tegra_tear_down_cpu)(void); |
95872f42 JL |
45 | void (*tegra_sleep_core_finish)(unsigned long v2p); |
46 | static int (*tegra_sleep_func)(unsigned long v2p); | |
d457ef35 | 47 | |
bf91add4 JL |
48 | static void tegra_tear_down_cpu_init(void) |
49 | { | |
304664ea | 50 | switch (tegra_get_chip_id()) { |
bf91add4 JL |
51 | case TEGRA20: |
52 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) | |
53 | tegra_tear_down_cpu = tegra20_tear_down_cpu; | |
54 | break; | |
55 | case TEGRA30: | |
b573ad9f | 56 | case TEGRA114: |
f0c4ac13 | 57 | case TEGRA124: |
b573ad9f | 58 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || |
f0c4ac13 JL |
59 | IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || |
60 | IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) | |
bf91add4 JL |
61 | tegra_tear_down_cpu = tegra30_tear_down_cpu; |
62 | break; | |
63 | } | |
64 | } | |
65 | ||
d552920a JL |
66 | /* |
67 | * restore_cpu_complex | |
68 | * | |
69 | * restores cpu clock setting, clears flow controller | |
70 | * | |
71 | * Always called on CPU 0. | |
72 | */ | |
73 | static void restore_cpu_complex(void) | |
74 | { | |
75 | int cpu = smp_processor_id(); | |
76 | ||
77 | BUG_ON(cpu != 0); | |
78 | ||
79 | #ifdef CONFIG_SMP | |
80 | cpu = cpu_logical_map(cpu); | |
81 | #endif | |
82 | ||
83 | /* Restore the CPU clock settings */ | |
84 | tegra_cpu_clock_resume(); | |
85 | ||
86 | flowctrl_cpu_suspend_exit(cpu); | |
d552920a JL |
87 | } |
88 | ||
89 | /* | |
90 | * suspend_cpu_complex | |
91 | * | |
92 | * saves pll state for use by restart_plls, prepares flow controller for | |
93 | * transition to suspend state | |
94 | * | |
95 | * Must always be called on cpu 0. | |
96 | */ | |
97 | static void suspend_cpu_complex(void) | |
98 | { | |
99 | int cpu = smp_processor_id(); | |
100 | ||
101 | BUG_ON(cpu != 0); | |
102 | ||
103 | #ifdef CONFIG_SMP | |
104 | cpu = cpu_logical_map(cpu); | |
105 | #endif | |
106 | ||
107 | /* Save the CPU clock settings */ | |
108 | tegra_cpu_clock_suspend(); | |
109 | ||
110 | flowctrl_cpu_suspend_enter(cpu); | |
d552920a JL |
111 | } |
112 | ||
1f3e18ec | 113 | void tegra_pm_clear_cpu_in_lp2(void) |
d457ef35 | 114 | { |
8f6a0b65 | 115 | int phy_cpu_id = cpu_logical_map(smp_processor_id()); |
d457ef35 JL |
116 | u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; |
117 | ||
118 | spin_lock(&tegra_lp2_lock); | |
119 | ||
120 | BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id))); | |
121 | *cpu_in_lp2 &= ~BIT(phy_cpu_id); | |
122 | ||
123 | spin_unlock(&tegra_lp2_lock); | |
124 | } | |
125 | ||
1f3e18ec | 126 | void tegra_pm_set_cpu_in_lp2(void) |
d457ef35 | 127 | { |
8f6a0b65 | 128 | int phy_cpu_id = cpu_logical_map(smp_processor_id()); |
d457ef35 JL |
129 | u32 *cpu_in_lp2 = tegra_cpu_lp2_mask; |
130 | ||
131 | spin_lock(&tegra_lp2_lock); | |
132 | ||
133 | BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id))); | |
134 | *cpu_in_lp2 |= BIT(phy_cpu_id); | |
135 | ||
d457ef35 | 136 | spin_unlock(&tegra_lp2_lock); |
d457ef35 | 137 | } |
d552920a JL |
138 | |
139 | static int tegra_sleep_cpu(unsigned long v2p) | |
140 | { | |
7ed50dd5 DO |
141 | if (tegra_cpu_car_ops->rail_off_ready && |
142 | WARN_ON(!tegra_cpu_rail_off_ready())) | |
143 | return -EBUSY; | |
144 | ||
78ee399f DO |
145 | /* |
146 | * L2 cache disabling using kernel API only allowed when all | |
147 | * secondary CPU's are offline. Cache have to be disabled with | |
148 | * MMU-on if cache maintenance is done via Trusted Foundations | |
149 | * firmware. Note that CPUIDLE won't ever enter powergate on Tegra30 | |
150 | * if any of secondary CPU's is online and this is the LP2-idle | |
151 | * code-path only for Tegra20/30. | |
152 | */ | |
7ed50dd5 DO |
153 | #ifdef CONFIG_OUTER_CACHE |
154 | if (trusted_foundations_registered() && outer_cache.disable) | |
155 | outer_cache.disable(); | |
156 | #endif | |
78ee399f DO |
157 | /* |
158 | * Note that besides of setting up CPU reset vector this firmware | |
159 | * call may also do the following, depending on the FW version: | |
160 | * 1) Disable L2. But this doesn't matter since we already | |
161 | * disabled the L2. | |
162 | * 2) Disable D-cache. This need to be taken into account in | |
163 | * particular by the tegra_disable_clean_inv_dcache() which | |
164 | * shall avoid the re-disable. | |
165 | */ | |
166 | call_firmware_op(prepare_idle, TF_PM_MODE_LP2); | |
167 | ||
6affb482 | 168 | setup_mm_for_reboot(); |
d552920a JL |
169 | tegra_sleep_cpu_finish(v2p); |
170 | ||
171 | /* should never here */ | |
172 | BUG(); | |
173 | ||
174 | return 0; | |
175 | } | |
176 | ||
7232398a TR |
177 | static void tegra_pm_set(enum tegra_suspend_mode mode) |
178 | { | |
179 | u32 value; | |
180 | ||
181 | switch (tegra_get_chip_id()) { | |
182 | case TEGRA20: | |
183 | case TEGRA30: | |
184 | break; | |
185 | default: | |
186 | /* Turn off CRAIL */ | |
187 | value = flowctrl_read_cpu_csr(0); | |
188 | value &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK; | |
189 | value |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL; | |
190 | flowctrl_write_cpu_csr(0, value); | |
191 | break; | |
192 | } | |
193 | ||
194 | tegra_pmc_enter_suspend_mode(mode); | |
195 | } | |
196 | ||
1f3e18ec | 197 | int tegra_pm_enter_lp2(void) |
d552920a | 198 | { |
891e1286 DO |
199 | int err; |
200 | ||
7232398a | 201 | tegra_pm_set(TEGRA_SUSPEND_LP2); |
d552920a JL |
202 | |
203 | cpu_cluster_pm_enter(); | |
204 | suspend_cpu_complex(); | |
d552920a | 205 | |
891e1286 | 206 | err = cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); |
d552920a | 207 | |
78ee399f DO |
208 | /* |
209 | * Resume L2 cache if it wasn't re-enabled early during resume, | |
210 | * which is the case for Tegra30 that has to re-enable the cache | |
211 | * via firmware call. In other cases cache is already enabled and | |
212 | * hence re-enabling is a no-op. This is always a no-op on Tegra114+. | |
213 | */ | |
214 | outer_resume(); | |
215 | ||
d552920a JL |
216 | restore_cpu_complex(); |
217 | cpu_cluster_pm_exit(); | |
891e1286 | 218 | |
38743e41 DO |
219 | call_firmware_op(prepare_idle, TF_PM_MODE_NONE); |
220 | ||
891e1286 | 221 | return err; |
d552920a | 222 | } |
c8c2e606 JL |
223 | |
224 | enum tegra_suspend_mode tegra_pm_validate_suspend_mode( | |
225 | enum tegra_suspend_mode mode) | |
226 | { | |
c8c2e606 | 227 | /* |
95872f42 | 228 | * The Tegra devices support suspending to LP1 or lower currently. |
c8c2e606 | 229 | */ |
95872f42 JL |
230 | if (mode > TEGRA_SUSPEND_LP1) |
231 | return TEGRA_SUSPEND_LP1; | |
c8c2e606 JL |
232 | |
233 | return mode; | |
234 | } | |
235 | ||
95872f42 JL |
236 | static int tegra_sleep_core(unsigned long v2p) |
237 | { | |
78ee399f DO |
238 | /* |
239 | * Cache have to be disabled with MMU-on if cache maintenance is done | |
240 | * via Trusted Foundations firmware. This is a no-op on Tegra114+. | |
241 | */ | |
242 | if (trusted_foundations_registered()) | |
243 | outer_disable(); | |
244 | ||
245 | call_firmware_op(prepare_idle, TF_PM_MODE_LP1); | |
246 | ||
95872f42 JL |
247 | setup_mm_for_reboot(); |
248 | tegra_sleep_core_finish(v2p); | |
249 | ||
250 | /* should never here */ | |
251 | BUG(); | |
252 | ||
253 | return 0; | |
254 | } | |
255 | ||
256 | /* | |
257 | * tegra_lp1_iram_hook | |
258 | * | |
259 | * Hooking the address of LP1 reset vector and SDRAM self-refresh code in | |
260 | * SDRAM. These codes not be copied to IRAM in this fuction. We need to | |
261 | * copy these code to IRAM before LP0/LP1 suspend and restore the content | |
262 | * of IRAM after resume. | |
263 | */ | |
264 | static bool tegra_lp1_iram_hook(void) | |
265 | { | |
304664ea | 266 | switch (tegra_get_chip_id()) { |
731a9274 JL |
267 | case TEGRA20: |
268 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) | |
269 | tegra20_lp1_iram_hook(); | |
270 | break; | |
e7a932b1 | 271 | case TEGRA30: |
e9f62449 | 272 | case TEGRA114: |
f0c4ac13 | 273 | case TEGRA124: |
e9f62449 | 274 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || |
f0c4ac13 JL |
275 | IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || |
276 | IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) | |
e7a932b1 JL |
277 | tegra30_lp1_iram_hook(); |
278 | break; | |
279 | default: | |
280 | break; | |
281 | } | |
282 | ||
95872f42 JL |
283 | if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr) |
284 | return false; | |
285 | ||
286 | iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr; | |
287 | iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL); | |
288 | if (!iram_save_addr) | |
289 | return false; | |
290 | ||
291 | return true; | |
292 | } | |
293 | ||
294 | static bool tegra_sleep_core_init(void) | |
295 | { | |
304664ea | 296 | switch (tegra_get_chip_id()) { |
731a9274 JL |
297 | case TEGRA20: |
298 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) | |
299 | tegra20_sleep_core_init(); | |
300 | break; | |
e7a932b1 | 301 | case TEGRA30: |
e9f62449 | 302 | case TEGRA114: |
f0c4ac13 | 303 | case TEGRA124: |
e9f62449 | 304 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) || |
f0c4ac13 JL |
305 | IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) || |
306 | IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)) | |
e7a932b1 JL |
307 | tegra30_sleep_core_init(); |
308 | break; | |
309 | default: | |
310 | break; | |
311 | } | |
312 | ||
95872f42 JL |
313 | if (!tegra_sleep_core_finish) |
314 | return false; | |
315 | ||
316 | return true; | |
317 | } | |
318 | ||
319 | static void tegra_suspend_enter_lp1(void) | |
320 | { | |
95872f42 | 321 | /* copy the reset vector & SDRAM shutdown code into IRAM */ |
fddb770d | 322 | memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), |
95872f42 | 323 | iram_save_size); |
fddb770d SW |
324 | memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), |
325 | tegra_lp1_iram.start_addr, iram_save_size); | |
95872f42 JL |
326 | |
327 | *((u32 *)tegra_cpu_lp1_mask) = 1; | |
328 | } | |
329 | ||
330 | static void tegra_suspend_exit_lp1(void) | |
331 | { | |
95872f42 | 332 | /* restore IRAM */ |
fddb770d | 333 | memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr, |
95872f42 JL |
334 | iram_save_size); |
335 | ||
336 | *(u32 *)tegra_cpu_lp1_mask = 0; | |
337 | } | |
338 | ||
c8c2e606 JL |
339 | static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { |
340 | [TEGRA_SUSPEND_NONE] = "none", | |
341 | [TEGRA_SUSPEND_LP2] = "LP2", | |
342 | [TEGRA_SUSPEND_LP1] = "LP1", | |
343 | [TEGRA_SUSPEND_LP0] = "LP0", | |
344 | }; | |
345 | ||
8bd26e3a | 346 | static int tegra_suspend_enter(suspend_state_t state) |
c8c2e606 JL |
347 | { |
348 | enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); | |
349 | ||
350 | if (WARN_ON(mode < TEGRA_SUSPEND_NONE || | |
351 | mode >= TEGRA_MAX_SUSPEND_MODE)) | |
352 | return -EINVAL; | |
353 | ||
354 | pr_info("Entering suspend state %s\n", lp_state[mode]); | |
355 | ||
7232398a | 356 | tegra_pm_set(mode); |
c8c2e606 JL |
357 | |
358 | local_fiq_disable(); | |
359 | ||
360 | suspend_cpu_complex(); | |
361 | switch (mode) { | |
95872f42 JL |
362 | case TEGRA_SUSPEND_LP1: |
363 | tegra_suspend_enter_lp1(); | |
364 | break; | |
c8c2e606 | 365 | case TEGRA_SUSPEND_LP2: |
1f3e18ec | 366 | tegra_pm_set_cpu_in_lp2(); |
c8c2e606 JL |
367 | break; |
368 | default: | |
369 | break; | |
370 | } | |
371 | ||
95872f42 | 372 | cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func); |
c8c2e606 | 373 | |
78ee399f DO |
374 | /* |
375 | * Resume L2 cache if it wasn't re-enabled early during resume, | |
376 | * which is the case for Tegra30 that has to re-enable the cache | |
377 | * via firmware call. In other cases cache is already enabled and | |
378 | * hence re-enabling is a no-op. | |
379 | */ | |
380 | outer_resume(); | |
381 | ||
c8c2e606 | 382 | switch (mode) { |
95872f42 JL |
383 | case TEGRA_SUSPEND_LP1: |
384 | tegra_suspend_exit_lp1(); | |
385 | break; | |
c8c2e606 | 386 | case TEGRA_SUSPEND_LP2: |
1f3e18ec | 387 | tegra_pm_clear_cpu_in_lp2(); |
c8c2e606 JL |
388 | break; |
389 | default: | |
390 | break; | |
391 | } | |
392 | restore_cpu_complex(); | |
393 | ||
394 | local_fiq_enable(); | |
395 | ||
38743e41 DO |
396 | call_firmware_op(prepare_idle, TF_PM_MODE_NONE); |
397 | ||
c8c2e606 JL |
398 | return 0; |
399 | } | |
400 | ||
401 | static const struct platform_suspend_ops tegra_suspend_ops = { | |
402 | .valid = suspend_valid_only_mem, | |
403 | .enter = tegra_suspend_enter, | |
404 | }; | |
405 | ||
9c93ccfc | 406 | void tegra_pm_init_suspend(void) |
c8c2e606 | 407 | { |
95872f42 JL |
408 | enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode(); |
409 | ||
410 | if (mode == TEGRA_SUSPEND_NONE) | |
c8c2e606 JL |
411 | return; |
412 | ||
bf91add4 | 413 | tegra_tear_down_cpu_init(); |
c8c2e606 | 414 | |
95872f42 JL |
415 | if (mode >= TEGRA_SUSPEND_LP1) { |
416 | if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) { | |
417 | pr_err("%s: unable to allocate memory for SDRAM" | |
418 | "self-refresh -- LP0/LP1 unavailable\n", | |
419 | __func__); | |
420 | tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2); | |
421 | mode = TEGRA_SUSPEND_LP2; | |
422 | } | |
423 | } | |
424 | ||
425 | /* set up sleep function for cpu_suspend */ | |
426 | switch (mode) { | |
427 | case TEGRA_SUSPEND_LP1: | |
428 | tegra_sleep_func = tegra_sleep_core; | |
429 | break; | |
430 | case TEGRA_SUSPEND_LP2: | |
431 | tegra_sleep_func = tegra_sleep_cpu; | |
432 | break; | |
433 | default: | |
434 | break; | |
435 | } | |
436 | ||
c8c2e606 JL |
437 | suspend_set_ops(&tegra_suspend_ops); |
438 | } | |
859a6f6e DO |
439 | |
440 | int tegra_pm_park_secondary_cpu(unsigned long cpu) | |
441 | { | |
442 | if (cpu > 0) { | |
443 | tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS); | |
444 | ||
445 | if (tegra_get_chip_id() == TEGRA20) | |
446 | tegra20_hotplug_shutdown(); | |
447 | else | |
448 | tegra30_hotplug_shutdown(); | |
449 | } | |
450 | ||
451 | return -EINVAL; | |
452 | } | |
d457ef35 | 453 | #endif |