[linux-2.6-block.git] / arch / arm / mach-tegra / pm.c

/*
 * CPU complex suspend & resume functions for Tegra SoCs
 *
 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/cpumask.h>
#include <linux/delay.h>
#include <linux/cpu_pm.h>
#include <linux/suspend.h>
#include <linux/err.h>
#include <linux/clk/tegra.h>

#include <asm/smp_plat.h>
#include <asm/cacheflush.h>
#include <asm/suspend.h>
#include <asm/idmap.h>
#include <asm/proc-fns.h>
#include <asm/tlbflush.h>

#include "iomap.h"
#include "reset.h"
#include "flowctrl.h"
#include "fuse.h"
#include "pm.h"
#include "pmc.h"
#include "sleep.h"

#ifdef CONFIG_PM_SLEEP
static DEFINE_SPINLOCK(tegra_lp2_lock);
static u32 iram_save_size;
static void *iram_save_addr;
struct tegra_lp1_iram tegra_lp1_iram;
void (*tegra_tear_down_cpu)(void);
void (*tegra_sleep_core_finish)(unsigned long v2p);
static int (*tegra_sleep_func)(unsigned long v2p);

static void tegra_tear_down_cpu_init(void)
{
	switch (tegra_chip_id) {
	case TEGRA20:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
			tegra_tear_down_cpu = tegra20_tear_down_cpu;
		break;
	case TEGRA30:
	case TEGRA114:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
			tegra_tear_down_cpu = tegra30_tear_down_cpu;
		break;
	}
}

/*
 * restore_cpu_complex
 *
 * restores cpu clock setting, clears flow controller
 *
 * Always called on CPU 0.
 */
static void restore_cpu_complex(void)
{
	int cpu = smp_processor_id();

	BUG_ON(cpu != 0);

#ifdef CONFIG_SMP
	cpu = cpu_logical_map(cpu);
#endif

	/* Restore the CPU clock settings */
	tegra_cpu_clock_resume();

	flowctrl_cpu_suspend_exit(cpu);
}

/*
 * suspend_cpu_complex
 *
 * saves pll state for use by restart_plls, prepares flow controller for
 * transition to suspend state
 *
 * Must always be called on cpu 0.
 */
static void suspend_cpu_complex(void)
{
	int cpu = smp_processor_id();

	BUG_ON(cpu != 0);

#ifdef CONFIG_SMP
	cpu = cpu_logical_map(cpu);
#endif

	/* Save the CPU clock settings */
	tegra_cpu_clock_suspend();

	flowctrl_cpu_suspend_enter(cpu);
}

void tegra_clear_cpu_in_lp2(void)
{
	int phy_cpu_id = cpu_logical_map(smp_processor_id());
	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;

	spin_lock(&tegra_lp2_lock);

	BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
	*cpu_in_lp2 &= ~BIT(phy_cpu_id);

	spin_unlock(&tegra_lp2_lock);
}

bool tegra_set_cpu_in_lp2(void)
{
	int phy_cpu_id = cpu_logical_map(smp_processor_id());
	bool last_cpu = false;
	cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;

	spin_lock(&tegra_lp2_lock);

	BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
	*cpu_in_lp2 |= BIT(phy_cpu_id);

	if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
		last_cpu = true;
	else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1)
		tegra20_cpu_set_resettable_soon();

	spin_unlock(&tegra_lp2_lock);
	return last_cpu;
}

int tegra_cpu_do_idle(void)
{
	return cpu_do_idle();
}

static int tegra_sleep_cpu(unsigned long v2p)
{
	setup_mm_for_reboot();
	tegra_sleep_cpu_finish(v2p);

	/* should never here */
	BUG();

	return 0;
}

void tegra_idle_lp2_last(void)
{
	tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);

	cpu_cluster_pm_enter();
	suspend_cpu_complex();

	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);

	restore_cpu_complex();
	cpu_cluster_pm_exit();
}

enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
				enum tegra_suspend_mode mode)
{
	/*
	 * The Tegra devices support suspending to LP1 or lower currently.
	 */
	if (mode > TEGRA_SUSPEND_LP1)
		return TEGRA_SUSPEND_LP1;

	return mode;
}

static int tegra_sleep_core(unsigned long v2p)
{
	setup_mm_for_reboot();
	tegra_sleep_core_finish(v2p);

	/* should never here */
	BUG();

	return 0;
}

/*
 * tegra_lp1_iram_hook
 *
 * Hooking the address of LP1 reset vector and SDRAM self-refresh code in
 * SDRAM. These codes not be copied to IRAM in this fuction. We need to
 * copy these code to IRAM before LP0/LP1 suspend and restore the content
 * of IRAM after resume.
 */
static bool tegra_lp1_iram_hook(void)
{
	switch (tegra_chip_id) {
	case TEGRA30:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
			tegra30_lp1_iram_hook();
		break;
	default:
		break;
	}

	if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr)
		return false;

	iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
	iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
	if (!iram_save_addr)
		return false;

	return true;
}

static bool tegra_sleep_core_init(void)
{
	switch (tegra_chip_id) {
	case TEGRA30:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
			tegra30_sleep_core_init();
		break;
	default:
		break;
	}

	if (!tegra_sleep_core_finish)
		return false;

	return true;
}

static void tegra_suspend_enter_lp1(void)
{
	tegra_pmc_suspend();

	/* copy the reset vector & SDRAM shutdown code into IRAM */
	memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA),
		iram_save_size);
	memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr,
		iram_save_size);

	*((u32 *)tegra_cpu_lp1_mask) = 1;
}

static void tegra_suspend_exit_lp1(void)
{
	tegra_pmc_resume();

	/* restore IRAM */
	memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr,
		iram_save_size);

	*(u32 *)tegra_cpu_lp1_mask = 0;
}

static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
	[TEGRA_SUSPEND_NONE] = "none",
	[TEGRA_SUSPEND_LP2] = "LP2",
	[TEGRA_SUSPEND_LP1] = "LP1",
	[TEGRA_SUSPEND_LP0] = "LP0",
};

static int __cpuinit tegra_suspend_enter(suspend_state_t state)
{
	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();

	if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
		    mode >= TEGRA_MAX_SUSPEND_MODE))
		return -EINVAL;

	pr_info("Entering suspend state %s\n", lp_state[mode]);

	tegra_pmc_pm_set(mode);

	local_fiq_disable();

	suspend_cpu_complex();
	switch (mode) {
	case TEGRA_SUSPEND_LP1:
		tegra_suspend_enter_lp1();
		break;
	case TEGRA_SUSPEND_LP2:
		tegra_set_cpu_in_lp2();
		break;
	default:
		break;
	}

	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);

	switch (mode) {
	case TEGRA_SUSPEND_LP1:
		tegra_suspend_exit_lp1();
		break;
	case TEGRA_SUSPEND_LP2:
		tegra_clear_cpu_in_lp2();
		break;
	default:
		break;
	}
	restore_cpu_complex();

	local_fiq_enable();

	return 0;
}

static const struct platform_suspend_ops tegra_suspend_ops = {
	.valid		= suspend_valid_only_mem,
	.enter		= tegra_suspend_enter,
};

void __init tegra_init_suspend(void)
{
	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();

	if (mode == TEGRA_SUSPEND_NONE)
		return;

	tegra_tear_down_cpu_init();
	tegra_pmc_suspend_init();

	if (mode >= TEGRA_SUSPEND_LP1) {
		if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) {
			pr_err("%s: unable to allocate memory for SDRAM"
			       "self-refresh -- LP0/LP1 unavailable\n",
			       __func__);
			tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
			mode = TEGRA_SUSPEND_LP2;
		}
	}

	/* set up sleep function for cpu_suspend */
	switch (mode) {
	case TEGRA_SUSPEND_LP1:
		tegra_sleep_func = tegra_sleep_core;
		break;
	case TEGRA_SUSPEND_LP2:
		tegra_sleep_func = tegra_sleep_cpu;
		break;
	default:
		break;
	}

	suspend_set_ops(&tegra_suspend_ops);
}
#endif
Commit	Line	Data
d457ef35 JL	1	/*
	2	* CPU complex suspend & resume functions for Tegra SoCs
	3	*
	4	* Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/spinlock.h>
	21	#include <linux/io.h>
	22	#include <linux/cpumask.h>
d552920a JL	23	#include <linux/delay.h>
d552920a JL	24	#include <linux/cpu_pm.h>
c8c2e606	25	#include <linux/suspend.h>
d552920a	26	#include <linux/err.h>
89572c77	27	#include <linux/clk/tegra.h>
d552920a JL	28
	29	#include <asm/smp_plat.h>
	30	#include <asm/cacheflush.h>
	31	#include <asm/suspend.h>
	32	#include <asm/idmap.h>
	33	#include <asm/proc-fns.h>
	34	#include <asm/tlbflush.h>
d457ef35 JL	35
	36	#include "iomap.h"
	37	#include "reset.h"
d552920a	38	#include "flowctrl.h"
5c1350bd	39	#include "fuse.h"
95872f42	40	#include "pm.h"
0337c3e0	41	#include "pmc.h"
d552920a	42	#include "sleep.h"
d552920a	43
d457ef35	44	#ifdef CONFIG_PM_SLEEP
d457ef35	45	static DEFINE_SPINLOCK(tegra_lp2_lock);
95872f42 JL	46	static u32 iram_save_size;
	47	static void *iram_save_addr;
	48	struct tegra_lp1_iram tegra_lp1_iram;
d552920a	49	void (*tegra_tear_down_cpu)(void);
95872f42 JL	50	void (*tegra_sleep_core_finish)(unsigned long v2p);
95872f42 JL	51	static int (*tegra_sleep_func)(unsigned long v2p);
d457ef35	52
bf91add4 JL	53	static void tegra_tear_down_cpu_init(void)
	54	{
	55	switch (tegra_chip_id) {
	56	case TEGRA20:
	57	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
	58	tegra_tear_down_cpu = tegra20_tear_down_cpu;
	59	break;
	60	case TEGRA30:
b573ad9f JL	61	case TEGRA114:
	62	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) \|\|
	63	IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
bf91add4 JL	64	tegra_tear_down_cpu = tegra30_tear_down_cpu;
	65	break;
	66	}
	67	}
	68
d552920a JL	69	/*
	70	* restore_cpu_complex
	71	*
	72	* restores cpu clock setting, clears flow controller
	73	*
	74	* Always called on CPU 0.
	75	*/
	76	static void restore_cpu_complex(void)
	77	{
	78	int cpu = smp_processor_id();
	79
	80	BUG_ON(cpu != 0);
	81
	82	#ifdef CONFIG_SMP
	83	cpu = cpu_logical_map(cpu);
	84	#endif
	85
	86	/* Restore the CPU clock settings */
	87	tegra_cpu_clock_resume();
	88
	89	flowctrl_cpu_suspend_exit(cpu);
d552920a JL	90	}
	91
	92	/*
	93	* suspend_cpu_complex
	94	*
	95	* saves pll state for use by restart_plls, prepares flow controller for
	96	* transition to suspend state
	97	*
	98	* Must always be called on cpu 0.
	99	*/
	100	static void suspend_cpu_complex(void)
	101	{
	102	int cpu = smp_processor_id();
	103
	104	BUG_ON(cpu != 0);
	105
	106	#ifdef CONFIG_SMP
	107	cpu = cpu_logical_map(cpu);
	108	#endif
	109
	110	/* Save the CPU clock settings */
	111	tegra_cpu_clock_suspend();
	112
	113	flowctrl_cpu_suspend_enter(cpu);
d552920a JL	114	}
d552920a JL	115
8f6a0b65	116	void tegra_clear_cpu_in_lp2(void)
d457ef35	117	{
8f6a0b65	118	int phy_cpu_id = cpu_logical_map(smp_processor_id());
d457ef35 JL	119	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
	120
	121	spin_lock(&tegra_lp2_lock);
	122
	123	BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
	124	*cpu_in_lp2 &= ~BIT(phy_cpu_id);
	125
	126	spin_unlock(&tegra_lp2_lock);
	127	}
	128
8f6a0b65	129	bool tegra_set_cpu_in_lp2(void)
d457ef35	130	{
8f6a0b65	131	int phy_cpu_id = cpu_logical_map(smp_processor_id());
d457ef35 JL	132	bool last_cpu = false;
	133	cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
	134	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
	135
	136	spin_lock(&tegra_lp2_lock);
	137
	138	BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
	139	*cpu_in_lp2 \|= BIT(phy_cpu_id);
	140
	141	if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
	142	last_cpu = true;
5c1350bd JL	143	else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1)
5c1350bd JL	144	tegra20_cpu_set_resettable_soon();
d457ef35 JL	145
	146	spin_unlock(&tegra_lp2_lock);
	147	return last_cpu;
	148	}
d552920a	149
2058842e AB	150	int tegra_cpu_do_idle(void)
	151	{
	152	return cpu_do_idle();
	153	}
	154
d552920a JL	155	static int tegra_sleep_cpu(unsigned long v2p)
d552920a JL	156	{
6affb482	157	setup_mm_for_reboot();
d552920a JL	158	tegra_sleep_cpu_finish(v2p);
	159
	160	/* should never here */
	161	BUG();
	162
	163	return 0;
	164	}
	165
4d82d058	166	void tegra_idle_lp2_last(void)
d552920a	167	{
c8c2e606	168	tegra_pmc_pm_set(TEGRA_SUSPEND_LP2);
d552920a JL	169
	170	cpu_cluster_pm_enter();
	171	suspend_cpu_complex();
d552920a JL	172
	173	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
	174
d552920a JL	175	restore_cpu_complex();
	176	cpu_cluster_pm_exit();
	177	}
c8c2e606 JL	178
	179	enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
	180	enum tegra_suspend_mode mode)
	181	{
c8c2e606	182	/*
95872f42	183	* The Tegra devices support suspending to LP1 or lower currently.
c8c2e606	184	*/
95872f42 JL	185	if (mode > TEGRA_SUSPEND_LP1)
95872f42 JL	186	return TEGRA_SUSPEND_LP1;
c8c2e606 JL	187
	188	return mode;
	189	}
	190
95872f42 JL	191	static int tegra_sleep_core(unsigned long v2p)
	192	{
	193	setup_mm_for_reboot();
	194	tegra_sleep_core_finish(v2p);
	195
	196	/* should never here */
	197	BUG();
	198
	199	return 0;
	200	}
	201
	202	/*
	203	* tegra_lp1_iram_hook
	204	*
	205	* Hooking the address of LP1 reset vector and SDRAM self-refresh code in
	206	* SDRAM. These codes not be copied to IRAM in this fuction. We need to
	207	* copy these code to IRAM before LP0/LP1 suspend and restore the content
	208	* of IRAM after resume.
	209	*/
	210	static bool tegra_lp1_iram_hook(void)
	211	{
e7a932b1 JL	212	switch (tegra_chip_id) {
	213	case TEGRA30:
	214	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
	215	tegra30_lp1_iram_hook();
	216	break;
	217	default:
	218	break;
	219	}
	220
95872f42 JL	221	if (!tegra_lp1_iram.start_addr \|\| !tegra_lp1_iram.end_addr)
	222	return false;
	223
	224	iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
	225	iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
	226	if (!iram_save_addr)
	227	return false;
	228
	229	return true;
	230	}
	231
	232	static bool tegra_sleep_core_init(void)
	233	{
e7a932b1 JL	234	switch (tegra_chip_id) {
	235	case TEGRA30:
	236	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
	237	tegra30_sleep_core_init();
	238	break;
	239	default:
	240	break;
	241	}
	242
95872f42 JL	243	if (!tegra_sleep_core_finish)
	244	return false;
	245
	246	return true;
	247	}
	248
	249	static void tegra_suspend_enter_lp1(void)
	250	{
	251	tegra_pmc_suspend();
	252
	253	/* copy the reset vector & SDRAM shutdown code into IRAM */
	254	memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA),
	255	iram_save_size);
	256	memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr,
	257	iram_save_size);
	258
	259	((u32 )tegra_cpu_lp1_mask) = 1;
	260	}
	261
	262	static void tegra_suspend_exit_lp1(void)
	263	{
	264	tegra_pmc_resume();
	265
	266	/* restore IRAM */
	267	memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr,
	268	iram_save_size);
	269
	270	(u32 )tegra_cpu_lp1_mask = 0;
	271	}
	272
c8c2e606 JL	273	static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
	274	[TEGRA_SUSPEND_NONE] = "none",
	275	[TEGRA_SUSPEND_LP2] = "LP2",
	276	[TEGRA_SUSPEND_LP1] = "LP1",
	277	[TEGRA_SUSPEND_LP0] = "LP0",
	278	};
	279
	280	static int __cpuinit tegra_suspend_enter(suspend_state_t state)
	281	{
	282	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
	283
	284	if (WARN_ON(mode < TEGRA_SUSPEND_NONE \|\|
	285	mode >= TEGRA_MAX_SUSPEND_MODE))
	286	return -EINVAL;
	287
	288	pr_info("Entering suspend state %s\n", lp_state[mode]);
	289
	290	tegra_pmc_pm_set(mode);
	291
	292	local_fiq_disable();
	293
	294	suspend_cpu_complex();
	295	switch (mode) {
95872f42 JL	296	case TEGRA_SUSPEND_LP1:
	297	tegra_suspend_enter_lp1();
	298	break;
c8c2e606	299	case TEGRA_SUSPEND_LP2:
8f6a0b65	300	tegra_set_cpu_in_lp2();
c8c2e606 JL	301	break;
	302	default:
	303	break;
	304	}
	305
95872f42	306	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
c8c2e606 JL	307
c8c2e606 JL	308	switch (mode) {
95872f42 JL	309	case TEGRA_SUSPEND_LP1:
	310	tegra_suspend_exit_lp1();
	311	break;
c8c2e606	312	case TEGRA_SUSPEND_LP2:
8f6a0b65	313	tegra_clear_cpu_in_lp2();
c8c2e606 JL	314	break;
	315	default:
	316	break;
	317	}
	318	restore_cpu_complex();
	319
	320	local_fiq_enable();
	321
	322	return 0;
	323	}
	324
	325	static const struct platform_suspend_ops tegra_suspend_ops = {
	326	.valid = suspend_valid_only_mem,
	327	.enter = tegra_suspend_enter,
	328	};
	329
	330	void __init tegra_init_suspend(void)
	331	{
95872f42 JL	332	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
	333
	334	if (mode == TEGRA_SUSPEND_NONE)
c8c2e606 JL	335	return;
c8c2e606 JL	336
bf91add4	337	tegra_tear_down_cpu_init();
c8c2e606 JL	338	tegra_pmc_suspend_init();
c8c2e606 JL	339
95872f42 JL	340	if (mode >= TEGRA_SUSPEND_LP1) {
	341	if (!tegra_lp1_iram_hook() \|\| !tegra_sleep_core_init()) {
	342	pr_err("%s: unable to allocate memory for SDRAM"
	343	"self-refresh -- LP0/LP1 unavailable\n",
	344	__func__);
	345	tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
	346	mode = TEGRA_SUSPEND_LP2;
	347	}
	348	}
	349
	350	/* set up sleep function for cpu_suspend */
	351	switch (mode) {
	352	case TEGRA_SUSPEND_LP1:
	353	tegra_sleep_func = tegra_sleep_core;
	354	break;
	355	case TEGRA_SUSPEND_LP2:
	356	tegra_sleep_func = tegra_sleep_cpu;
	357	break;
	358	default:
	359	break;
	360	}
	361
c8c2e606 JL	362	suspend_set_ops(&tegra_suspend_ops);
c8c2e606 JL	363	}
d457ef35	364	#endif