[linux-2.6-block.git] / arch / arm / mach-tegra / pm.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * CPU complex suspend & resume functions for Tegra SoCs
 *
 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
 */

#include <linux/clk/tegra.h>
#include <linux/cpumask.h>
#include <linux/cpu_pm.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/suspend.h>

#include <linux/firmware/trusted_foundations.h>

#include <soc/tegra/flowctrl.h>
#include <soc/tegra/fuse.h>
#include <soc/tegra/pm.h>
#include <soc/tegra/pmc.h>

#include <asm/cacheflush.h>
#include <asm/firmware.h>
#include <asm/idmap.h>
#include <asm/proc-fns.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include <asm/tlbflush.h>

#include "iomap.h"
#include "pm.h"
#include "reset.h"
#include "sleep.h"

#ifdef CONFIG_PM_SLEEP
static DEFINE_SPINLOCK(tegra_lp2_lock);
static u32 iram_save_size;
static void *iram_save_addr;
struct tegra_lp1_iram tegra_lp1_iram;
void (*tegra_tear_down_cpu)(void);
void (*tegra_sleep_core_finish)(unsigned long v2p);
static int (*tegra_sleep_func)(unsigned long v2p);

static void tegra_tear_down_cpu_init(void)
{
	switch (tegra_get_chip_id()) {
	case TEGRA20:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
			tegra_tear_down_cpu = tegra20_tear_down_cpu;
		break;
	case TEGRA30:
	case TEGRA114:
	case TEGRA124:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
			tegra_tear_down_cpu = tegra30_tear_down_cpu;
		break;
	}
}

/*
 * restore_cpu_complex
 *
 * restores cpu clock setting, clears flow controller
 *
 * Always called on CPU 0.
 */
static void restore_cpu_complex(void)
{
	int cpu = smp_processor_id();

	BUG_ON(cpu != 0);

#ifdef CONFIG_SMP
	cpu = cpu_logical_map(cpu);
#endif

	/* Restore the CPU clock settings */
	tegra_cpu_clock_resume();

	flowctrl_cpu_suspend_exit(cpu);
}

/*
 * suspend_cpu_complex
 *
 * saves pll state for use by restart_plls, prepares flow controller for
 * transition to suspend state
 *
 * Must always be called on cpu 0.
 */
static void suspend_cpu_complex(void)
{
	int cpu = smp_processor_id();

	BUG_ON(cpu != 0);

#ifdef CONFIG_SMP
	cpu = cpu_logical_map(cpu);
#endif

	/* Save the CPU clock settings */
	tegra_cpu_clock_suspend();

	flowctrl_cpu_suspend_enter(cpu);
}

void tegra_clear_cpu_in_lp2(void)
{
	int phy_cpu_id = cpu_logical_map(smp_processor_id());
	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;

	spin_lock(&tegra_lp2_lock);

	BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
	*cpu_in_lp2 &= ~BIT(phy_cpu_id);

	spin_unlock(&tegra_lp2_lock);
}

bool tegra_set_cpu_in_lp2(void)
{
	int phy_cpu_id = cpu_logical_map(smp_processor_id());
	bool last_cpu = false;
	cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;

	spin_lock(&tegra_lp2_lock);

	BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
	*cpu_in_lp2 |= BIT(phy_cpu_id);

	if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
		last_cpu = true;
	else if (tegra_get_chip_id() == TEGRA20 && phy_cpu_id == 1)
		tegra20_cpu_set_resettable_soon();

	spin_unlock(&tegra_lp2_lock);
	return last_cpu;
}

int tegra_cpu_do_idle(void)
{
	return cpu_do_idle();
}

static int tegra_sleep_cpu(unsigned long v2p)
{
	/*
	 * L2 cache disabling using kernel API only allowed when all
	 * secondary CPU's are offline. Cache have to be disabled with
	 * MMU-on if cache maintenance is done via Trusted Foundations
	 * firmware. Note that CPUIDLE won't ever enter powergate on Tegra30
	 * if any of secondary CPU's is online and this is the LP2-idle
	 * code-path only for Tegra20/30.
	 */
	if (trusted_foundations_registered())
		outer_disable();

	/*
	 * Note that besides of setting up CPU reset vector this firmware
	 * call may also do the following, depending on the FW version:
	 *  1) Disable L2. But this doesn't matter since we already
	 *     disabled the L2.
	 *  2) Disable D-cache. This need to be taken into account in
	 *     particular by the tegra_disable_clean_inv_dcache() which
	 *     shall avoid the re-disable.
	 */
	call_firmware_op(prepare_idle, TF_PM_MODE_LP2);

	setup_mm_for_reboot();
	tegra_sleep_cpu_finish(v2p);

	/* should never here */
	BUG();

	return 0;
}

static void tegra_pm_set(enum tegra_suspend_mode mode)
{
	u32 value;

	switch (tegra_get_chip_id()) {
	case TEGRA20:
	case TEGRA30:
		break;
	default:
		/* Turn off CRAIL */
		value = flowctrl_read_cpu_csr(0);
		value &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
		value |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
		flowctrl_write_cpu_csr(0, value);
		break;
	}

	tegra_pmc_enter_suspend_mode(mode);
}

void tegra_idle_lp2_last(void)
{
	tegra_pm_set(TEGRA_SUSPEND_LP2);

	cpu_cluster_pm_enter();
	suspend_cpu_complex();

	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);

	/*
	 * Resume L2 cache if it wasn't re-enabled early during resume,
	 * which is the case for Tegra30 that has to re-enable the cache
	 * via firmware call. In other cases cache is already enabled and
	 * hence re-enabling is a no-op. This is always a no-op on Tegra114+.
	 */
	outer_resume();

	restore_cpu_complex();
	cpu_cluster_pm_exit();
}

enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
				enum tegra_suspend_mode mode)
{
	/*
	 * The Tegra devices support suspending to LP1 or lower currently.
	 */
	if (mode > TEGRA_SUSPEND_LP1)
		return TEGRA_SUSPEND_LP1;

	return mode;
}

static int tegra_sleep_core(unsigned long v2p)
{
	/*
	 * Cache have to be disabled with MMU-on if cache maintenance is done
	 * via Trusted Foundations firmware. This is a no-op on Tegra114+.
	 */
	if (trusted_foundations_registered())
		outer_disable();

	call_firmware_op(prepare_idle, TF_PM_MODE_LP1);

	setup_mm_for_reboot();
	tegra_sleep_core_finish(v2p);

	/* should never here */
	BUG();

	return 0;
}

/*
 * tegra_lp1_iram_hook
 *
 * Hooking the address of LP1 reset vector and SDRAM self-refresh code in
 * SDRAM. These codes not be copied to IRAM in this fuction. We need to
 * copy these code to IRAM before LP0/LP1 suspend and restore the content
 * of IRAM after resume.
 */
static bool tegra_lp1_iram_hook(void)
{
	switch (tegra_get_chip_id()) {
	case TEGRA20:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
			tegra20_lp1_iram_hook();
		break;
	case TEGRA30:
	case TEGRA114:
	case TEGRA124:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
			tegra30_lp1_iram_hook();
		break;
	default:
		break;
	}

	if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr)
		return false;

	iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
	iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
	if (!iram_save_addr)
		return false;

	return true;
}

static bool tegra_sleep_core_init(void)
{
	switch (tegra_get_chip_id()) {
	case TEGRA20:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
			tegra20_sleep_core_init();
		break;
	case TEGRA30:
	case TEGRA114:
	case TEGRA124:
		if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
		    IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
			tegra30_sleep_core_init();
		break;
	default:
		break;
	}

	if (!tegra_sleep_core_finish)
		return false;

	return true;
}

static void tegra_suspend_enter_lp1(void)
{
	/* copy the reset vector & SDRAM shutdown code into IRAM */
	memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
		iram_save_size);
	memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
		tegra_lp1_iram.start_addr, iram_save_size);

	*((u32 *)tegra_cpu_lp1_mask) = 1;
}

static void tegra_suspend_exit_lp1(void)
{
	/* restore IRAM */
	memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr,
		iram_save_size);

	*(u32 *)tegra_cpu_lp1_mask = 0;
}

static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
	[TEGRA_SUSPEND_NONE] = "none",
	[TEGRA_SUSPEND_LP2] = "LP2",
	[TEGRA_SUSPEND_LP1] = "LP1",
	[TEGRA_SUSPEND_LP0] = "LP0",
};

static int tegra_suspend_enter(suspend_state_t state)
{
	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();

	if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
		    mode >= TEGRA_MAX_SUSPEND_MODE))
		return -EINVAL;

	pr_info("Entering suspend state %s\n", lp_state[mode]);

	tegra_pm_set(mode);

	local_fiq_disable();

	suspend_cpu_complex();
	switch (mode) {
	case TEGRA_SUSPEND_LP1:
		tegra_suspend_enter_lp1();
		break;
	case TEGRA_SUSPEND_LP2:
		tegra_set_cpu_in_lp2();
		break;
	default:
		break;
	}

	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);

	/*
	 * Resume L2 cache if it wasn't re-enabled early during resume,
	 * which is the case for Tegra30 that has to re-enable the cache
	 * via firmware call. In other cases cache is already enabled and
	 * hence re-enabling is a no-op.
	 */
	outer_resume();

	switch (mode) {
	case TEGRA_SUSPEND_LP1:
		tegra_suspend_exit_lp1();
		break;
	case TEGRA_SUSPEND_LP2:
		tegra_clear_cpu_in_lp2();
		break;
	default:
		break;
	}
	restore_cpu_complex();

	local_fiq_enable();

	return 0;
}

static const struct platform_suspend_ops tegra_suspend_ops = {
	.valid		= suspend_valid_only_mem,
	.enter		= tegra_suspend_enter,
};

void __init tegra_init_suspend(void)
{
	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();

	if (mode == TEGRA_SUSPEND_NONE)
		return;

	tegra_tear_down_cpu_init();

	if (mode >= TEGRA_SUSPEND_LP1) {
		if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) {
			pr_err("%s: unable to allocate memory for SDRAM"
			       "self-refresh -- LP0/LP1 unavailable\n",
			       __func__);
			tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
			mode = TEGRA_SUSPEND_LP2;
		}
	}

	/* set up sleep function for cpu_suspend */
	switch (mode) {
	case TEGRA_SUSPEND_LP1:
		tegra_sleep_func = tegra_sleep_core;
		break;
	case TEGRA_SUSPEND_LP2:
		tegra_sleep_func = tegra_sleep_cpu;
		break;
	default:
		break;
	}

	suspend_set_ops(&tegra_suspend_ops);
}
#endif
Commit	Line	Data
9952f691	1	// SPDX-License-Identifier: GPL-2.0-only
d457ef35 JL	2	/*
	3	* CPU complex suspend & resume functions for Tegra SoCs
	4	*
	5	* Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
d457ef35 JL	6	*/
d457ef35 JL	7
a0524acc	8	#include <linux/clk/tegra.h>
d457ef35	9	#include <linux/cpumask.h>
d552920a	10	#include <linux/cpu_pm.h>
a0524acc	11	#include <linux/delay.h>
d552920a	12	#include <linux/err.h>
a0524acc TR	13	#include <linux/io.h>
a0524acc TR	14	#include <linux/kernel.h>
1ff6bbfd	15	#include <linux/slab.h>
a0524acc TR	16	#include <linux/spinlock.h>
a0524acc TR	17	#include <linux/suspend.h>
d552920a	18
4cb5d9ec TR	19	#include <linux/firmware/trusted_foundations.h>
4cb5d9ec TR	20
7e10cf74	21	#include <soc/tegra/flowctrl.h>
304664ea	22	#include <soc/tegra/fuse.h>
7232398a TR	23	#include <soc/tegra/pm.h>
7232398a TR	24	#include <soc/tegra/pmc.h>
304664ea	25
d552920a	26	#include <asm/cacheflush.h>
78ee399f	27	#include <asm/firmware.h>
d552920a JL	28	#include <asm/idmap.h>
d552920a JL	29	#include <asm/proc-fns.h>
a0524acc TR	30	#include <asm/smp_plat.h>
a0524acc TR	31	#include <asm/suspend.h>
d552920a	32	#include <asm/tlbflush.h>
d457ef35	33
a0524acc	34	#include "iomap.h"
a0524acc TR	35	#include "pm.h"
a0524acc TR	36	#include "reset.h"
d552920a	37	#include "sleep.h"
d552920a	38
d457ef35	39	#ifdef CONFIG_PM_SLEEP
d457ef35	40	static DEFINE_SPINLOCK(tegra_lp2_lock);
95872f42 JL	41	static u32 iram_save_size;
	42	static void *iram_save_addr;
	43	struct tegra_lp1_iram tegra_lp1_iram;
d552920a	44	void (*tegra_tear_down_cpu)(void);
95872f42 JL	45	void (*tegra_sleep_core_finish)(unsigned long v2p);
95872f42 JL	46	static int (*tegra_sleep_func)(unsigned long v2p);
d457ef35	47
bf91add4 JL	48	static void tegra_tear_down_cpu_init(void)
bf91add4 JL	49	{
304664ea	50	switch (tegra_get_chip_id()) {
bf91add4 JL	51	case TEGRA20:
	52	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
	53	tegra_tear_down_cpu = tegra20_tear_down_cpu;
	54	break;
	55	case TEGRA30:
b573ad9f	56	case TEGRA114:
f0c4ac13	57	case TEGRA124:
b573ad9f	58	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) \|\|
f0c4ac13 JL	59	IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) \|\|
f0c4ac13 JL	60	IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
bf91add4 JL	61	tegra_tear_down_cpu = tegra30_tear_down_cpu;
	62	break;
	63	}
	64	}
	65
d552920a JL	66	/*
	67	* restore_cpu_complex
	68	*
	69	* restores cpu clock setting, clears flow controller
	70	*
	71	* Always called on CPU 0.
	72	*/
	73	static void restore_cpu_complex(void)
	74	{
	75	int cpu = smp_processor_id();
	76
	77	BUG_ON(cpu != 0);
	78
	79	#ifdef CONFIG_SMP
	80	cpu = cpu_logical_map(cpu);
	81	#endif
	82
	83	/* Restore the CPU clock settings */
	84	tegra_cpu_clock_resume();
	85
	86	flowctrl_cpu_suspend_exit(cpu);
d552920a JL	87	}
	88
	89	/*
	90	* suspend_cpu_complex
	91	*
	92	* saves pll state for use by restart_plls, prepares flow controller for
	93	* transition to suspend state
	94	*
	95	* Must always be called on cpu 0.
	96	*/
	97	static void suspend_cpu_complex(void)
	98	{
	99	int cpu = smp_processor_id();
	100
	101	BUG_ON(cpu != 0);
	102
	103	#ifdef CONFIG_SMP
	104	cpu = cpu_logical_map(cpu);
	105	#endif
	106
	107	/* Save the CPU clock settings */
	108	tegra_cpu_clock_suspend();
	109
	110	flowctrl_cpu_suspend_enter(cpu);
d552920a JL	111	}
d552920a JL	112
8f6a0b65	113	void tegra_clear_cpu_in_lp2(void)
d457ef35	114	{
8f6a0b65	115	int phy_cpu_id = cpu_logical_map(smp_processor_id());
d457ef35 JL	116	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
	117
	118	spin_lock(&tegra_lp2_lock);
	119
	120	BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
	121	*cpu_in_lp2 &= ~BIT(phy_cpu_id);
	122
	123	spin_unlock(&tegra_lp2_lock);
	124	}
	125
8f6a0b65	126	bool tegra_set_cpu_in_lp2(void)
d457ef35	127	{
8f6a0b65	128	int phy_cpu_id = cpu_logical_map(smp_processor_id());
d457ef35 JL	129	bool last_cpu = false;
	130	cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
	131	u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
	132
	133	spin_lock(&tegra_lp2_lock);
	134
	135	BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
	136	*cpu_in_lp2 \|= BIT(phy_cpu_id);
	137
	138	if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
	139	last_cpu = true;
304664ea	140	else if (tegra_get_chip_id() == TEGRA20 && phy_cpu_id == 1)
5c1350bd	141	tegra20_cpu_set_resettable_soon();
d457ef35 JL	142
	143	spin_unlock(&tegra_lp2_lock);
	144	return last_cpu;
	145	}
d552920a	146
2058842e AB	147	int tegra_cpu_do_idle(void)
	148	{
	149	return cpu_do_idle();
	150	}
	151
d552920a JL	152	static int tegra_sleep_cpu(unsigned long v2p)
d552920a JL	153	{
78ee399f DO	154	/*
	155	* L2 cache disabling using kernel API only allowed when all
	156	* secondary CPU's are offline. Cache have to be disabled with
	157	* MMU-on if cache maintenance is done via Trusted Foundations
	158	* firmware. Note that CPUIDLE won't ever enter powergate on Tegra30
	159	* if any of secondary CPU's is online and this is the LP2-idle
	160	* code-path only for Tegra20/30.
	161	*/
	162	if (trusted_foundations_registered())
	163	outer_disable();
	164
	165	/*
	166	* Note that besides of setting up CPU reset vector this firmware
	167	* call may also do the following, depending on the FW version:
	168	* 1) Disable L2. But this doesn't matter since we already
	169	* disabled the L2.
	170	* 2) Disable D-cache. This need to be taken into account in
	171	* particular by the tegra_disable_clean_inv_dcache() which
	172	* shall avoid the re-disable.
	173	*/
	174	call_firmware_op(prepare_idle, TF_PM_MODE_LP2);
	175
6affb482	176	setup_mm_for_reboot();
d552920a JL	177	tegra_sleep_cpu_finish(v2p);
	178
	179	/* should never here */
	180	BUG();
	181
	182	return 0;
	183	}
	184
7232398a TR	185	static void tegra_pm_set(enum tegra_suspend_mode mode)
	186	{
	187	u32 value;
	188
	189	switch (tegra_get_chip_id()) {
	190	case TEGRA20:
	191	case TEGRA30:
	192	break;
	193	default:
	194	/* Turn off CRAIL */
	195	value = flowctrl_read_cpu_csr(0);
	196	value &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
	197	value \|= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
	198	flowctrl_write_cpu_csr(0, value);
	199	break;
	200	}
	201
	202	tegra_pmc_enter_suspend_mode(mode);
	203	}
	204
4d82d058	205	void tegra_idle_lp2_last(void)
d552920a	206	{
7232398a	207	tegra_pm_set(TEGRA_SUSPEND_LP2);
d552920a JL	208
	209	cpu_cluster_pm_enter();
	210	suspend_cpu_complex();
d552920a JL	211
	212	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
	213
78ee399f DO	214	/*
	215	* Resume L2 cache if it wasn't re-enabled early during resume,
	216	* which is the case for Tegra30 that has to re-enable the cache
	217	* via firmware call. In other cases cache is already enabled and
	218	* hence re-enabling is a no-op. This is always a no-op on Tegra114+.
	219	*/
	220	outer_resume();
	221
d552920a JL	222	restore_cpu_complex();
	223	cpu_cluster_pm_exit();
	224	}
c8c2e606 JL	225
	226	enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
	227	enum tegra_suspend_mode mode)
	228	{
c8c2e606	229	/*
95872f42	230	* The Tegra devices support suspending to LP1 or lower currently.
c8c2e606	231	*/
95872f42 JL	232	if (mode > TEGRA_SUSPEND_LP1)
95872f42 JL	233	return TEGRA_SUSPEND_LP1;
c8c2e606 JL	234
	235	return mode;
	236	}
	237
95872f42 JL	238	static int tegra_sleep_core(unsigned long v2p)
95872f42 JL	239	{
78ee399f DO	240	/*
	241	* Cache have to be disabled with MMU-on if cache maintenance is done
	242	* via Trusted Foundations firmware. This is a no-op on Tegra114+.
	243	*/
	244	if (trusted_foundations_registered())
	245	outer_disable();
	246
	247	call_firmware_op(prepare_idle, TF_PM_MODE_LP1);
	248
95872f42 JL	249	setup_mm_for_reboot();
	250	tegra_sleep_core_finish(v2p);
	251
	252	/* should never here */
	253	BUG();
	254
	255	return 0;
	256	}
	257
	258	/*
	259	* tegra_lp1_iram_hook
	260	*
	261	* Hooking the address of LP1 reset vector and SDRAM self-refresh code in
	262	* SDRAM. These codes not be copied to IRAM in this fuction. We need to
	263	* copy these code to IRAM before LP0/LP1 suspend and restore the content
	264	* of IRAM after resume.
	265	*/
	266	static bool tegra_lp1_iram_hook(void)
	267	{
304664ea	268	switch (tegra_get_chip_id()) {
731a9274 JL	269	case TEGRA20:
	270	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
	271	tegra20_lp1_iram_hook();
	272	break;
e7a932b1	273	case TEGRA30:
e9f62449	274	case TEGRA114:
f0c4ac13	275	case TEGRA124:
e9f62449	276	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) \|\|
f0c4ac13 JL	277	IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) \|\|
f0c4ac13 JL	278	IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
e7a932b1 JL	279	tegra30_lp1_iram_hook();
	280	break;
	281	default:
	282	break;
	283	}
	284
95872f42 JL	285	if (!tegra_lp1_iram.start_addr \|\| !tegra_lp1_iram.end_addr)
	286	return false;
	287
	288	iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
	289	iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
	290	if (!iram_save_addr)
	291	return false;
	292
	293	return true;
	294	}
	295
	296	static bool tegra_sleep_core_init(void)
	297	{
304664ea	298	switch (tegra_get_chip_id()) {
731a9274 JL	299	case TEGRA20:
	300	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
	301	tegra20_sleep_core_init();
	302	break;
e7a932b1	303	case TEGRA30:
e9f62449	304	case TEGRA114:
f0c4ac13	305	case TEGRA124:
e9f62449	306	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) \|\|
f0c4ac13 JL	307	IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) \|\|
f0c4ac13 JL	308	IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
e7a932b1 JL	309	tegra30_sleep_core_init();
	310	break;
	311	default:
	312	break;
	313	}
	314
95872f42 JL	315	if (!tegra_sleep_core_finish)
	316	return false;
	317
	318	return true;
	319	}
	320
	321	static void tegra_suspend_enter_lp1(void)
	322	{
95872f42	323	/* copy the reset vector & SDRAM shutdown code into IRAM */
fddb770d	324	memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
95872f42	325	iram_save_size);
fddb770d SW	326	memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
fddb770d SW	327	tegra_lp1_iram.start_addr, iram_save_size);
95872f42 JL	328
	329	((u32 )tegra_cpu_lp1_mask) = 1;
	330	}
	331
	332	static void tegra_suspend_exit_lp1(void)
	333	{
95872f42	334	/* restore IRAM */
fddb770d	335	memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr,
95872f42 JL	336	iram_save_size);
	337
	338	(u32 )tegra_cpu_lp1_mask = 0;
	339	}
	340
c8c2e606 JL	341	static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
	342	[TEGRA_SUSPEND_NONE] = "none",
	343	[TEGRA_SUSPEND_LP2] = "LP2",
	344	[TEGRA_SUSPEND_LP1] = "LP1",
	345	[TEGRA_SUSPEND_LP0] = "LP0",
	346	};
	347
8bd26e3a	348	static int tegra_suspend_enter(suspend_state_t state)
c8c2e606 JL	349	{
	350	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
	351
	352	if (WARN_ON(mode < TEGRA_SUSPEND_NONE \|\|
	353	mode >= TEGRA_MAX_SUSPEND_MODE))
	354	return -EINVAL;
	355
	356	pr_info("Entering suspend state %s\n", lp_state[mode]);
	357
7232398a	358	tegra_pm_set(mode);
c8c2e606 JL	359
	360	local_fiq_disable();
	361
	362	suspend_cpu_complex();
	363	switch (mode) {
95872f42 JL	364	case TEGRA_SUSPEND_LP1:
	365	tegra_suspend_enter_lp1();
	366	break;
c8c2e606	367	case TEGRA_SUSPEND_LP2:
8f6a0b65	368	tegra_set_cpu_in_lp2();
c8c2e606 JL	369	break;
	370	default:
	371	break;
	372	}
	373
95872f42	374	cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
c8c2e606	375
78ee399f DO	376	/*
	377	* Resume L2 cache if it wasn't re-enabled early during resume,
	378	* which is the case for Tegra30 that has to re-enable the cache
	379	* via firmware call. In other cases cache is already enabled and
	380	* hence re-enabling is a no-op.
	381	*/
	382	outer_resume();
	383
c8c2e606	384	switch (mode) {
95872f42 JL	385	case TEGRA_SUSPEND_LP1:
	386	tegra_suspend_exit_lp1();
	387	break;
c8c2e606	388	case TEGRA_SUSPEND_LP2:
8f6a0b65	389	tegra_clear_cpu_in_lp2();
c8c2e606 JL	390	break;
	391	default:
	392	break;
	393	}
	394	restore_cpu_complex();
	395
	396	local_fiq_enable();
	397
	398	return 0;
	399	}
	400
	401	static const struct platform_suspend_ops tegra_suspend_ops = {
	402	.valid = suspend_valid_only_mem,
	403	.enter = tegra_suspend_enter,
	404	};
	405
	406	void __init tegra_init_suspend(void)
	407	{
95872f42 JL	408	enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
	409
	410	if (mode == TEGRA_SUSPEND_NONE)
c8c2e606 JL	411	return;
c8c2e606 JL	412
bf91add4	413	tegra_tear_down_cpu_init();
c8c2e606	414
95872f42 JL	415	if (mode >= TEGRA_SUSPEND_LP1) {
	416	if (!tegra_lp1_iram_hook() \|\| !tegra_sleep_core_init()) {
	417	pr_err("%s: unable to allocate memory for SDRAM"
	418	"self-refresh -- LP0/LP1 unavailable\n",
	419	__func__);
	420	tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
	421	mode = TEGRA_SUSPEND_LP2;
	422	}
	423	}
	424
	425	/* set up sleep function for cpu_suspend */
	426	switch (mode) {
	427	case TEGRA_SUSPEND_LP1:
	428	tegra_sleep_func = tegra_sleep_core;
	429	break;
	430	case TEGRA_SUSPEND_LP2:
	431	tegra_sleep_func = tegra_sleep_cpu;
	432	break;
	433	default:
	434	break;
	435	}
	436
c8c2e606 JL	437	suspend_set_ops(&tegra_suspend_ops);
c8c2e606 JL	438	}
d457ef35	439	#endif