[linux-2.6-block.git] / arch / arm / mach-tegra / flowctrl.c

/*
 * arch/arm/mach-tegra/flowctrl.c
 *
 * functions and macros to control the flowcontroller
 *
 * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/cpumask.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include <soc/tegra/fuse.h>

#include "flowctrl.h"

static u8 flowctrl_offset_halt_cpu[] = {
	FLOW_CTRL_HALT_CPU0_EVENTS,
	FLOW_CTRL_HALT_CPU1_EVENTS,
	FLOW_CTRL_HALT_CPU1_EVENTS + 8,
	FLOW_CTRL_HALT_CPU1_EVENTS + 16,
};

static u8 flowctrl_offset_cpu_csr[] = {
	FLOW_CTRL_CPU0_CSR,
	FLOW_CTRL_CPU1_CSR,
	FLOW_CTRL_CPU1_CSR + 8,
	FLOW_CTRL_CPU1_CSR + 16,
};

static void __iomem *tegra_flowctrl_base;

static void flowctrl_update(u8 offset, u32 value)
{
	writel(value, tegra_flowctrl_base + offset);

	/* ensure the update has reached the flow controller */
	wmb();
	readl_relaxed(tegra_flowctrl_base + offset);
}

u32 flowctrl_read_cpu_csr(unsigned int cpuid)
{
	u8 offset = flowctrl_offset_cpu_csr[cpuid];

	return readl(tegra_flowctrl_base + offset);
}

void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
{
	return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
}

void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
{
	return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
}

void flowctrl_cpu_suspend_enter(unsigned int cpuid)
{
	unsigned int reg;
	int i;

	reg = flowctrl_read_cpu_csr(cpuid);
	switch (tegra_get_chip_id()) {
	case TEGRA20:
		/* clear wfe bitmap */
		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
		/* clear wfi bitmap */
		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
		/* pwr gating on wfe */
		reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
		break;
	case TEGRA30:
	case TEGRA114:
	case TEGRA124:
		/* clear wfe bitmap */
		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
		/* clear wfi bitmap */
		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
		/* pwr gating on wfi */
		reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
		break;
	}
	reg |= FLOW_CTRL_CSR_INTR_FLAG;			/* clear intr flag */
	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event flag */
	reg |= FLOW_CTRL_CSR_ENABLE;			/* pwr gating */
	flowctrl_write_cpu_csr(cpuid, reg);

	for (i = 0; i < num_possible_cpus(); i++) {
		if (i == cpuid)
			continue;
		reg = flowctrl_read_cpu_csr(i);
		reg |= FLOW_CTRL_CSR_EVENT_FLAG;
		reg |= FLOW_CTRL_CSR_INTR_FLAG;
		flowctrl_write_cpu_csr(i, reg);
	}
}

void flowctrl_cpu_suspend_exit(unsigned int cpuid)
{
	unsigned int reg;

	/* Disable powergating via flow controller for CPU0 */
	reg = flowctrl_read_cpu_csr(cpuid);
	switch (tegra_get_chip_id()) {
	case TEGRA20:
		/* clear wfe bitmap */
		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
		/* clear wfi bitmap */
		reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
		break;
	case TEGRA30:
	case TEGRA114:
	case TEGRA124:
		/* clear wfe bitmap */
		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
		/* clear wfi bitmap */
		reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
		break;
	}
	reg &= ~FLOW_CTRL_CSR_ENABLE;			/* clear enable */
	reg |= FLOW_CTRL_CSR_INTR_FLAG;			/* clear intr */
	reg |= FLOW_CTRL_CSR_EVENT_FLAG;		/* clear event */
	flowctrl_write_cpu_csr(cpuid, reg);
}

static const struct of_device_id matches[] __initconst = {
	{ .compatible = "nvidia,tegra124-flowctrl" },
	{ .compatible = "nvidia,tegra114-flowctrl" },
	{ .compatible = "nvidia,tegra30-flowctrl" },
	{ .compatible = "nvidia,tegra20-flowctrl" },
	{ }
};

void __init tegra_flowctrl_init(void)
{
	/* hardcoded fallback if device tree node is missing */
	unsigned long base = 0x60007000;
	unsigned long size = SZ_4K;
	struct device_node *np;

	np = of_find_matching_node(NULL, matches);
	if (np) {
		struct resource res;

		if (of_address_to_resource(np, 0, &res) == 0) {
			size = resource_size(&res);
			base = res.start;
		}

		of_node_put(np);
	}

	tegra_flowctrl_base = ioremap_nocache(base, size);
}
Commit	Line	Data
26fe681f PDS	1	/*
	2	* arch/arm/mach-tegra/flowctrl.c
	3	*
	4	* functions and macros to control the flowcontroller
	5	*
	6	* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms and conditions of the GNU General Public License,
	10	* version 2, as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
a0524acc	21	#include <linux/cpumask.h>
26fe681f	22	#include <linux/init.h>
26fe681f	23	#include <linux/io.h>
a0524acc	24	#include <linux/kernel.h>
783944fe TR	25	#include <linux/of.h>
783944fe TR	26	#include <linux/of_address.h>
26fe681f	27
304664ea TR	28	#include <soc/tegra/fuse.h>
304664ea TR	29
26fe681f PDS	30	#include "flowctrl.h"
26fe681f PDS	31
deeb8d19	32	static u8 flowctrl_offset_halt_cpu[] = {
26fe681f PDS	33	FLOW_CTRL_HALT_CPU0_EVENTS,
	34	FLOW_CTRL_HALT_CPU1_EVENTS,
	35	FLOW_CTRL_HALT_CPU1_EVENTS + 8,
	36	FLOW_CTRL_HALT_CPU1_EVENTS + 16,
	37	};
	38
deeb8d19	39	static u8 flowctrl_offset_cpu_csr[] = {
26fe681f PDS	40	FLOW_CTRL_CPU0_CSR,
	41	FLOW_CTRL_CPU1_CSR,
	42	FLOW_CTRL_CPU1_CSR + 8,
	43	FLOW_CTRL_CPU1_CSR + 16,
	44	};
	45
783944fe TR	46	static void __iomem *tegra_flowctrl_base;
783944fe TR	47
26fe681f PDS	48	static void flowctrl_update(u8 offset, u32 value)
26fe681f PDS	49	{
783944fe	50	writel(value, tegra_flowctrl_base + offset);
26fe681f PDS	51
	52	/* ensure the update has reached the flow controller */
	53	wmb();
783944fe	54	readl_relaxed(tegra_flowctrl_base + offset);
26fe681f PDS	55	}
26fe681f PDS	56
01459c69 JL	57	u32 flowctrl_read_cpu_csr(unsigned int cpuid)
	58	{
	59	u8 offset = flowctrl_offset_cpu_csr[cpuid];
01459c69	60
783944fe	61	return readl(tegra_flowctrl_base + offset);
01459c69 JL	62	}
01459c69 JL	63
26fe681f PDS	64	void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
26fe681f PDS	65	{
97e7abc5	66	return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
26fe681f PDS	67	}
	68
	69	void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
	70	{
97e7abc5	71	return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
26fe681f	72	}
01459c69 JL	73
	74	void flowctrl_cpu_suspend_enter(unsigned int cpuid)
	75	{
	76	unsigned int reg;
	77	int i;
	78
	79	reg = flowctrl_read_cpu_csr(cpuid);
304664ea	80	switch (tegra_get_chip_id()) {
afec581c JL	81	case TEGRA20:
	82	/* clear wfe bitmap */
	83	reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
	84	/* clear wfi bitmap */
	85	reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
	86	/* pwr gating on wfe */
	87	reg \|= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
	88	break;
	89	case TEGRA30:
dd6fe9a9	90	case TEGRA114:
f0c4ac13	91	case TEGRA124:
afec581c JL	92	/* clear wfe bitmap */
	93	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
	94	/* clear wfi bitmap */
	95	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
	96	/* pwr gating on wfi */
	97	reg \|= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
	98	break;
	99	}
01459c69 JL	100	reg \|= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
01459c69 JL	101	reg \|= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
01459c69 JL	102	reg \|= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
	103	flowctrl_write_cpu_csr(cpuid, reg);
	104
	105	for (i = 0; i < num_possible_cpus(); i++) {
	106	if (i == cpuid)
	107	continue;
	108	reg = flowctrl_read_cpu_csr(i);
	109	reg \|= FLOW_CTRL_CSR_EVENT_FLAG;
	110	reg \|= FLOW_CTRL_CSR_INTR_FLAG;
	111	flowctrl_write_cpu_csr(i, reg);
	112	}
	113	}
	114
	115	void flowctrl_cpu_suspend_exit(unsigned int cpuid)
	116	{
	117	unsigned int reg;
	118
	119	/* Disable powergating via flow controller for CPU0 */
	120	reg = flowctrl_read_cpu_csr(cpuid);
304664ea	121	switch (tegra_get_chip_id()) {
afec581c JL	122	case TEGRA20:
	123	/* clear wfe bitmap */
	124	reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
	125	/* clear wfi bitmap */
	126	reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
	127	break;
	128	case TEGRA30:
dd6fe9a9	129	case TEGRA114:
f0c4ac13	130	case TEGRA124:
afec581c JL	131	/* clear wfe bitmap */
	132	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
	133	/* clear wfi bitmap */
	134	reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
	135	break;
	136	}
01459c69 JL	137	reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
	138	reg \|= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
	139	reg \|= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
	140	flowctrl_write_cpu_csr(cpuid, reg);
	141	}
783944fe TR	142
	143	static const struct of_device_id matches[] __initconst = {
	144	{ .compatible = "nvidia,tegra124-flowctrl" },
	145	{ .compatible = "nvidia,tegra114-flowctrl" },
	146	{ .compatible = "nvidia,tegra30-flowctrl" },
	147	{ .compatible = "nvidia,tegra20-flowctrl" },
	148	{ }
	149	};
	150
	151	void __init tegra_flowctrl_init(void)
	152	{
	153	/* hardcoded fallback if device tree node is missing */
	154	unsigned long base = 0x60007000;
	155	unsigned long size = SZ_4K;
	156	struct device_node *np;
	157
	158	np = of_find_matching_node(NULL, matches);
	159	if (np) {
	160	struct resource res;
	161
	162	if (of_address_to_resource(np, 0, &res) == 0) {
	163	size = resource_size(&res);
	164	base = res.start;
	165	}
	166
	167	of_node_put(np);
	168	}
	169
	170	tegra_flowctrl_base = ioremap_nocache(base, size);
	171	}