Commit | Line | Data |
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0b25e25b JL |
1 | /* |
2 | * CPU idle driver for Tegra CPUs | |
3 | * | |
4 | * Copyright (c) 2010-2012, NVIDIA Corporation. | |
5 | * Copyright (c) 2011 Google, Inc. | |
6 | * Author: Colin Cross <ccross@android.com> | |
7 | * Gary King <gking@nvidia.com> | |
8 | * | |
9 | * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
17 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
18 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
19 | * more details. | |
20 | */ | |
21 | ||
a0524acc | 22 | #include <linux/clk/tegra.h> |
a0b41224 | 23 | #include <linux/tick.h> |
0b25e25b | 24 | #include <linux/cpuidle.h> |
5c1350bd | 25 | #include <linux/cpu_pm.h> |
a0524acc TR |
26 | #include <linux/kernel.h> |
27 | #include <linux/module.h> | |
0b25e25b JL |
28 | |
29 | #include <asm/cpuidle.h> | |
5c1350bd | 30 | #include <asm/smp_plat.h> |
a0524acc | 31 | #include <asm/suspend.h> |
5c1350bd | 32 | |
a0524acc | 33 | #include "flowctrl.h" |
1d328606 JL |
34 | #include "iomap.h" |
35 | #include "irq.h" | |
a0524acc TR |
36 | #include "pm.h" |
37 | #include "sleep.h" | |
5c1350bd JL |
38 | |
39 | #ifdef CONFIG_PM_SLEEP | |
1d328606 JL |
40 | static bool abort_flag; |
41 | static atomic_t abort_barrier; | |
42 | static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, | |
43 | struct cpuidle_driver *drv, | |
44 | int index); | |
14ad7a11 DL |
45 | #define TEGRA20_MAX_STATES 2 |
46 | #else | |
47 | #define TEGRA20_MAX_STATES 1 | |
5c1350bd JL |
48 | #endif |
49 | ||
0b25e25b JL |
50 | static struct cpuidle_driver tegra_idle_driver = { |
51 | .name = "tegra_idle", | |
52 | .owner = THIS_MODULE, | |
14ad7a11 DL |
53 | .states = { |
54 | ARM_CPUIDLE_WFI_STATE_PWR(600), | |
55 | #ifdef CONFIG_PM_SLEEP | |
56 | { | |
57 | .enter = tegra20_idle_lp2_coupled, | |
58 | .exit_latency = 5000, | |
59 | .target_residency = 10000, | |
60 | .power_usage = 0, | |
b82b6cca | 61 | .flags = CPUIDLE_FLAG_COUPLED, |
14ad7a11 DL |
62 | .name = "powered-down", |
63 | .desc = "CPU power gated", | |
64 | }, | |
65 | #endif | |
66 | }, | |
67 | .state_count = TEGRA20_MAX_STATES, | |
68 | .safe_state_index = 0, | |
0b25e25b JL |
69 | }; |
70 | ||
5c1350bd | 71 | #ifdef CONFIG_PM_SLEEP |
1d328606 JL |
72 | #ifdef CONFIG_SMP |
73 | static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); | |
74 | ||
75 | static int tegra20_reset_sleeping_cpu_1(void) | |
76 | { | |
77 | int ret = 0; | |
78 | ||
79 | tegra_pen_lock(); | |
80 | ||
81 | if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE) | |
82 | tegra20_cpu_shutdown(1); | |
83 | else | |
84 | ret = -EINVAL; | |
85 | ||
86 | tegra_pen_unlock(); | |
87 | ||
88 | return ret; | |
89 | } | |
90 | ||
91 | static void tegra20_wake_cpu1_from_reset(void) | |
92 | { | |
93 | tegra_pen_lock(); | |
94 | ||
95 | tegra20_cpu_clear_resettable(); | |
96 | ||
97 | /* enable cpu clock on cpu */ | |
98 | tegra_enable_cpu_clock(1); | |
99 | ||
100 | /* take the CPU out of reset */ | |
101 | tegra_cpu_out_of_reset(1); | |
102 | ||
103 | /* unhalt the cpu */ | |
104 | flowctrl_write_cpu_halt(1, 0); | |
105 | ||
106 | tegra_pen_unlock(); | |
107 | } | |
108 | ||
109 | static int tegra20_reset_cpu_1(void) | |
110 | { | |
111 | if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1()) | |
112 | return 0; | |
113 | ||
114 | tegra20_wake_cpu1_from_reset(); | |
115 | return -EBUSY; | |
116 | } | |
117 | #else | |
118 | static inline void tegra20_wake_cpu1_from_reset(void) | |
119 | { | |
120 | } | |
121 | ||
122 | static inline int tegra20_reset_cpu_1(void) | |
123 | { | |
124 | return 0; | |
125 | } | |
126 | #endif | |
127 | ||
128 | static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev, | |
129 | struct cpuidle_driver *drv, | |
130 | int index) | |
131 | { | |
1d328606 JL |
132 | while (tegra20_cpu_is_resettable_soon()) |
133 | cpu_relax(); | |
134 | ||
135 | if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready()) | |
136 | return false; | |
137 | ||
a0b41224 | 138 | tick_broadcast_enter(); |
1d328606 | 139 | |
4d82d058 | 140 | tegra_idle_lp2_last(); |
1d328606 | 141 | |
a0b41224 | 142 | tick_broadcast_exit(); |
1d328606 JL |
143 | |
144 | if (cpu_online(1)) | |
145 | tegra20_wake_cpu1_from_reset(); | |
146 | ||
147 | return true; | |
148 | } | |
149 | ||
5c1350bd JL |
150 | #ifdef CONFIG_SMP |
151 | static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, | |
152 | struct cpuidle_driver *drv, | |
153 | int index) | |
154 | { | |
a0b41224 | 155 | tick_broadcast_enter(); |
5c1350bd JL |
156 | |
157 | cpu_suspend(0, tegra20_sleep_cpu_secondary_finish); | |
158 | ||
159 | tegra20_cpu_clear_resettable(); | |
160 | ||
a0b41224 | 161 | tick_broadcast_exit(); |
5c1350bd JL |
162 | |
163 | return true; | |
164 | } | |
165 | #else | |
166 | static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev, | |
167 | struct cpuidle_driver *drv, | |
168 | int index) | |
169 | { | |
170 | return true; | |
171 | } | |
172 | #endif | |
173 | ||
1d328606 JL |
174 | static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev, |
175 | struct cpuidle_driver *drv, | |
176 | int index) | |
5c1350bd | 177 | { |
5c1350bd JL |
178 | bool entered_lp2 = false; |
179 | ||
1d328606 JL |
180 | if (tegra_pending_sgi()) |
181 | ACCESS_ONCE(abort_flag) = true; | |
182 | ||
183 | cpuidle_coupled_parallel_barrier(dev, &abort_barrier); | |
184 | ||
185 | if (abort_flag) { | |
186 | cpuidle_coupled_parallel_barrier(dev, &abort_barrier); | |
187 | abort_flag = false; /* clean flag for next coming */ | |
188 | return -EINTR; | |
189 | } | |
190 | ||
5c1350bd JL |
191 | local_fiq_disable(); |
192 | ||
8f6a0b65 | 193 | tegra_set_cpu_in_lp2(); |
5c1350bd JL |
194 | cpu_pm_enter(); |
195 | ||
8f6a0b65 | 196 | if (dev->cpu == 0) |
1d328606 | 197 | entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index); |
5c1350bd JL |
198 | else |
199 | entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index); | |
200 | ||
201 | cpu_pm_exit(); | |
8f6a0b65 | 202 | tegra_clear_cpu_in_lp2(); |
5c1350bd JL |
203 | |
204 | local_fiq_enable(); | |
205 | ||
206 | smp_rmb(); | |
207 | ||
208 | return entered_lp2 ? index : 0; | |
209 | } | |
210 | #endif | |
211 | ||
b4f17375 SW |
212 | /* |
213 | * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether | |
214 | * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around | |
215 | * this, simply disable LP2 if the PCI driver and DT node are both enabled. | |
216 | */ | |
217 | void tegra20_cpuidle_pcie_irqs_in_use(void) | |
218 | { | |
219 | pr_info_once( | |
220 | "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n"); | |
221 | tegra_idle_driver.states[1].disabled = true; | |
222 | } | |
223 | ||
0b25e25b JL |
224 | int __init tegra20_cpuidle_init(void) |
225 | { | |
c5106c9d | 226 | return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); |
0b25e25b | 227 | } |