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8e267f3d GL |
1 | /* |
2 | * nVidia Tegra device tree board support | |
3 | * | |
4 | * Copyright (C) 2010 Secret Lab Technologies, Ltd. | |
5 | * Copyright (C) 2010 Google, Inc. | |
6 | * | |
7 | * This software is licensed under the terms of the GNU General Public | |
8 | * License version 2, as published by the Free Software Foundation, and | |
9 | * may be copied, distributed, and modified under those terms. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/serial_8250.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/irqdomain.h> | |
25 | #include <linux/of.h> | |
26 | #include <linux/of_address.h> | |
27 | #include <linux/of_fdt.h> | |
28 | #include <linux/of_irq.h> | |
29 | #include <linux/of_platform.h> | |
30 | #include <linux/pda_power.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/i2c.h> | |
33 | #include <linux/i2c-tegra.h> | |
34 | ||
35 | #include <asm/mach-types.h> | |
36 | #include <asm/mach/arch.h> | |
37 | #include <asm/mach/time.h> | |
38 | #include <asm/setup.h> | |
39 | ||
40 | #include <mach/iomap.h> | |
41 | #include <mach/irqs.h> | |
42 | ||
43 | #include "board.h" | |
44 | #include "board-harmony.h" | |
45 | #include "clock.h" | |
46 | #include "devices.h" | |
47 | ||
48 | void harmony_pinmux_init(void); | |
49 | void seaboard_pinmux_init(void); | |
add29e61 | 50 | void ventana_pinmux_init(void); |
8e267f3d GL |
51 | |
52 | struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { | |
1a4a30c8 SW |
53 | OF_DEV_AUXDATA("nvidia,tegra20-pinmux", TEGRA_APB_MISC_BASE + 0x14, "tegra-pinmux", NULL), |
54 | OF_DEV_AUXDATA("nvidia,tegra20-gpio", TEGRA_GPIO_BASE, "tegra-gpio", NULL), | |
8e267f3d GL |
55 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), |
56 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), | |
57 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), | |
58 | OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL), | |
59 | OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL), | |
60 | OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL), | |
61 | OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL), | |
62 | OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_DVC_BASE, "tegra-i2c.3", NULL), | |
63 | OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.0", NULL), | |
64 | OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra-i2s.1", NULL), | |
65 | OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra-das", NULL), | |
66 | {} | |
67 | }; | |
68 | ||
69 | static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { | |
70 | /* name parent rate enabled */ | |
71 | { "uartd", "pll_p", 216000000, true }, | |
72 | { NULL, NULL, 0, 0}, | |
73 | }; | |
74 | ||
75 | static struct of_device_id tegra_dt_match_table[] __initdata = { | |
76 | { .compatible = "simple-bus", }, | |
77 | {} | |
78 | }; | |
79 | ||
80 | static struct of_device_id tegra_dt_gic_match[] __initdata = { | |
81 | { .compatible = "nvidia,tegra20-gic", }, | |
82 | {} | |
83 | }; | |
84 | ||
add29e61 PDS |
85 | static struct { |
86 | char *machine; | |
87 | void (*init)(void); | |
88 | } pinmux_configs[] = { | |
89 | { "nvidia,harmony", harmony_pinmux_init }, | |
90 | { "nvidia,seaboard", seaboard_pinmux_init }, | |
91 | { "nvidia,ventana", ventana_pinmux_init }, | |
92 | }; | |
93 | ||
8e267f3d GL |
94 | static void __init tegra_dt_init(void) |
95 | { | |
96 | struct device_node *node; | |
add29e61 | 97 | int i; |
8e267f3d GL |
98 | |
99 | node = of_find_matching_node_by_address(NULL, tegra_dt_gic_match, | |
100 | TEGRA_ARM_INT_DIST_BASE); | |
101 | if (node) | |
102 | irq_domain_add_simple(node, INT_GIC_BASE); | |
103 | ||
104 | tegra_clk_init_from_table(tegra_dt_clk_init_table); | |
105 | ||
4b91b6fb SW |
106 | /* |
107 | * Finished with the static registrations now; fill in the missing | |
108 | * devices | |
109 | */ | |
110 | of_platform_populate(NULL, tegra_dt_match_table, | |
111 | tegra20_auxdata_lookup, NULL); | |
112 | ||
add29e61 PDS |
113 | for (i = 0; i < ARRAY_SIZE(pinmux_configs); i++) { |
114 | if (of_machine_is_compatible(pinmux_configs[i].machine)) { | |
115 | pinmux_configs[i].init(); | |
116 | break; | |
117 | } | |
118 | } | |
119 | ||
120 | WARN(i == ARRAY_SIZE(pinmux_configs), | |
121 | "Unknown platform! Pinmuxing not initialized\n"); | |
8e267f3d GL |
122 | } |
123 | ||
124 | static const char * tegra_dt_board_compat[] = { | |
125 | "nvidia,harmony", | |
126 | "nvidia,seaboard", | |
add29e61 | 127 | "nvidia,ventana", |
8e267f3d GL |
128 | NULL |
129 | }; | |
130 | ||
131 | DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)") | |
132 | .map_io = tegra_map_common_io, | |
133 | .init_early = tegra_init_early, | |
134 | .init_irq = tegra_init_irq, | |
135 | .timer = &tegra_timer, | |
136 | .init_machine = tegra_dt_init, | |
137 | .dt_compat = tegra_dt_board_compat, | |
138 | MACHINE_END |