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clocksource: tegra: cosmetic: Fix error message
[linux-2.6-block.git] / arch / arm / mach-tegra / board-dt-tegra20.c
CommitLineData
8e267f3d
GL		 1/*
2 * nVidia Tegra device tree board support
3 *
4 * Copyright (C) 2010 Secret Lab Technologies, Ltd.
5 * Copyright (C) 2010 Google, Inc.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
1711b1e1 18#include <linux/clocksource.h>
8e267f3d
GL		 19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/serial_8250.h>
23#include <linux/clk.h>
24#include <linux/dma-mapping.h>
25#include <linux/irqdomain.h>
26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/of_fdt.h>
29#include <linux/of_irq.h>
30#include <linux/of_platform.h>
31#include <linux/pda_power.h>
bab53ce3 32#include <linux/platform_data/tegra_usb.h>
8e267f3d
GL		 33#include <linux/io.h>
34#include <linux/i2c.h>
35#include <linux/i2c-tegra.h>
bab53ce3 36#include <linux/usb/tegra_usb_phy.h>
8e267f3d 37
afed2a26 38#include <asm/hardware/gic.h>
8e267f3d
GL		 39#include <asm/mach-types.h>
40#include <asm/mach/arch.h>
41#include <asm/mach/time.h>
42#include <asm/setup.h>
43
8e267f3d 44#include "board.h"
8e267f3d 45#include "clock.h"
a1725732 46#include "common.h"
2be39c07 47#include "iomap.h"
bab53ce3
SW		 48
49struct tegra_ehci_platform_data tegra_ehci1_pdata = {
50 .operating_mode = TEGRA_USB_OTG,
51 .power_down_on_bus_suspend = 1,
52 .vbus_gpio = -1,
53};
54
55struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
56 .reset_gpio = -1,
57 .clk = "cdev2",
58};
59
60struct tegra_ehci_platform_data tegra_ehci2_pdata = {
61 .phy_config = &tegra_ehci2_ulpi_phy_config,
62 .operating_mode = TEGRA_USB_HOST,
63 .power_down_on_bus_suspend = 1,
64 .vbus_gpio = -1,
65};
66
67struct tegra_ehci_platform_data tegra_ehci3_pdata = {
68 .operating_mode = TEGRA_USB_HOST,
69 .power_down_on_bus_suspend = 1,
70 .vbus_gpio = -1,
71};
8e267f3d 72
8e267f3d
GL		 73struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
74 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL),
75 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL),
76 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL),
77 OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL),
78 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL),
79 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL),
80 OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL),
0bc2ecb6 81 OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL),
896637ac
SW		 82 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", NULL),
83 OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", NULL),
84 OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra20-das", NULL),
4a53f4e6 85 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0",
8c3ec841 86 &tegra_ehci1_pdata),
4a53f4e6 87 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1",
8c3ec841 88 &tegra_ehci2_pdata),
4a53f4e6 89 OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
8c3ec841 90 &tegra_ehci3_pdata),
9ec97169 91 OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
140fd977 92 OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
e245f54a 93 OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL),
ffa05e45
LD		 94 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),
95 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
96 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
97 OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
35de7bfe
TR		 98 OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL),
99 OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL),
100 OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL),
101 OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL),
102 OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL),
103 OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL),
8e267f3d
GL		 104 {}
105};
106
107static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
108 /* name parent rate enabled */
37c241ed 109 { "uarta", "pll_p", 216000000, true },
8e267f3d 110 { "uartd", "pll_p", 216000000, true },
4a53f4e6
OJ		 111 { "usbd", "clk_m", 12000000, false },
112 { "usb2", "clk_m", 12000000, false },
113 { "usb3", "clk_m", 12000000, false },
586187e2
SW		 114 { "pll_a", "pll_p_out1", 56448000, true },
115 { "pll_a_out0", "pll_a", 11289600, true },
116 { "cdev1", NULL, 0, true },
25804d81 117 { "blink", "clk_32k", 32768, true },
586187e2
SW		 118 { "i2s1", "pll_a_out0", 11289600, false},
119 { "i2s2", "pll_a_out0", 11289600, false},
25804d81
WN		 120 { "sdmmc1", "pll_p", 48000000, false},
121 { "sdmmc3", "pll_p", 48000000, false},
122 { "sdmmc4", "pll_p", 48000000, false},
e245f54a 123 { "spi", "pll_p", 20000000, false },
ffa05e45
LD		 124 { "sbc1", "pll_p", 100000000, false },
125 { "sbc2", "pll_p", 100000000, false },
126 { "sbc3", "pll_p", 100000000, false },
127 { "sbc4", "pll_p", 100000000, false },
35de7bfe
TR		 128 { "host1x", "pll_c", 150000000, false },
129 { "disp1", "pll_p", 600000000, false },
130 { "disp2", "pll_p", 600000000, false },
8e267f3d
GL		 131 { NULL, NULL, 0, 0},
132};
133
8e267f3d
GL		 134static void __init tegra_dt_init(void)
135{
8e267f3d
GL		 136 tegra_clk_init_from_table(tegra_dt_clk_init_table);
137
a58116f3
SW		 138 /*
139 * Finished with the static registrations now; fill in the missing
140 * devices
141 */
2553dcc6 142 of_platform_populate(NULL, of_default_bus_match_table,
a58116f3 143 tegra20_auxdata_lookup, NULL);
8e267f3d
GL		 144}
145
c554dee3
SW		 146static void __init trimslice_init(void)
147{
be6a9194 148#ifdef CONFIG_TEGRA_PCI
c554dee3
SW		 149 int ret;
150
151 ret = tegra_pcie_init(true, true);
152 if (ret)
153 pr_err("tegra_pci_init() failed: %d\n", ret);
c554dee3 154#endif
be6a9194 155}
c554dee3 156
a12c0efc
SW		 157static void __init harmony_init(void)
158{
3cc404de 159#ifdef CONFIG_TEGRA_PCI
a12c0efc
SW		 160 int ret;
161
a12c0efc
SW		 162 ret = harmony_pcie_init();
163 if (ret)
164 pr_err("harmony_pcie_init() failed: %d\n", ret);
a12c0efc 165#endif
bb25af81 166}
a12c0efc 167
b64a02c6
SW		 168static void __init paz00_init(void)
169{
170 tegra_paz00_wifikill_init();
171}
b64a02c6 172
c554dee3
SW		 173static struct {
174 char *machine;
175 void (*init)(void);
176} board_init_funcs[] = {
c554dee3 177 { "compulab,trimslice", trimslice_init },
a12c0efc 178 { "nvidia,harmony", harmony_init },
b64a02c6 179 { "compal,paz00", paz00_init },
c554dee3
SW		 180};
181
182static void __init tegra_dt_init_late(void)
183{
184 int i;
185
186 tegra_init_late();
187
188 for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
189 if (of_machine_is_compatible(board_init_funcs[i].machine)) {
190 board_init_funcs[i].init();
191 break;
192 }
193 }
194}
195
c37c07dd 196static const char *tegra20_dt_board_compat[] = {
c5444f39 197 "nvidia,tegra20",
8e267f3d
GL		 198 NULL
199};
200
c37c07dd 201DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
8e267f3d 202 .map_io = tegra_map_common_io,
a1725732 203 .smp = smp_ops(tegra_smp_ops),
c37c07dd 204 .init_early = tegra20_init_early,
0d4f7479 205 .init_irq = tegra_dt_init_irq,
afed2a26 206 .handle_irq = gic_handle_irq,
1711b1e1 207 .init_time = clocksource_of_init,
8e267f3d 208 .init_machine = tegra_dt_init,
c554dee3 209 .init_late = tegra_dt_init_late,
abea3f2c 210 .restart = tegra_assert_system_reset,
c37c07dd 211 .dt_compat = tegra20_dt_board_compat,
8e267f3d 212MACHINE_END
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