Commit | Line | Data |
---|---|---|
9952f691 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
9c4566a1 DN |
2 | /* |
3 | * Copyright 2010-2011 Calxeda, Inc. | |
4 | * Copyright 2012 Pavel Machek <pavel@denx.de> | |
5 | * Based on platsmp.c, Copyright (C) 2002 ARM Ltd. | |
6 | * Copyright (C) 2012 Altera Corporation | |
9c4566a1 DN |
7 | */ |
8 | #include <linux/delay.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/smp.h> | |
11 | #include <linux/io.h> | |
12 | #include <linux/of.h> | |
13 | #include <linux/of_address.h> | |
14 | ||
15 | #include <asm/cacheflush.h> | |
9c4566a1 DN |
16 | #include <asm/smp_scu.h> |
17 | #include <asm/smp_plat.h> | |
18 | ||
19 | #include "core.h" | |
20 | ||
8bd26e3a | 21 | static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) |
9c4566a1 | 22 | { |
187bea47 | 23 | int trampoline_size = secondary_trampoline_end - secondary_trampoline; |
9c4566a1 | 24 | |
3a4356c0 | 25 | if (socfpga_cpu1start_addr) { |
d686ce42 AT |
26 | /* This will put CPU #1 into reset. */ |
27 | writel(RSTMGR_MPUMODRST_CPU1, | |
28 | rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST); | |
29 | ||
187bea47 | 30 | memcpy(phys_to_virt(0), secondary_trampoline, trampoline_size); |
9c4566a1 | 31 | |
64fc2a94 | 32 | writel(__pa_symbol(secondary_startup), |
d686ce42 | 33 | sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)); |
9c4566a1 | 34 | |
d6dd735f DN |
35 | flush_cache_all(); |
36 | smp_wmb(); | |
37 | outer_clean_range(0, trampoline_size); | |
9c4566a1 | 38 | |
d686ce42 AT |
39 | /* This will release CPU #1 out of reset. */ |
40 | writel(0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST); | |
d6dd735f | 41 | } |
9c4566a1 DN |
42 | |
43 | return 0; | |
44 | } | |
45 | ||
45be0cdb | 46 | static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle) |
9c4566a1 | 47 | { |
187bea47 | 48 | int trampoline_size = secondary_trampoline_end - secondary_trampoline; |
9c4566a1 | 49 | |
45be0cdb DN |
50 | if (socfpga_cpu1start_addr) { |
51 | writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr + | |
52 | SOCFPGA_A10_RSTMGR_MODMPURST); | |
187bea47 | 53 | memcpy(phys_to_virt(0), secondary_trampoline, trampoline_size); |
9c4566a1 | 54 | |
64fc2a94 | 55 | writel(__pa_symbol(secondary_startup), |
45be0cdb | 56 | sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff)); |
9c4566a1 | 57 | |
45be0cdb DN |
58 | flush_cache_all(); |
59 | smp_wmb(); | |
60 | outer_clean_range(0, trampoline_size); | |
61 | ||
62 | /* This will release CPU #1 out of reset. */ | |
63 | writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST); | |
9c4566a1 DN |
64 | } |
65 | ||
45be0cdb | 66 | return 0; |
9c4566a1 DN |
67 | } |
68 | ||
69 | static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus) | |
70 | { | |
122694a0 DN |
71 | struct device_node *np; |
72 | void __iomem *socfpga_scu_base_addr; | |
9c4566a1 | 73 | |
122694a0 DN |
74 | np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); |
75 | if (!np) { | |
76 | pr_err("%s: missing scu\n", __func__); | |
77 | return; | |
9c4566a1 DN |
78 | } |
79 | ||
122694a0 DN |
80 | socfpga_scu_base_addr = of_iomap(np, 0); |
81 | if (!socfpga_scu_base_addr) | |
82 | return; | |
9c4566a1 DN |
83 | scu_enable(socfpga_scu_base_addr); |
84 | } | |
85 | ||
5d37e80b | 86 | #ifdef CONFIG_HOTPLUG_CPU |
9c4566a1 DN |
87 | /* |
88 | * platform-specific code to shutdown a CPU | |
89 | * | |
90 | * Called with IRQs disabled | |
91 | */ | |
92 | static void socfpga_cpu_die(unsigned int cpu) | |
93 | { | |
d686ce42 AT |
94 | /* Do WFI. If we wake up early, go back into WFI */ |
95 | while (1) | |
96 | cpu_do_idle(); | |
9c4566a1 DN |
97 | } |
98 | ||
b33612e1 HT |
99 | /* |
100 | * We need a dummy function so that platform_can_cpu_hotplug() knows | |
101 | * we support CPU hotplug. However, the function does not need to do | |
102 | * anything, because CPUs going offline just do WFI. We could reset | |
103 | * the CPUs but it would increase power consumption. | |
104 | */ | |
105 | static int socfpga_cpu_kill(unsigned int cpu) | |
106 | { | |
107 | return 1; | |
108 | } | |
5d37e80b | 109 | #endif |
b33612e1 | 110 | |
75305275 | 111 | static const struct smp_operations socfpga_smp_ops __initconst = { |
9c4566a1 | 112 | .smp_prepare_cpus = socfpga_smp_prepare_cpus, |
9c4566a1 DN |
113 | .smp_boot_secondary = socfpga_boot_secondary, |
114 | #ifdef CONFIG_HOTPLUG_CPU | |
115 | .cpu_die = socfpga_cpu_die, | |
b33612e1 | 116 | .cpu_kill = socfpga_cpu_kill, |
9c4566a1 DN |
117 | #endif |
118 | }; | |
5f763ef8 | 119 | |
75305275 | 120 | static const struct smp_operations socfpga_a10_smp_ops __initconst = { |
45be0cdb DN |
121 | .smp_prepare_cpus = socfpga_smp_prepare_cpus, |
122 | .smp_boot_secondary = socfpga_a10_boot_secondary, | |
123 | #ifdef CONFIG_HOTPLUG_CPU | |
124 | .cpu_die = socfpga_cpu_die, | |
b33612e1 | 125 | .cpu_kill = socfpga_cpu_kill, |
45be0cdb DN |
126 | #endif |
127 | }; | |
128 | ||
5f763ef8 | 129 | CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops); |
45be0cdb | 130 | CPU_METHOD_OF_DECLARE(socfpga_a10_smp, "altr,socfpga-a10-smp", &socfpga_a10_smp_ops); |