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1a59d1b8 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
9c4566a1 DN |
2 | /* |
3 | * Copyright 2012 Pavel Machek <pavel@denx.de> | |
44fd8c7d | 4 | * Copyright (C) 2012-2015 Altera Corporation |
9c4566a1 DN |
5 | */ |
6 | ||
7 | #ifndef __MACH_CORE_H | |
8 | #define __MACH_CORE_H | |
9 | ||
5c04b57f | 10 | #define SOCFPGA_RSTMGR_CTRL 0x04 |
d686ce42 | 11 | #define SOCFPGA_RSTMGR_MODMPURST 0x10 |
5c04b57f DN |
12 | #define SOCFPGA_RSTMGR_MODPERRST 0x14 |
13 | #define SOCFPGA_RSTMGR_BRGMODRST 0x1c | |
14 | ||
cd871d51 | 15 | #define SOCFPGA_A10_RSTMGR_CTRL 0xC |
45be0cdb DN |
16 | #define SOCFPGA_A10_RSTMGR_MODMPURST 0x20 |
17 | ||
5c04b57f DN |
18 | /* System Manager bits */ |
19 | #define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */ | |
20 | #define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */ | |
21 | ||
d686ce42 AT |
22 | #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ |
23 | ||
4d113838 | 24 | void socfpga_init_l2_ecc(void); |
7cc5a5d3 | 25 | void socfpga_init_ocram_ecc(void); |
ff6fd147 | 26 | void socfpga_init_arria10_l2_ecc(void); |
c5fb04cc | 27 | void socfpga_init_arria10_ocram_ecc(void); |
9c4566a1 | 28 | |
5c04b57f DN |
29 | extern void __iomem *sys_manager_base_addr; |
30 | extern void __iomem *rst_manager_base_addr; | |
44fd8c7d AT |
31 | extern void __iomem *sdr_ctl_base_addr; |
32 | ||
33 | u32 socfpga_sdram_self_refresh(u32 sdr_base); | |
34 | extern unsigned int socfpga_sdram_self_refresh_sz; | |
5c04b57f | 35 | |
9c4566a1 DN |
36 | extern char secondary_trampoline, secondary_trampoline_end; |
37 | ||
3a4356c0 | 38 | extern unsigned long socfpga_cpu1start_addr; |
d6dd735f | 39 | |
de04261d | 40 | #define SOCFPGA_SCU_VIRT_BASE 0xfee00000 |
9c4566a1 DN |
41 | |
42 | #endif |