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6d9598e2 MD |
1 | /* |
2 | * sh73a0 processor support | |
3 | * | |
4 | * Copyright (C) 2010 Takashi Yoshii | |
5 | * Copyright (C) 2010 Magnus Damm | |
6 | * Copyright (C) 2008 Yoshihiro Shimoda | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; version 2 of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | */ | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/platform_device.h> | |
48609533 | 26 | #include <linux/of_platform.h> |
6d9598e2 MD |
27 | #include <linux/delay.h> |
28 | #include <linux/input.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/serial_sci.h> | |
681e1b3e | 31 | #include <linux/sh_dma.h> |
6d9598e2 | 32 | #include <linux/sh_timer.h> |
9a27dee7 | 33 | #include <linux/platform_data/sh_ipmmu.h> |
341eb546 | 34 | #include <linux/platform_data/irq-renesas-intc-irqpin.h> |
ded59d6d | 35 | |
6d9598e2 | 36 | #include <asm/mach-types.h> |
50e15c34 | 37 | #include <asm/mach/map.h> |
6d9598e2 | 38 | #include <asm/mach/arch.h> |
3be26fdb | 39 | #include <asm/mach/time.h> |
ded59d6d | 40 | |
fd44aa5e | 41 | #include "common.h" |
74ac0de8 | 42 | #include "dma-register.h" |
86155b35 | 43 | #include "intc.h" |
b6bab126 | 44 | #include "irqs.h" |
ded59d6d | 45 | #include "sh73a0.h" |
6d9598e2 | 46 | |
50e15c34 MD |
47 | static struct map_desc sh73a0_io_desc[] __initdata = { |
48 | /* create a 1:1 entity map for 0xe6xxxxxx | |
49 | * used by CPGA, INTC and PFC. | |
50 | */ | |
51 | { | |
52 | .virtual = 0xe6000000, | |
53 | .pfn = __phys_to_pfn(0xe6000000), | |
54 | .length = 256 << 20, | |
55 | .type = MT_DEVICE_NONSHARED | |
56 | }, | |
57 | }; | |
58 | ||
59 | void __init sh73a0_map_io(void) | |
60 | { | |
61 | iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); | |
62 | } | |
63 | ||
474f6758 MD |
64 | /* PFC */ |
65 | static struct resource pfc_resources[] __initdata = { | |
66 | DEFINE_RES_MEM(0xe6050000, 0x8000), | |
67 | DEFINE_RES_MEM(0xe605801c, 0x000c), | |
994d66a4 LP |
68 | }; |
69 | ||
70 | void __init sh73a0_pinmux_init(void) | |
71 | { | |
474f6758 MD |
72 | platform_device_register_simple("pfc-sh73a0", -1, pfc_resources, |
73 | ARRAY_SIZE(pfc_resources)); | |
994d66a4 LP |
74 | } |
75 | ||
d000fff9 LP |
76 | /* SCIF */ |
77 | #define SH73A0_SCIF(scif_type, index, baseaddr, irq) \ | |
78 | static struct plat_sci_port scif##index##_platform_data = { \ | |
79 | .type = scif_type, \ | |
d000fff9 | 80 | .flags = UPF_BOOT_AUTOCONF, \ |
d000fff9 LP |
81 | .scscr = SCSCR_RE | SCSCR_TE, \ |
82 | }; \ | |
83 | \ | |
31e1ee86 LP |
84 | static struct resource scif##index##_resources[] = { \ |
85 | DEFINE_RES_MEM(baseaddr, 0x100), \ | |
86 | DEFINE_RES_IRQ(irq), \ | |
87 | }; \ | |
88 | \ | |
d000fff9 LP |
89 | static struct platform_device scif##index##_device = { \ |
90 | .name = "sh-sci", \ | |
91 | .id = index, \ | |
31e1ee86 LP |
92 | .resource = scif##index##_resources, \ |
93 | .num_resources = ARRAY_SIZE(scif##index##_resources), \ | |
d000fff9 LP |
94 | .dev = { \ |
95 | .platform_data = &scif##index##_platform_data, \ | |
96 | }, \ | |
97 | } | |
6d9598e2 | 98 | |
d000fff9 LP |
99 | SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72)); |
100 | SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73)); | |
101 | SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74)); | |
102 | SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75)); | |
103 | SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78)); | |
104 | SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79)); | |
105 | SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156)); | |
106 | SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143)); | |
107 | SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80)); | |
6d9598e2 | 108 | |
652256fd LP |
109 | static struct sh_timer_config cmt1_platform_data = { |
110 | .channels_mask = 0x3f, | |
6d9598e2 MD |
111 | }; |
112 | ||
652256fd LP |
113 | static struct resource cmt1_resources[] = { |
114 | DEFINE_RES_MEM(0xe6138000, 0x200), | |
115 | DEFINE_RES_IRQ(gic_spi(65)), | |
6d9598e2 MD |
116 | }; |
117 | ||
652256fd LP |
118 | static struct platform_device cmt1_device = { |
119 | .name = "sh-cmt-48", | |
120 | .id = 1, | |
6d9598e2 | 121 | .dev = { |
652256fd | 122 | .platform_data = &cmt1_platform_data, |
6d9598e2 | 123 | }, |
652256fd LP |
124 | .resource = cmt1_resources, |
125 | .num_resources = ARRAY_SIZE(cmt1_resources), | |
6d9598e2 MD |
126 | }; |
127 | ||
5010f3db | 128 | /* TMU */ |
3df592bc LP |
129 | static struct sh_timer_config tmu0_platform_data = { |
130 | .channels_mask = 7, | |
5010f3db MD |
131 | }; |
132 | ||
3df592bc LP |
133 | static struct resource tmu0_resources[] = { |
134 | DEFINE_RES_MEM(0xfff60000, 0x2c), | |
135 | DEFINE_RES_IRQ(intcs_evt2irq(0xe80)), | |
136 | DEFINE_RES_IRQ(intcs_evt2irq(0xea0)), | |
137 | DEFINE_RES_IRQ(intcs_evt2irq(0xec0)), | |
5010f3db MD |
138 | }; |
139 | ||
3df592bc LP |
140 | static struct platform_device tmu0_device = { |
141 | .name = "sh-tmu", | |
5010f3db MD |
142 | .id = 0, |
143 | .dev = { | |
3df592bc | 144 | .platform_data = &tmu0_platform_data, |
5010f3db | 145 | }, |
3df592bc LP |
146 | .resource = tmu0_resources, |
147 | .num_resources = ARRAY_SIZE(tmu0_resources), | |
5010f3db MD |
148 | }; |
149 | ||
b028f94b | 150 | static struct resource i2c0_resources[] = { |
8e85524b | 151 | [0] = DEFINE_RES_MEM(0xe6820000, 0x426), |
b028f94b YT |
152 | [1] = { |
153 | .start = gic_spi(167), | |
154 | .end = gic_spi(170), | |
155 | .flags = IORESOURCE_IRQ, | |
156 | }, | |
157 | }; | |
158 | ||
159 | static struct resource i2c1_resources[] = { | |
8e85524b | 160 | [0] = DEFINE_RES_MEM(0xe6822000, 0x426), |
b028f94b YT |
161 | [1] = { |
162 | .start = gic_spi(51), | |
163 | .end = gic_spi(54), | |
164 | .flags = IORESOURCE_IRQ, | |
165 | }, | |
166 | }; | |
167 | ||
168 | static struct resource i2c2_resources[] = { | |
8e85524b | 169 | [0] = DEFINE_RES_MEM(0xe6824000, 0x426), |
b028f94b YT |
170 | [1] = { |
171 | .start = gic_spi(171), | |
172 | .end = gic_spi(174), | |
173 | .flags = IORESOURCE_IRQ, | |
174 | }, | |
175 | }; | |
176 | ||
177 | static struct resource i2c3_resources[] = { | |
8e85524b | 178 | [0] = DEFINE_RES_MEM(0xe6826000, 0x426), |
b028f94b YT |
179 | [1] = { |
180 | .start = gic_spi(183), | |
181 | .end = gic_spi(186), | |
182 | .flags = IORESOURCE_IRQ, | |
183 | }, | |
184 | }; | |
185 | ||
186 | static struct resource i2c4_resources[] = { | |
8e85524b | 187 | [0] = DEFINE_RES_MEM(0xe6828000, 0x426), |
b028f94b YT |
188 | [1] = { |
189 | .start = gic_spi(187), | |
190 | .end = gic_spi(190), | |
191 | .flags = IORESOURCE_IRQ, | |
192 | }, | |
193 | }; | |
194 | ||
195 | static struct platform_device i2c0_device = { | |
196 | .name = "i2c-sh_mobile", | |
197 | .id = 0, | |
198 | .resource = i2c0_resources, | |
199 | .num_resources = ARRAY_SIZE(i2c0_resources), | |
200 | }; | |
201 | ||
202 | static struct platform_device i2c1_device = { | |
203 | .name = "i2c-sh_mobile", | |
204 | .id = 1, | |
205 | .resource = i2c1_resources, | |
206 | .num_resources = ARRAY_SIZE(i2c1_resources), | |
207 | }; | |
208 | ||
209 | static struct platform_device i2c2_device = { | |
210 | .name = "i2c-sh_mobile", | |
211 | .id = 2, | |
212 | .resource = i2c2_resources, | |
213 | .num_resources = ARRAY_SIZE(i2c2_resources), | |
214 | }; | |
215 | ||
216 | static struct platform_device i2c3_device = { | |
217 | .name = "i2c-sh_mobile", | |
218 | .id = 3, | |
219 | .resource = i2c3_resources, | |
220 | .num_resources = ARRAY_SIZE(i2c3_resources), | |
221 | }; | |
222 | ||
223 | static struct platform_device i2c4_device = { | |
224 | .name = "i2c-sh_mobile", | |
225 | .id = 4, | |
226 | .resource = i2c4_resources, | |
227 | .num_resources = ARRAY_SIZE(i2c4_resources), | |
228 | }; | |
229 | ||
681e1b3e MD |
230 | static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = { |
231 | { | |
232 | .slave_id = SHDMA_SLAVE_SCIF0_TX, | |
233 | .addr = 0xe6c40020, | |
234 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
235 | .mid_rid = 0x21, | |
236 | }, { | |
237 | .slave_id = SHDMA_SLAVE_SCIF0_RX, | |
238 | .addr = 0xe6c40024, | |
239 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
240 | .mid_rid = 0x22, | |
241 | }, { | |
242 | .slave_id = SHDMA_SLAVE_SCIF1_TX, | |
243 | .addr = 0xe6c50020, | |
244 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
245 | .mid_rid = 0x25, | |
246 | }, { | |
247 | .slave_id = SHDMA_SLAVE_SCIF1_RX, | |
248 | .addr = 0xe6c50024, | |
249 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
250 | .mid_rid = 0x26, | |
251 | }, { | |
252 | .slave_id = SHDMA_SLAVE_SCIF2_TX, | |
253 | .addr = 0xe6c60020, | |
254 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
255 | .mid_rid = 0x29, | |
256 | }, { | |
257 | .slave_id = SHDMA_SLAVE_SCIF2_RX, | |
258 | .addr = 0xe6c60024, | |
259 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
260 | .mid_rid = 0x2a, | |
261 | }, { | |
262 | .slave_id = SHDMA_SLAVE_SCIF3_TX, | |
263 | .addr = 0xe6c70020, | |
264 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
265 | .mid_rid = 0x2d, | |
266 | }, { | |
267 | .slave_id = SHDMA_SLAVE_SCIF3_RX, | |
268 | .addr = 0xe6c70024, | |
269 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
270 | .mid_rid = 0x2e, | |
271 | }, { | |
272 | .slave_id = SHDMA_SLAVE_SCIF4_TX, | |
273 | .addr = 0xe6c80020, | |
274 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
275 | .mid_rid = 0x39, | |
276 | }, { | |
277 | .slave_id = SHDMA_SLAVE_SCIF4_RX, | |
278 | .addr = 0xe6c80024, | |
279 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
280 | .mid_rid = 0x3a, | |
281 | }, { | |
282 | .slave_id = SHDMA_SLAVE_SCIF5_TX, | |
283 | .addr = 0xe6cb0020, | |
284 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
285 | .mid_rid = 0x35, | |
286 | }, { | |
287 | .slave_id = SHDMA_SLAVE_SCIF5_RX, | |
288 | .addr = 0xe6cb0024, | |
289 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
290 | .mid_rid = 0x36, | |
291 | }, { | |
292 | .slave_id = SHDMA_SLAVE_SCIF6_TX, | |
293 | .addr = 0xe6cc0020, | |
294 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
295 | .mid_rid = 0x1d, | |
296 | }, { | |
297 | .slave_id = SHDMA_SLAVE_SCIF6_RX, | |
298 | .addr = 0xe6cc0024, | |
299 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
300 | .mid_rid = 0x1e, | |
301 | }, { | |
302 | .slave_id = SHDMA_SLAVE_SCIF7_TX, | |
303 | .addr = 0xe6cd0020, | |
304 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
305 | .mid_rid = 0x19, | |
306 | }, { | |
307 | .slave_id = SHDMA_SLAVE_SCIF7_RX, | |
308 | .addr = 0xe6cd0024, | |
309 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
310 | .mid_rid = 0x1a, | |
311 | }, { | |
312 | .slave_id = SHDMA_SLAVE_SCIF8_TX, | |
313 | .addr = 0xe6c30040, | |
314 | .chcr = CHCR_TX(XMIT_SZ_8BIT), | |
315 | .mid_rid = 0x3d, | |
316 | }, { | |
317 | .slave_id = SHDMA_SLAVE_SCIF8_RX, | |
318 | .addr = 0xe6c30060, | |
319 | .chcr = CHCR_RX(XMIT_SZ_8BIT), | |
320 | .mid_rid = 0x3e, | |
321 | }, { | |
322 | .slave_id = SHDMA_SLAVE_SDHI0_TX, | |
323 | .addr = 0xee100030, | |
324 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
325 | .mid_rid = 0xc1, | |
326 | }, { | |
327 | .slave_id = SHDMA_SLAVE_SDHI0_RX, | |
328 | .addr = 0xee100030, | |
329 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
330 | .mid_rid = 0xc2, | |
331 | }, { | |
332 | .slave_id = SHDMA_SLAVE_SDHI1_TX, | |
333 | .addr = 0xee120030, | |
334 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
335 | .mid_rid = 0xc9, | |
336 | }, { | |
337 | .slave_id = SHDMA_SLAVE_SDHI1_RX, | |
338 | .addr = 0xee120030, | |
339 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
340 | .mid_rid = 0xca, | |
341 | }, { | |
342 | .slave_id = SHDMA_SLAVE_SDHI2_TX, | |
343 | .addr = 0xee140030, | |
344 | .chcr = CHCR_TX(XMIT_SZ_16BIT), | |
345 | .mid_rid = 0xcd, | |
346 | }, { | |
347 | .slave_id = SHDMA_SLAVE_SDHI2_RX, | |
348 | .addr = 0xee140030, | |
349 | .chcr = CHCR_RX(XMIT_SZ_16BIT), | |
350 | .mid_rid = 0xce, | |
351 | }, { | |
352 | .slave_id = SHDMA_SLAVE_MMCIF_TX, | |
353 | .addr = 0xe6bd0034, | |
354 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | |
355 | .mid_rid = 0xd1, | |
356 | }, { | |
357 | .slave_id = SHDMA_SLAVE_MMCIF_RX, | |
358 | .addr = 0xe6bd0034, | |
359 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
360 | .mid_rid = 0xd2, | |
361 | }, | |
362 | }; | |
363 | ||
364 | #define DMAE_CHANNEL(_offset) \ | |
365 | { \ | |
366 | .offset = _offset - 0x20, \ | |
367 | .dmars = _offset - 0x20 + 0x40, \ | |
368 | } | |
369 | ||
370 | static const struct sh_dmae_channel sh73a0_dmae_channels[] = { | |
371 | DMAE_CHANNEL(0x8000), | |
372 | DMAE_CHANNEL(0x8080), | |
373 | DMAE_CHANNEL(0x8100), | |
374 | DMAE_CHANNEL(0x8180), | |
375 | DMAE_CHANNEL(0x8200), | |
376 | DMAE_CHANNEL(0x8280), | |
377 | DMAE_CHANNEL(0x8300), | |
378 | DMAE_CHANNEL(0x8380), | |
379 | DMAE_CHANNEL(0x8400), | |
380 | DMAE_CHANNEL(0x8480), | |
381 | DMAE_CHANNEL(0x8500), | |
382 | DMAE_CHANNEL(0x8580), | |
383 | DMAE_CHANNEL(0x8600), | |
384 | DMAE_CHANNEL(0x8680), | |
385 | DMAE_CHANNEL(0x8700), | |
386 | DMAE_CHANNEL(0x8780), | |
387 | DMAE_CHANNEL(0x8800), | |
388 | DMAE_CHANNEL(0x8880), | |
389 | DMAE_CHANNEL(0x8900), | |
390 | DMAE_CHANNEL(0x8980), | |
391 | }; | |
392 | ||
681e1b3e MD |
393 | static struct sh_dmae_pdata sh73a0_dmae_platform_data = { |
394 | .slave = sh73a0_dmae_slaves, | |
395 | .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves), | |
396 | .channel = sh73a0_dmae_channels, | |
397 | .channel_num = ARRAY_SIZE(sh73a0_dmae_channels), | |
6088b422 KM |
398 | .ts_low_shift = TS_LOW_SHIFT, |
399 | .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, | |
400 | .ts_high_shift = TS_HI_SHIFT, | |
401 | .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, | |
402 | .ts_shift = dma_ts_shift, | |
403 | .ts_shift_num = ARRAY_SIZE(dma_ts_shift), | |
681e1b3e MD |
404 | .dmaor_init = DMAOR_DME, |
405 | }; | |
406 | ||
407 | static struct resource sh73a0_dmae_resources[] = { | |
abbec5f4 | 408 | DEFINE_RES_MEM(0xfe000020, 0x89e0), |
681e1b3e | 409 | { |
20052462 | 410 | .name = "error_irq", |
681e1b3e MD |
411 | .start = gic_spi(129), |
412 | .end = gic_spi(129), | |
413 | .flags = IORESOURCE_IRQ, | |
414 | }, | |
415 | { | |
416 | /* IRQ for channels 0-19 */ | |
417 | .start = gic_spi(109), | |
418 | .end = gic_spi(128), | |
419 | .flags = IORESOURCE_IRQ, | |
420 | }, | |
421 | }; | |
422 | ||
423 | static struct platform_device dma0_device = { | |
424 | .name = "sh-dma-engine", | |
425 | .id = 0, | |
426 | .resource = sh73a0_dmae_resources, | |
427 | .num_resources = ARRAY_SIZE(sh73a0_dmae_resources), | |
428 | .dev = { | |
429 | .platform_data = &sh73a0_dmae_platform_data, | |
430 | }, | |
431 | }; | |
432 | ||
832290b2 KM |
433 | /* MPDMAC */ |
434 | static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = { | |
435 | { | |
436 | .slave_id = SHDMA_SLAVE_FSI2A_RX, | |
437 | .addr = 0xec230020, | |
438 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
439 | .mid_rid = 0xd6, /* CHECK ME */ | |
440 | }, { | |
441 | .slave_id = SHDMA_SLAVE_FSI2A_TX, | |
442 | .addr = 0xec230024, | |
443 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | |
444 | .mid_rid = 0xd5, /* CHECK ME */ | |
445 | }, { | |
446 | .slave_id = SHDMA_SLAVE_FSI2C_RX, | |
447 | .addr = 0xec230060, | |
448 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
449 | .mid_rid = 0xda, /* CHECK ME */ | |
450 | }, { | |
451 | .slave_id = SHDMA_SLAVE_FSI2C_TX, | |
452 | .addr = 0xec230064, | |
453 | .chcr = CHCR_TX(XMIT_SZ_32BIT), | |
454 | .mid_rid = 0xd9, /* CHECK ME */ | |
455 | }, { | |
456 | .slave_id = SHDMA_SLAVE_FSI2B_RX, | |
457 | .addr = 0xec240020, | |
458 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
459 | .mid_rid = 0x8e, /* CHECK ME */ | |
460 | }, { | |
461 | .slave_id = SHDMA_SLAVE_FSI2B_TX, | |
462 | .addr = 0xec240024, | |
463 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
464 | .mid_rid = 0x8d, /* CHECK ME */ | |
465 | }, { | |
466 | .slave_id = SHDMA_SLAVE_FSI2D_RX, | |
467 | .addr = 0xec240060, | |
468 | .chcr = CHCR_RX(XMIT_SZ_32BIT), | |
469 | .mid_rid = 0x9a, /* CHECK ME */ | |
470 | }, | |
471 | }; | |
472 | ||
473 | #define MPDMA_CHANNEL(a, b, c) \ | |
474 | { \ | |
475 | .offset = a, \ | |
476 | .dmars = b, \ | |
477 | .dmars_bit = c, \ | |
478 | .chclr_offset = (0x220 - 0x20) + a \ | |
479 | } | |
480 | ||
481 | static const struct sh_dmae_channel sh73a0_mpdma_channels[] = { | |
482 | MPDMA_CHANNEL(0x00, 0, 0), | |
483 | MPDMA_CHANNEL(0x10, 0, 8), | |
484 | MPDMA_CHANNEL(0x20, 4, 0), | |
485 | MPDMA_CHANNEL(0x30, 4, 8), | |
486 | MPDMA_CHANNEL(0x50, 8, 0), | |
487 | MPDMA_CHANNEL(0x70, 8, 8), | |
488 | }; | |
489 | ||
490 | static struct sh_dmae_pdata sh73a0_mpdma_platform_data = { | |
491 | .slave = sh73a0_mpdma_slaves, | |
492 | .slave_num = ARRAY_SIZE(sh73a0_mpdma_slaves), | |
493 | .channel = sh73a0_mpdma_channels, | |
494 | .channel_num = ARRAY_SIZE(sh73a0_mpdma_channels), | |
6088b422 KM |
495 | .ts_low_shift = TS_LOW_SHIFT, |
496 | .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, | |
497 | .ts_high_shift = TS_HI_SHIFT, | |
498 | .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, | |
499 | .ts_shift = dma_ts_shift, | |
500 | .ts_shift_num = ARRAY_SIZE(dma_ts_shift), | |
832290b2 KM |
501 | .dmaor_init = DMAOR_DME, |
502 | .chclr_present = 1, | |
503 | }; | |
504 | ||
505 | /* Resource order important! */ | |
506 | static struct resource sh73a0_mpdma_resources[] = { | |
abbec5f4 SH |
507 | /* Channel registers and DMAOR */ |
508 | DEFINE_RES_MEM(0xec618020, 0x270), | |
509 | /* DMARSx */ | |
510 | DEFINE_RES_MEM(0xec619000, 0xc), | |
832290b2 KM |
511 | { |
512 | .name = "error_irq", | |
513 | .start = gic_spi(181), | |
514 | .end = gic_spi(181), | |
515 | .flags = IORESOURCE_IRQ, | |
516 | }, | |
517 | { | |
518 | /* IRQ for channels 0-5 */ | |
519 | .start = gic_spi(175), | |
520 | .end = gic_spi(180), | |
521 | .flags = IORESOURCE_IRQ, | |
522 | }, | |
523 | }; | |
524 | ||
525 | static struct platform_device mpdma0_device = { | |
526 | .name = "sh-dma-engine", | |
527 | .id = 1, | |
528 | .resource = sh73a0_mpdma_resources, | |
529 | .num_resources = ARRAY_SIZE(sh73a0_mpdma_resources), | |
530 | .dev = { | |
531 | .platform_data = &sh73a0_mpdma_platform_data, | |
532 | }, | |
533 | }; | |
534 | ||
f23f5be0 TK |
535 | static struct resource pmu_resources[] = { |
536 | [0] = { | |
537 | .start = gic_spi(55), | |
538 | .end = gic_spi(55), | |
539 | .flags = IORESOURCE_IRQ, | |
540 | }, | |
541 | [1] = { | |
542 | .start = gic_spi(56), | |
543 | .end = gic_spi(56), | |
544 | .flags = IORESOURCE_IRQ, | |
545 | }, | |
546 | }; | |
547 | ||
548 | static struct platform_device pmu_device = { | |
549 | .name = "arm-pmu", | |
550 | .id = -1, | |
551 | .num_resources = ARRAY_SIZE(pmu_resources), | |
552 | .resource = pmu_resources, | |
553 | }; | |
554 | ||
9a27dee7 HE |
555 | /* an IPMMU module for ICB */ |
556 | static struct resource ipmmu_resources[] = { | |
6244cd73 | 557 | DEFINE_RES_MEM(0xfe951000, 0x100), |
9a27dee7 HE |
558 | }; |
559 | ||
560 | static const char * const ipmmu_dev_names[] = { | |
561 | "sh_mobile_lcdc_fb.0", | |
562 | }; | |
563 | ||
564 | static struct shmobile_ipmmu_platform_data ipmmu_platform_data = { | |
565 | .dev_names = ipmmu_dev_names, | |
566 | .num_dev_names = ARRAY_SIZE(ipmmu_dev_names), | |
567 | }; | |
568 | ||
569 | static struct platform_device ipmmu_device = { | |
570 | .name = "ipmmu", | |
571 | .id = -1, | |
572 | .dev = { | |
573 | .platform_data = &ipmmu_platform_data, | |
574 | }, | |
575 | .resource = ipmmu_resources, | |
576 | .num_resources = ARRAY_SIZE(ipmmu_resources), | |
577 | }; | |
578 | ||
1461f8b6 | 579 | static struct renesas_intc_irqpin_config irqpin0_platform_data = { |
341eb546 MD |
580 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */ |
581 | }; | |
582 | ||
583 | static struct resource irqpin0_resources[] = { | |
584 | DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */ | |
585 | DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */ | |
586 | DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */ | |
587 | DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */ | |
588 | DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */ | |
589 | DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */ | |
590 | DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */ | |
591 | DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */ | |
592 | DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */ | |
593 | DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */ | |
594 | DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */ | |
595 | DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */ | |
596 | DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */ | |
597 | }; | |
598 | ||
599 | static struct platform_device irqpin0_device = { | |
600 | .name = "renesas_intc_irqpin", | |
601 | .id = 0, | |
602 | .resource = irqpin0_resources, | |
603 | .num_resources = ARRAY_SIZE(irqpin0_resources), | |
604 | .dev = { | |
605 | .platform_data = &irqpin0_platform_data, | |
606 | }, | |
607 | }; | |
608 | ||
1461f8b6 | 609 | static struct renesas_intc_irqpin_config irqpin1_platform_data = { |
341eb546 MD |
610 | .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */ |
611 | .control_parent = true, /* Disable spurious IRQ10 */ | |
612 | }; | |
613 | ||
614 | static struct resource irqpin1_resources[] = { | |
615 | DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */ | |
616 | DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */ | |
617 | DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */ | |
618 | DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */ | |
619 | DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */ | |
620 | DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */ | |
621 | DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */ | |
622 | DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */ | |
623 | DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */ | |
624 | DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */ | |
625 | DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */ | |
626 | DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */ | |
627 | DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */ | |
628 | }; | |
629 | ||
630 | static struct platform_device irqpin1_device = { | |
631 | .name = "renesas_intc_irqpin", | |
632 | .id = 1, | |
633 | .resource = irqpin1_resources, | |
634 | .num_resources = ARRAY_SIZE(irqpin1_resources), | |
635 | .dev = { | |
636 | .platform_data = &irqpin1_platform_data, | |
637 | }, | |
638 | }; | |
639 | ||
1461f8b6 | 640 | static struct renesas_intc_irqpin_config irqpin2_platform_data = { |
341eb546 MD |
641 | .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */ |
642 | }; | |
643 | ||
644 | static struct resource irqpin2_resources[] = { | |
645 | DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */ | |
646 | DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */ | |
647 | DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */ | |
648 | DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */ | |
649 | DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */ | |
650 | DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */ | |
651 | DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */ | |
652 | DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */ | |
653 | DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */ | |
654 | DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */ | |
655 | DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */ | |
656 | DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */ | |
657 | DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */ | |
658 | }; | |
659 | ||
660 | static struct platform_device irqpin2_device = { | |
661 | .name = "renesas_intc_irqpin", | |
662 | .id = 2, | |
663 | .resource = irqpin2_resources, | |
664 | .num_resources = ARRAY_SIZE(irqpin2_resources), | |
665 | .dev = { | |
666 | .platform_data = &irqpin2_platform_data, | |
667 | }, | |
668 | }; | |
669 | ||
1461f8b6 | 670 | static struct renesas_intc_irqpin_config irqpin3_platform_data = { |
341eb546 MD |
671 | .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */ |
672 | }; | |
673 | ||
674 | static struct resource irqpin3_resources[] = { | |
675 | DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */ | |
676 | DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */ | |
677 | DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */ | |
678 | DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */ | |
679 | DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */ | |
680 | DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */ | |
681 | DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */ | |
682 | DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */ | |
683 | DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */ | |
684 | DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */ | |
685 | DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */ | |
686 | DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */ | |
687 | DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */ | |
688 | }; | |
689 | ||
690 | static struct platform_device irqpin3_device = { | |
691 | .name = "renesas_intc_irqpin", | |
692 | .id = 3, | |
693 | .resource = irqpin3_resources, | |
694 | .num_resources = ARRAY_SIZE(irqpin3_resources), | |
695 | .dev = { | |
696 | .platform_data = &irqpin3_platform_data, | |
697 | }, | |
698 | }; | |
699 | ||
700ce7c2 | 700 | static struct platform_device *sh73a0_early_devices[] __initdata = { |
6d9598e2 MD |
701 | &scif0_device, |
702 | &scif1_device, | |
703 | &scif2_device, | |
704 | &scif3_device, | |
705 | &scif4_device, | |
706 | &scif5_device, | |
707 | &scif6_device, | |
708 | &scif7_device, | |
709 | &scif8_device, | |
3df592bc | 710 | &tmu0_device, |
9a27dee7 | 711 | &ipmmu_device, |
48a0d1e0 | 712 | &cmt1_device, |
6d9598e2 MD |
713 | }; |
714 | ||
b028f94b YT |
715 | static struct platform_device *sh73a0_late_devices[] __initdata = { |
716 | &i2c0_device, | |
717 | &i2c1_device, | |
718 | &i2c2_device, | |
719 | &i2c3_device, | |
720 | &i2c4_device, | |
681e1b3e | 721 | &dma0_device, |
832290b2 | 722 | &mpdma0_device, |
f23f5be0 | 723 | &pmu_device, |
341eb546 MD |
724 | &irqpin0_device, |
725 | &irqpin1_device, | |
726 | &irqpin2_device, | |
727 | &irqpin3_device, | |
b028f94b YT |
728 | }; |
729 | ||
0a4b04dc | 730 | #define SRCR2 IOMEM(0xe61580b0) |
681e1b3e | 731 | |
6d9598e2 MD |
732 | void __init sh73a0_add_standard_devices(void) |
733 | { | |
681e1b3e MD |
734 | /* Clear software reset bit on SY-DMAC module */ |
735 | __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2); | |
736 | ||
6d9598e2 MD |
737 | platform_add_devices(sh73a0_early_devices, |
738 | ARRAY_SIZE(sh73a0_early_devices)); | |
b028f94b YT |
739 | platform_add_devices(sh73a0_late_devices, |
740 | ARRAY_SIZE(sh73a0_late_devices)); | |
6d9598e2 MD |
741 | } |
742 | ||
43cb8cb7 MD |
743 | void __init sh73a0_init_delay(void) |
744 | { | |
5df622a5 | 745 | shmobile_init_delay(); |
43cb8cb7 MD |
746 | } |
747 | ||
d6720003 KM |
748 | /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ |
749 | void __init __weak sh73a0_register_twd(void) { } | |
750 | ||
6bb27d73 | 751 | void __init sh73a0_earlytimer_init(void) |
3be26fdb | 752 | { |
43cb8cb7 | 753 | sh73a0_init_delay(); |
3be26fdb MD |
754 | sh73a0_clock_init(); |
755 | shmobile_earlytimer_init(); | |
d6720003 | 756 | sh73a0_register_twd(); |
3be26fdb MD |
757 | } |
758 | ||
6d9598e2 MD |
759 | void __init sh73a0_add_early_devices(void) |
760 | { | |
761 | early_platform_add_devices(sh73a0_early_devices, | |
762 | ARRAY_SIZE(sh73a0_early_devices)); | |
50e15c34 MD |
763 | |
764 | /* setup early console here as well */ | |
765 | shmobile_setup_console(); | |
6d9598e2 | 766 | } |
48609533 SH |
767 | |
768 | #ifdef CONFIG_USE_OF | |
769 | ||
48609533 SH |
770 | void __init sh73a0_add_standard_devices_dt(void) |
771 | { | |
772 | /* clocks are setup late during boot in the case of DT */ | |
773 | sh73a0_clock_init(); | |
774 | ||
ea31597f | 775 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
48609533 SH |
776 | } |
777 | ||
778 | static const char *sh73a0_boards_compat_dt[] __initdata = { | |
779 | "renesas,sh73a0", | |
780 | NULL, | |
781 | }; | |
782 | ||
783 | DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") | |
f9989507 | 784 | .smp = smp_ops(sh73a0_smp_ops), |
48609533 | 785 | .map_io = sh73a0_map_io, |
3b00f934 | 786 | .init_early = sh73a0_init_delay, |
48609533 | 787 | .init_machine = sh73a0_add_standard_devices_dt, |
e604d809 | 788 | .init_late = shmobile_init_late, |
48609533 SH |
789 | .dt_compat = sh73a0_boards_compat_dt, |
790 | MACHINE_END | |
791 | #endif /* CONFIG_USE_OF */ |