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ARM: shmobile: Add early debugging support using SCIF(A)
[linux-2.6-block.git] / arch / arm / mach-shmobile / setup-sh7372.c
CommitLineData
2b7eda63
MD		 1/*
2 * sh7372 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
3b7b7055 25#include <linux/of_platform.h>
6822471e 26#include <linux/uio_driver.h>
2b7eda63
MD		 27#include <linux/delay.h>
28#include <linux/input.h>
29#include <linux/io.h>
30#include <linux/serial_sci.h>
69bf6f45 31#include <linux/sh_dma.h>
2b7eda63 32#include <linux/sh_timer.h>
111058c3 33#include <linux/pm_domain.h>
426f1af9 34#include <linux/dma-mapping.h>
3cfb8439 35#include <linux/platform_data/sh_ipmmu.h>
113522ee 36
5d7220ec 37#include <asm/mach/map.h>
2b7eda63
MD		 38#include <asm/mach-types.h>
39#include <asm/mach/arch.h>
17254bff 40#include <asm/mach/time.h>
113522ee 41
fd44aa5e 42#include "common.h"
74ac0de8 43#include "dma-register.h"
86155b35 44#include "intc.h"
b6bab126 45#include "irqs.h"
6b8b0cb4 46#include "pm-rmobile.h"
113522ee 47#include "sh7372.h"
2b7eda63 48
5d7220ec
MD		 49static struct map_desc sh7372_io_desc[] __initdata = {
50 /* create a 1:1 entity map for 0xe6xxxxxx
51 * used by CPGA, INTC and PFC.
52 */
53 {
54 .virtual = 0xe6000000,
55 .pfn = __phys_to_pfn(0xe6000000),
56 .length = 256 << 20,
57 .type = MT_DEVICE_NONSHARED
58 },
59};
60
61void __init sh7372_map_io(void)
62{
7a2071c5 63 debug_ll_io_init();
5d7220ec
MD		 64 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
65}
2b7eda63 66
5967fe09
LP		 67/* PFC */
68static struct resource sh7372_pfc_resources[] = {
69 [0] = {
70 .start = 0xe6050000,
71 .end = 0xe6057fff,
72 .flags = IORESOURCE_MEM,
73 },
74 [1] = {
75 .start = 0xe605800c,
76 .end = 0xe6058027,
77 .flags = IORESOURCE_MEM,
78 }
79};
80
81static struct platform_device sh7372_pfc_device = {
82 .name = "pfc-sh7372",
83 .id = -1,
84 .resource = sh7372_pfc_resources,
85 .num_resources = ARRAY_SIZE(sh7372_pfc_resources),
86};
87
88void __init sh7372_pinmux_init(void)
89{
90 platform_device_register(&sh7372_pfc_device);
91}
92
c6a0d864
LP		 93/* SCIF */
94#define SH7372_SCIF(scif_type, index, baseaddr, irq) \
95static struct plat_sci_port scif##index##_platform_data = { \
96 .type = scif_type, \
c6a0d864 97 .flags = UPF_BOOT_AUTOCONF, \
c6a0d864
LP		 98 .scscr = SCSCR_RE | SCSCR_TE, \
99}; \
100 \
d39f98b3
LP		 101static struct resource scif##index##_resources[] = { \
102 DEFINE_RES_MEM(baseaddr, 0x100), \
103 DEFINE_RES_IRQ(irq), \
104}; \
105 \
c6a0d864
LP		 106static struct platform_device scif##index##_device = { \
107 .name = "sh-sci", \
108 .id = index, \
d39f98b3
LP		 109 .resource = scif##index##_resources, \
110 .num_resources = ARRAY_SIZE(scif##index##_resources), \
c6a0d864
LP		 111 .dev = { \
112 .platform_data = &scif##index##_platform_data, \
113 }, \
114}
2b7eda63 115
c6a0d864
LP		 116SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
117SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
118SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
119SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
120SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
121SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
122SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
2b7eda63 123
c1909cc1 124/* CMT */
0ed61fc9 125static struct sh_timer_config cmt2_platform_data = {
386f60aa 126 .channels_mask = 0x20,
2b7eda63
MD		 127};
128
0ed61fc9 129static struct resource cmt2_resources[] = {
386f60aa
LP		 130 DEFINE_RES_MEM(0xe6130000, 0x50),
131 DEFINE_RES_IRQ(evt2irq(0x0b80)),
2b7eda63
MD		 132};
133
0ed61fc9 134static struct platform_device cmt2_device = {
386f60aa 135 .name = "sh-cmt-32-fast",
0ed61fc9 136 .id = 2,
2b7eda63 137 .dev = {
0ed61fc9 138 .platform_data = &cmt2_platform_data,
2b7eda63 139 },
0ed61fc9
MD		 140 .resource = cmt2_resources,
141 .num_resources = ARRAY_SIZE(cmt2_resources),
2b7eda63
MD		 142};
143
c6c049ec 144/* TMU */
8e8236a9
LP		 145static struct sh_timer_config tmu0_platform_data = {
146 .channels_mask = 7,
c6c049ec
MD		 147};
148
8e8236a9
LP		 149static struct resource tmu0_resources[] = {
150 DEFINE_RES_MEM(0xfff60000, 0x2c),
151 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
152 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
153 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
c6c049ec
MD		 154};
155
8e8236a9
LP		 156static struct platform_device tmu0_device = {
157 .name = "sh-tmu",
c6c049ec
MD		 158 .id = 0,
159 .dev = {
8e8236a9 160 .platform_data = &tmu0_platform_data,
c6c049ec 161 },
8e8236a9
LP		 162 .resource = tmu0_resources,
163 .num_resources = ARRAY_SIZE(tmu0_resources),
c6c049ec
MD		 164};
165
c1909cc1
KM		 166/* I2C */
167static struct resource iic0_resources[] = {
168 [0] = {
169 .name = "IIC0",
170 .start = 0xFFF20000,
171 .end = 0xFFF20425 - 1,
172 .flags = IORESOURCE_MEM,
173 },
174 [1] = {
33c9607a
MD		 175 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
176 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
c1909cc1
KM		 177 .flags = IORESOURCE_IRQ,
178 },
179};
180
181static struct platform_device iic0_device = {
182 .name = "i2c-sh_mobile",
183 .id = 0, /* "i2c0" clock */
184 .num_resources = ARRAY_SIZE(iic0_resources),
185 .resource = iic0_resources,
186};
187
188static struct resource iic1_resources[] = {
189 [0] = {
190 .name = "IIC1",
191 .start = 0xE6C20000,
192 .end = 0xE6C20425 - 1,
193 .flags = IORESOURCE_MEM,
194 },
195 [1] = {
33c9607a
MD		 196 .start = evt2irq(0x780), /* IIC1_ALI1 */
197 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
c1909cc1
KM		 198 .flags = IORESOURCE_IRQ,
199 },
200};
201
202static struct platform_device iic1_device = {
203 .name = "i2c-sh_mobile",
204 .id = 1, /* "i2c1" clock */
205 .num_resources = ARRAY_SIZE(iic1_resources),
206 .resource = iic1_resources,
207};
208
69bf6f45 209/* DMA */
69bf6f45
GL		 210static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
211 {
8d3e17ba
GL		 212 .slave_id = SHDMA_SLAVE_SCIF0_TX,
213 .addr = 0xe6c40020,
c317fc59 214 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 215 .mid_rid = 0x21,
216 }, {
217 .slave_id = SHDMA_SLAVE_SCIF0_RX,
218 .addr = 0xe6c40024,
c317fc59 219 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 220 .mid_rid = 0x22,
221 }, {
222 .slave_id = SHDMA_SLAVE_SCIF1_TX,
223 .addr = 0xe6c50020,
c317fc59 224 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 225 .mid_rid = 0x25,
226 }, {
227 .slave_id = SHDMA_SLAVE_SCIF1_RX,
228 .addr = 0xe6c50024,
c317fc59 229 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 230 .mid_rid = 0x26,
231 }, {
232 .slave_id = SHDMA_SLAVE_SCIF2_TX,
233 .addr = 0xe6c60020,
c317fc59 234 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 235 .mid_rid = 0x29,
236 }, {
237 .slave_id = SHDMA_SLAVE_SCIF2_RX,
238 .addr = 0xe6c60024,
c317fc59 239 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 240 .mid_rid = 0x2a,
241 }, {
242 .slave_id = SHDMA_SLAVE_SCIF3_TX,
243 .addr = 0xe6c70020,
c317fc59 244 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 245 .mid_rid = 0x2d,
246 }, {
247 .slave_id = SHDMA_SLAVE_SCIF3_RX,
248 .addr = 0xe6c70024,
c317fc59 249 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 250 .mid_rid = 0x2e,
251 }, {
252 .slave_id = SHDMA_SLAVE_SCIF4_TX,
253 .addr = 0xe6c80020,
c317fc59 254 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 255 .mid_rid = 0x39,
256 }, {
257 .slave_id = SHDMA_SLAVE_SCIF4_RX,
258 .addr = 0xe6c80024,
c317fc59 259 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 260 .mid_rid = 0x3a,
261 }, {
262 .slave_id = SHDMA_SLAVE_SCIF5_TX,
263 .addr = 0xe6cb0020,
c317fc59 264 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 265 .mid_rid = 0x35,
266 }, {
267 .slave_id = SHDMA_SLAVE_SCIF5_RX,
268 .addr = 0xe6cb0024,
c317fc59 269 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba
GL		 270 .mid_rid = 0x36,
271 }, {
272 .slave_id = SHDMA_SLAVE_SCIF6_TX,
273 .addr = 0xe6c30040,
c317fc59 274 .chcr = CHCR_TX(XMIT_SZ_8BIT),
8d3e17ba
GL		 275 .mid_rid = 0x3d,
276 }, {
277 .slave_id = SHDMA_SLAVE_SCIF6_RX,
278 .addr = 0xe6c30060,
c317fc59 279 .chcr = CHCR_RX(XMIT_SZ_8BIT),
8d3e17ba 280 .mid_rid = 0x3e,
40eaed7f
BH		 281 }, {
282 .slave_id = SHDMA_SLAVE_FLCTL0_TX,
283 .addr = 0xe6a30050,
284 .chcr = CHCR_TX(XMIT_SZ_32BIT),
285 .mid_rid = 0x83,
286 }, {
287 .slave_id = SHDMA_SLAVE_FLCTL0_RX,
288 .addr = 0xe6a30050,
289 .chcr = CHCR_RX(XMIT_SZ_32BIT),
290 .mid_rid = 0x83,
291 }, {
292 .slave_id = SHDMA_SLAVE_FLCTL1_TX,
293 .addr = 0xe6a30060,
294 .chcr = CHCR_TX(XMIT_SZ_32BIT),
295 .mid_rid = 0x87,
296 }, {
297 .slave_id = SHDMA_SLAVE_FLCTL1_RX,
298 .addr = 0xe6a30060,
299 .chcr = CHCR_RX(XMIT_SZ_32BIT),
300 .mid_rid = 0x87,
8d3e17ba 301 }, {
69bf6f45
GL		 302 .slave_id = SHDMA_SLAVE_SDHI0_TX,
303 .addr = 0xe6850030,
c317fc59 304 .chcr = CHCR_TX(XMIT_SZ_16BIT),
69bf6f45
GL		 305 .mid_rid = 0xc1,
306 }, {
307 .slave_id = SHDMA_SLAVE_SDHI0_RX,
308 .addr = 0xe6850030,
c317fc59 309 .chcr = CHCR_RX(XMIT_SZ_16BIT),
69bf6f45
GL		 310 .mid_rid = 0xc2,
311 }, {
312 .slave_id = SHDMA_SLAVE_SDHI1_TX,
313 .addr = 0xe6860030,
c317fc59 314 .chcr = CHCR_TX(XMIT_SZ_16BIT),
69bf6f45
GL		 315 .mid_rid = 0xc9,
316 }, {
317 .slave_id = SHDMA_SLAVE_SDHI1_RX,
318 .addr = 0xe6860030,
c317fc59 319 .chcr = CHCR_RX(XMIT_SZ_16BIT),
69bf6f45
GL		 320 .mid_rid = 0xca,
321 }, {
322 .slave_id = SHDMA_SLAVE_SDHI2_TX,
323 .addr = 0xe6870030,
c317fc59 324 .chcr = CHCR_TX(XMIT_SZ_16BIT),
69bf6f45
GL		 325 .mid_rid = 0xcd,
326 }, {
327 .slave_id = SHDMA_SLAVE_SDHI2_RX,
328 .addr = 0xe6870030,
c317fc59 329 .chcr = CHCR_RX(XMIT_SZ_16BIT),
69bf6f45 330 .mid_rid = 0xce,
880452b6
KM		 331 }, {
332 .slave_id = SHDMA_SLAVE_FSIA_TX,
333 .addr = 0xfe1f0024,
c317fc59 334 .chcr = CHCR_TX(XMIT_SZ_32BIT),
880452b6
KM		 335 .mid_rid = 0xb1,
336 }, {
337 .slave_id = SHDMA_SLAVE_FSIA_RX,
338 .addr = 0xfe1f0020,
c317fc59 339 .chcr = CHCR_RX(XMIT_SZ_32BIT),
880452b6 340 .mid_rid = 0xb2,
6d11dc14
GL		 341 }, {
342 .slave_id = SHDMA_SLAVE_MMCIF_TX,
343 .addr = 0xe6bd0034,
c317fc59 344 .chcr = CHCR_TX(XMIT_SZ_32BIT),
6d11dc14
GL		 345 .mid_rid = 0xd1,
346 }, {
347 .slave_id = SHDMA_SLAVE_MMCIF_RX,
348 .addr = 0xe6bd0034,
c317fc59 349 .chcr = CHCR_RX(XMIT_SZ_32BIT),
6d11dc14 350 .mid_rid = 0xd2,
69bf6f45
GL		 351 },
352};
353
4d6344f3 354#define SH7372_CHCLR (0x220 - 0x20)
e08b881a 355
69bf6f45
GL		 356static const struct sh_dmae_channel sh7372_dmae_channels[] = {
357 {
358 .offset = 0,
359 .dmars = 0,
360 .dmars_bit = 0,
e08b881a 361 .chclr_offset = SH7372_CHCLR + 0,
69bf6f45
GL		 362 }, {
363 .offset = 0x10,
364 .dmars = 0,
365 .dmars_bit = 8,
e08b881a 366 .chclr_offset = SH7372_CHCLR + 0x10,
69bf6f45
GL		 367 }, {
368 .offset = 0x20,
369 .dmars = 4,
370 .dmars_bit = 0,
e08b881a 371 .chclr_offset = SH7372_CHCLR + 0x20,
69bf6f45
GL		 372 }, {
373 .offset = 0x30,
374 .dmars = 4,
375 .dmars_bit = 8,
e08b881a 376 .chclr_offset = SH7372_CHCLR + 0x30,
69bf6f45
GL		 377 }, {
378 .offset = 0x50,
379 .dmars = 8,
380 .dmars_bit = 0,
e08b881a 381 .chclr_offset = SH7372_CHCLR + 0x50,
69bf6f45
GL		 382 }, {
383 .offset = 0x60,
384 .dmars = 8,
385 .dmars_bit = 8,
e08b881a 386 .chclr_offset = SH7372_CHCLR + 0x60,
69bf6f45
GL		 387 }
388};
389
69bf6f45
GL		 390static struct sh_dmae_pdata dma_platform_data = {
391 .slave = sh7372_dmae_slaves,
392 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
393 .channel = sh7372_dmae_channels,
394 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
c317fc59
KM		 395 .ts_low_shift = TS_LOW_SHIFT,
396 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
397 .ts_high_shift = TS_HI_SHIFT,
398 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
399 .ts_shift = dma_ts_shift,
400 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
69bf6f45 401 .dmaor_init = DMAOR_DME,
e08b881a 402 .chclr_present = 1,
69bf6f45
GL		 403};
404
405/* Resource order important! */
406static struct resource sh7372_dmae0_resources[] = {
407 {
408 /* Channel registers and DMAOR */
409 .start = 0xfe008020,
e08b881a 410 .end = 0xfe00828f,
69bf6f45
GL		 411 .flags = IORESOURCE_MEM,
412 },
413 {
414 /* DMARSx */
415 .start = 0xfe009000,
416 .end = 0xfe00900b,
417 .flags = IORESOURCE_MEM,
418 },
419 {
20052462 420 .name = "error_irq",
f989ae5b
MD		 421 .start = evt2irq(0x20c0),
422 .end = evt2irq(0x20c0),
69bf6f45
GL		 423 .flags = IORESOURCE_IRQ,
424 },
425 {
426 /* IRQ for channels 0-5 */
f989ae5b
MD		 427 .start = evt2irq(0x2000),
428 .end = evt2irq(0x20a0),
69bf6f45
GL		 429 .flags = IORESOURCE_IRQ,
430 },
431};
432
433/* Resource order important! */
434static struct resource sh7372_dmae1_resources[] = {
435 {
436 /* Channel registers and DMAOR */
437 .start = 0xfe018020,
e08b881a 438 .end = 0xfe01828f,
69bf6f45
GL		 439 .flags = IORESOURCE_MEM,
440 },
441 {
442 /* DMARSx */
443 .start = 0xfe019000,
444 .end = 0xfe01900b,
445 .flags = IORESOURCE_MEM,
446 },
447 {
20052462 448 .name = "error_irq",
f989ae5b
MD		 449 .start = evt2irq(0x21c0),
450 .end = evt2irq(0x21c0),
69bf6f45
GL		 451 .flags = IORESOURCE_IRQ,
452 },
453 {
454 /* IRQ for channels 0-5 */
f989ae5b
MD		 455 .start = evt2irq(0x2100),
456 .end = evt2irq(0x21a0),
69bf6f45
GL		 457 .flags = IORESOURCE_IRQ,
458 },
459};
460
461/* Resource order important! */
462static struct resource sh7372_dmae2_resources[] = {
463 {
464 /* Channel registers and DMAOR */
465 .start = 0xfe028020,
e08b881a 466 .end = 0xfe02828f,
69bf6f45
GL		 467 .flags = IORESOURCE_MEM,
468 },
469 {
470 /* DMARSx */
471 .start = 0xfe029000,
472 .end = 0xfe02900b,
473 .flags = IORESOURCE_MEM,
474 },
475 {
20052462 476 .name = "error_irq",
f989ae5b
MD		 477 .start = evt2irq(0x22c0),
478 .end = evt2irq(0x22c0),
69bf6f45
GL		 479 .flags = IORESOURCE_IRQ,
480 },
481 {
482 /* IRQ for channels 0-5 */
f989ae5b
MD		 483 .start = evt2irq(0x2200),
484 .end = evt2irq(0x22a0),
69bf6f45
GL		 485 .flags = IORESOURCE_IRQ,
486 },
487};
488
489static struct platform_device dma0_device = {
490 .name = "sh-dma-engine",
491 .id = 0,
492 .resource = sh7372_dmae0_resources,
493 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
494 .dev = {
495 .platform_data = &dma_platform_data,
496 },
497};
498
499static struct platform_device dma1_device = {
500 .name = "sh-dma-engine",
501 .id = 1,
502 .resource = sh7372_dmae1_resources,
503 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
504 .dev = {
505 .platform_data = &dma_platform_data,
506 },
507};
508
509static struct platform_device dma2_device = {
510 .name = "sh-dma-engine",
511 .id = 2,
512 .resource = sh7372_dmae2_resources,
513 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
514 .dev = {
515 .platform_data = &dma_platform_data,
516 },
517};
518
afe48049
KM		 519/*
520 * USB-DMAC
521 */
afe48049
KM		 522static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
523 {
524 .offset = 0,
525 }, {
526 .offset = 0x20,
527 },
528};
529
530/* USB DMAC0 */
531static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
532 {
533 .slave_id = SHDMA_SLAVE_USB0_TX,
c317fc59 534 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
afe48049
KM		 535 }, {
536 .slave_id = SHDMA_SLAVE_USB0_RX,
c317fc59 537 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
afe48049
KM		 538 },
539};
540
541static struct sh_dmae_pdata usb_dma0_platform_data = {
542 .slave = sh7372_usb_dmae0_slaves,
543 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
544 .channel = sh7372_usb_dmae_channels,
545 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
c317fc59
KM		 546 .ts_low_shift = USBTS_LOW_SHIFT,
547 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
548 .ts_high_shift = USBTS_HI_SHIFT,
549 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
550 .ts_shift = dma_usbts_shift,
551 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
afe48049
KM		 552 .dmaor_init = DMAOR_DME,
553 .chcr_offset = 0x14,
554 .chcr_ie_bit = 1 << 5,
555 .dmaor_is_32bit = 1,
556 .needs_tend_set = 1,
557 .no_dmars = 1,
c8ddf036 558 .slave_only = 1,
afe48049
KM		 559};
560
561static struct resource sh7372_usb_dmae0_resources[] = {
562 {
563 /* Channel registers and DMAOR */
564 .start = 0xe68a0020,
565 .end = 0xe68a0064 - 1,
566 .flags = IORESOURCE_MEM,
567 },
568 {
569 /* VCR/SWR/DMICR */
570 .start = 0xe68a0000,
571 .end = 0xe68a0014 - 1,
572 .flags = IORESOURCE_MEM,
573 },
574 {
575 /* IRQ for channels */
576 .start = evt2irq(0x0a00),
577 .end = evt2irq(0x0a00),
578 .flags = IORESOURCE_IRQ,
579 },
580};
581
582static struct platform_device usb_dma0_device = {
583 .name = "sh-dma-engine",
584 .id = 3,
585 .resource = sh7372_usb_dmae0_resources,
586 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
587 .dev = {
588 .platform_data = &usb_dma0_platform_data,
589 },
590};
591
592/* USB DMAC1 */
593static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
594 {
595 .slave_id = SHDMA_SLAVE_USB1_TX,
c317fc59 596 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
afe48049
KM		 597 }, {
598 .slave_id = SHDMA_SLAVE_USB1_RX,
c317fc59 599 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
afe48049
KM		 600 },
601};
602
603static struct sh_dmae_pdata usb_dma1_platform_data = {
604 .slave = sh7372_usb_dmae1_slaves,
605 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
606 .channel = sh7372_usb_dmae_channels,
607 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
c317fc59
KM		 608 .ts_low_shift = USBTS_LOW_SHIFT,
609 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
610 .ts_high_shift = USBTS_HI_SHIFT,
611 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
612 .ts_shift = dma_usbts_shift,
613 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
afe48049
KM		 614 .dmaor_init = DMAOR_DME,
615 .chcr_offset = 0x14,
616 .chcr_ie_bit = 1 << 5,
617 .dmaor_is_32bit = 1,
618 .needs_tend_set = 1,
619 .no_dmars = 1,
c8ddf036 620 .slave_only = 1,
afe48049
KM		 621};
622
623static struct resource sh7372_usb_dmae1_resources[] = {
624 {
625 /* Channel registers and DMAOR */
626 .start = 0xe68c0020,
627 .end = 0xe68c0064 - 1,
628 .flags = IORESOURCE_MEM,
629 },
630 {
631 /* VCR/SWR/DMICR */
632 .start = 0xe68c0000,
633 .end = 0xe68c0014 - 1,
634 .flags = IORESOURCE_MEM,
635 },
636 {
637 /* IRQ for channels */
638 .start = evt2irq(0x1d00),
639 .end = evt2irq(0x1d00),
640 .flags = IORESOURCE_IRQ,
641 },
642};
643
644static struct platform_device usb_dma1_device = {
645 .name = "sh-dma-engine",
646 .id = 4,
647 .resource = sh7372_usb_dmae1_resources,
648 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
649 .dev = {
650 .platform_data = &usb_dma1_platform_data,
651 },
652};
653
6822471e
MD		 654/* VPU */
655static struct uio_info vpu_platform_data = {
656 .name = "VPU5HG",
657 .version = "0",
658 .irq = intcs_evt2irq(0x980),
659};
660
661static struct resource vpu_resources[] = {
662 [0] = {
663 .name = "VPU",
664 .start = 0xfe900000,
665 .end = 0xfe900157,
666 .flags = IORESOURCE_MEM,
667 },
668};
669
670static struct platform_device vpu_device = {
671 .name = "uio_pdrv_genirq",
672 .id = 0,
673 .dev = {
674 .platform_data = &vpu_platform_data,
675 },
676 .resource = vpu_resources,
677 .num_resources = ARRAY_SIZE(vpu_resources),
678};
679
680/* VEU0 */
681static struct uio_info veu0_platform_data = {
682 .name = "VEU0",
683 .version = "0",
684 .irq = intcs_evt2irq(0x700),
685};
686
687static struct resource veu0_resources[] = {
688 [0] = {
689 .name = "VEU0",
690 .start = 0xfe920000,
691 .end = 0xfe9200cb,
692 .flags = IORESOURCE_MEM,
693 },
694};
695
696static struct platform_device veu0_device = {
697 .name = "uio_pdrv_genirq",
698 .id = 1,
699 .dev = {
700 .platform_data = &veu0_platform_data,
701 },
702 .resource = veu0_resources,
703 .num_resources = ARRAY_SIZE(veu0_resources),
704};
705
706/* VEU1 */
707static struct uio_info veu1_platform_data = {
708 .name = "VEU1",
709 .version = "0",
710 .irq = intcs_evt2irq(0x720),
711};
712
713static struct resource veu1_resources[] = {
714 [0] = {
715 .name = "VEU1",
716 .start = 0xfe924000,
717 .end = 0xfe9240cb,
718 .flags = IORESOURCE_MEM,
719 },
720};
721
722static struct platform_device veu1_device = {
723 .name = "uio_pdrv_genirq",
724 .id = 2,
725 .dev = {
726 .platform_data = &veu1_platform_data,
727 },
728 .resource = veu1_resources,
729 .num_resources = ARRAY_SIZE(veu1_resources),
730};
731
732/* VEU2 */
733static struct uio_info veu2_platform_data = {
734 .name = "VEU2",
735 .version = "0",
736 .irq = intcs_evt2irq(0x740),
737};
738
739static struct resource veu2_resources[] = {
740 [0] = {
741 .name = "VEU2",
742 .start = 0xfe928000,
743 .end = 0xfe928307,
744 .flags = IORESOURCE_MEM,
745 },
746};
747
748static struct platform_device veu2_device = {
749 .name = "uio_pdrv_genirq",
750 .id = 3,
751 .dev = {
752 .platform_data = &veu2_platform_data,
753 },
754 .resource = veu2_resources,
755 .num_resources = ARRAY_SIZE(veu2_resources),
756};
757
758/* VEU3 */
759static struct uio_info veu3_platform_data = {
760 .name = "VEU3",
761 .version = "0",
762 .irq = intcs_evt2irq(0x760),
763};
764
765static struct resource veu3_resources[] = {
766 [0] = {
767 .name = "VEU3",
768 .start = 0xfe92c000,
769 .end = 0xfe92c307,
770 .flags = IORESOURCE_MEM,
771 },
772};
773
774static struct platform_device veu3_device = {
775 .name = "uio_pdrv_genirq",
776 .id = 4,
777 .dev = {
778 .platform_data = &veu3_platform_data,
779 },
780 .resource = veu3_resources,
781 .num_resources = ARRAY_SIZE(veu3_resources),
782};
783
784/* JPU */
785static struct uio_info jpu_platform_data = {
786 .name = "JPU",
787 .version = "0",
788 .irq = intcs_evt2irq(0x560),
789};
790
791static struct resource jpu_resources[] = {
792 [0] = {
793 .name = "JPU",
794 .start = 0xfe980000,
795 .end = 0xfe9902d3,
796 .flags = IORESOURCE_MEM,
797 },
798};
799
800static struct platform_device jpu_device = {
801 .name = "uio_pdrv_genirq",
802 .id = 5,
803 .dev = {
804 .platform_data = &jpu_platform_data,
805 },
806 .resource = jpu_resources,
807 .num_resources = ARRAY_SIZE(jpu_resources),
808};
809
810/* SPU2DSP0 */
811static struct uio_info spu0_platform_data = {
812 .name = "SPU2DSP0",
813 .version = "0",
814 .irq = evt2irq(0x1800),
815};
816
817static struct resource spu0_resources[] = {
818 [0] = {
819 .name = "SPU2DSP0",
820 .start = 0xfe200000,
821 .end = 0xfe2fffff,
822 .flags = IORESOURCE_MEM,
823 },
824};
825
826static struct platform_device spu0_device = {
827 .name = "uio_pdrv_genirq",
828 .id = 6,
829 .dev = {
830 .platform_data = &spu0_platform_data,
831 },
832 .resource = spu0_resources,
833 .num_resources = ARRAY_SIZE(spu0_resources),
834};
835
836/* SPU2DSP1 */
837static struct uio_info spu1_platform_data = {
838 .name = "SPU2DSP1",
839 .version = "0",
840 .irq = evt2irq(0x1820),
841};
842
843static struct resource spu1_resources[] = {
844 [0] = {
845 .name = "SPU2DSP1",
846 .start = 0xfe300000,
847 .end = 0xfe3fffff,
848 .flags = IORESOURCE_MEM,
849 },
850};
851
852static struct platform_device spu1_device = {
853 .name = "uio_pdrv_genirq",
854 .id = 7,
855 .dev = {
856 .platform_data = &spu1_platform_data,
857 },
858 .resource = spu1_resources,
859 .num_resources = ARRAY_SIZE(spu1_resources),
860};
861
3cfb8439
HE		 862/* IPMMUI (an IPMMU module for ICB/LMB) */
863static struct resource ipmmu_resources[] = {
864 [0] = {
865 .name = "IPMMUI",
866 .start = 0xfe951000,
867 .end = 0xfe9510ff,
868 .flags = IORESOURCE_MEM,
869 },
870};
871
872static const char * const ipmmu_dev_names[] = {
873 "sh_mobile_lcdc_fb.0",
874 "sh_mobile_lcdc_fb.1",
875 "sh_mobile_ceu.0",
876 "uio_pdrv_genirq.0",
877 "uio_pdrv_genirq.1",
878 "uio_pdrv_genirq.2",
879 "uio_pdrv_genirq.3",
880 "uio_pdrv_genirq.4",
881 "uio_pdrv_genirq.5",
882};
883
884static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
885 .dev_names = ipmmu_dev_names,
886 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
887};
888
889static struct platform_device ipmmu_device = {
890 .name = "ipmmu",
891 .id = -1,
892 .dev = {
893 .platform_data = &ipmmu_platform_data,
894 },
895 .resource = ipmmu_resources,
896 .num_resources = ARRAY_SIZE(ipmmu_resources),
897};
898
2b7eda63
MD		 899static struct platform_device *sh7372_early_devices[] __initdata = {
900 &scif0_device,
901 &scif1_device,
902 &scif2_device,
903 &scif3_device,
904 &scif4_device,
905 &scif5_device,
906 &scif6_device,
0ed61fc9 907 &cmt2_device,
8e8236a9 908 &tmu0_device,
3cfb8439 909 &ipmmu_device,
934e4078
MD		 910};
911
912static struct platform_device *sh7372_late_devices[] __initdata = {
c1909cc1
KM		 913 &iic0_device,
914 &iic1_device,
69bf6f45
GL		 915 &dma0_device,
916 &dma1_device,
917 &dma2_device,
afe48049
KM		 918 &usb_dma0_device,
919 &usb_dma1_device,
6822471e
MD		 920 &vpu_device,
921 &veu0_device,
922 &veu1_device,
923 &veu2_device,
924 &veu3_device,
925 &jpu_device,
926 &spu0_device,
927 &spu1_device,
2b7eda63
MD		 928};
929
930void __init sh7372_add_standard_devices(void)
931{
9eda01b2 932 static struct pm_domain_device domain_devices[] __initdata = {
ac18e02d
RW		 933 { "A3RV", &vpu_device, },
934 { "A4MP", &spu0_device, },
935 { "A4MP", &spu1_device, },
936 { "A3SP", &scif0_device, },
937 { "A3SP", &scif1_device, },
938 { "A3SP", &scif2_device, },
939 { "A3SP", &scif3_device, },
940 { "A3SP", &scif4_device, },
941 { "A3SP", &scif5_device, },
942 { "A3SP", &scif6_device, },
943 { "A3SP", &iic1_device, },
944 { "A3SP", &dma0_device, },
945 { "A3SP", &dma1_device, },
946 { "A3SP", &dma2_device, },
947 { "A3SP", &usb_dma0_device, },
948 { "A3SP", &usb_dma1_device, },
949 { "A4R", &iic0_device, },
950 { "A4R", &veu0_device, },
951 { "A4R", &veu1_device, },
952 { "A4R", &veu2_device, },
953 { "A4R", &veu3_device, },
954 { "A4R", &jpu_device, },
8e8236a9 955 { "A4R", &tmu0_device, },
c37b7a7b
RW		 956 };
957
e7e59a4b 958 sh7372_init_pm_domains();
f7dadb37 959
2b7eda63
MD		 960 platform_add_devices(sh7372_early_devices,
961 ARRAY_SIZE(sh7372_early_devices));
934e4078
MD		 962
963 platform_add_devices(sh7372_late_devices,
964 ARRAY_SIZE(sh7372_late_devices));
33afebf3 965
ac18e02d
RW		 966 rmobile_add_devices_to_domains(domain_devices,
967 ARRAY_SIZE(domain_devices));
2b7eda63
MD		 968}
969
6bb27d73 970void __init sh7372_earlytimer_init(void)
17254bff
MD		 971{
972 sh7372_clock_init();
973 shmobile_earlytimer_init();
974}
975
2b7eda63
MD		 976void __init sh7372_add_early_devices(void)
977{
2b7eda63
MD		 978 early_platform_add_devices(sh7372_early_devices,
979 ARRAY_SIZE(sh7372_early_devices));
5d7220ec
MD		 980
981 /* setup early console here as well */
982 shmobile_setup_console();
2b7eda63 983}
3b7b7055
MD		 984
985#ifdef CONFIG_USE_OF
986
987void __init sh7372_add_early_devices_dt(void)
988{
39b22e20 989 shmobile_init_delay();
3b7b7055 990
1fba31f0 991 sh7372_add_early_devices();
3b7b7055
MD		 992}
993
3b7b7055
MD		 994void __init sh7372_add_standard_devices_dt(void)
995{
996 /* clocks are setup late during boot in the case of DT */
997 sh7372_clock_init();
998
999 platform_add_devices(sh7372_early_devices,
1000 ARRAY_SIZE(sh7372_early_devices));
1001
975e5af9 1002 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
3b7b7055
MD		 1003}
1004
1005static const char *sh7372_boards_compat_dt[] __initdata = {
1006 "renesas,sh7372",
1007 NULL,
1008};
1009
1010DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1011 .map_io = sh7372_map_io,
1012 .init_early = sh7372_add_early_devices_dt,
3b7b7055
MD		 1013 .init_irq = sh7372_init_irq,
1014 .handle_irq = shmobile_handle_irq_intc,
1015 .init_machine = sh7372_add_standard_devices_dt,
27c1bb20 1016 .init_late = shmobile_init_late,
3b7b7055
MD		 1017 .dt_compat = sh7372_boards_compat_dt,
1018MACHINE_END
1019
1020#endif /* CONFIG_USE_OF */
Linux 6.x block layer and io_uring tree(s)