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Merge branch 'driver-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-block.git] / arch / arm / mach-shmobile / setup-sh7367.c
CommitLineData
c793c1b0
MD		 1/*
2 * sh7367 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/input.h>
27#include <linux/io.h>
28#include <linux/serial_sci.h>
c793c1b0
MD		 29#include <linux/sh_timer.h>
30#include <mach/hardware.h>
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33
7490509f 34/* SCIFA0 */
c793c1b0
MD		 35static struct plat_sci_port scif0_platform_data = {
36 .mapbase = 0xe6c40000,
37 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 38 .scscr = SCSCR_RE | SCSCR_TE,
39 .scbrr_algo_id = SCBRR_ALGO_4,
c793c1b0 40 .type = PORT_SCIF,
7490509f
MD		 41 .irqs = { evt2irq(0xc00), evt2irq(0xc00),
42 evt2irq(0xc00), evt2irq(0xc00) },
c793c1b0
MD		 43};
44
45static struct platform_device scif0_device = {
46 .name = "sh-sci",
47 .id = 0,
48 .dev = {
49 .platform_data = &scif0_platform_data,
50 },
51};
52
7490509f 53/* SCIFA1 */
c793c1b0
MD		 54static struct plat_sci_port scif1_platform_data = {
55 .mapbase = 0xe6c50000,
56 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 57 .scscr = SCSCR_RE | SCSCR_TE,
58 .scbrr_algo_id = SCBRR_ALGO_4,
c793c1b0 59 .type = PORT_SCIF,
7490509f
MD		 60 .irqs = { evt2irq(0xc20), evt2irq(0xc20),
61 evt2irq(0xc20), evt2irq(0xc20) },
c793c1b0
MD		 62};
63
64static struct platform_device scif1_device = {
65 .name = "sh-sci",
66 .id = 1,
67 .dev = {
68 .platform_data = &scif1_platform_data,
69 },
70};
71
7490509f 72/* SCIFA2 */
c793c1b0
MD		 73static struct plat_sci_port scif2_platform_data = {
74 .mapbase = 0xe6c60000,
75 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 76 .scscr = SCSCR_RE | SCSCR_TE,
77 .scbrr_algo_id = SCBRR_ALGO_4,
c793c1b0 78 .type = PORT_SCIF,
7490509f
MD		 79 .irqs = { evt2irq(0xc40), evt2irq(0xc40),
80 evt2irq(0xc40), evt2irq(0xc40) },
c793c1b0
MD		 81};
82
83static struct platform_device scif2_device = {
84 .name = "sh-sci",
85 .id = 2,
86 .dev = {
87 .platform_data = &scif2_platform_data,
88 },
89};
90
7490509f 91/* SCIFA3 */
c793c1b0
MD		 92static struct plat_sci_port scif3_platform_data = {
93 .mapbase = 0xe6c70000,
94 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 95 .scscr = SCSCR_RE | SCSCR_TE,
96 .scbrr_algo_id = SCBRR_ALGO_4,
c793c1b0 97 .type = PORT_SCIF,
7490509f
MD		 98 .irqs = { evt2irq(0xc60), evt2irq(0xc60),
99 evt2irq(0xc60), evt2irq(0xc60) },
c793c1b0
MD		 100};
101
102static struct platform_device scif3_device = {
103 .name = "sh-sci",
104 .id = 3,
105 .dev = {
106 .platform_data = &scif3_platform_data,
107 },
108};
109
7490509f 110/* SCIFA4 */
c793c1b0
MD		 111static struct plat_sci_port scif4_platform_data = {
112 .mapbase = 0xe6c80000,
113 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 114 .scscr = SCSCR_RE | SCSCR_TE,
115 .scbrr_algo_id = SCBRR_ALGO_4,
c793c1b0 116 .type = PORT_SCIF,
7490509f
MD		 117 .irqs = { evt2irq(0xd20), evt2irq(0xd20),
118 evt2irq(0xd20), evt2irq(0xd20) },
c793c1b0
MD		 119};
120
121static struct platform_device scif4_device = {
122 .name = "sh-sci",
123 .id = 4,
124 .dev = {
125 .platform_data = &scif4_platform_data,
126 },
127};
128
7490509f 129/* SCIFA5 */
c793c1b0
MD		 130static struct plat_sci_port scif5_platform_data = {
131 .mapbase = 0xe6cb0000,
132 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 133 .scscr = SCSCR_RE | SCSCR_TE,
134 .scbrr_algo_id = SCBRR_ALGO_4,
c793c1b0 135 .type = PORT_SCIF,
7490509f
MD		 136 .irqs = { evt2irq(0xd40), evt2irq(0xd40),
137 evt2irq(0xd40), evt2irq(0xd40) },
c793c1b0
MD		 138};
139
140static struct platform_device scif5_device = {
141 .name = "sh-sci",
142 .id = 5,
143 .dev = {
144 .platform_data = &scif5_platform_data,
145 },
146};
147
7490509f 148/* SCIFB */
c793c1b0
MD		 149static struct plat_sci_port scif6_platform_data = {
150 .mapbase = 0xe6c30000,
151 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 152 .scscr = SCSCR_RE | SCSCR_TE,
153 .scbrr_algo_id = SCBRR_ALGO_4,
c793c1b0 154 .type = PORT_SCIF,
7490509f
MD		 155 .irqs = { evt2irq(0xd60), evt2irq(0xd60),
156 evt2irq(0xd60), evt2irq(0xd60) },
c793c1b0
MD		 157};
158
159static struct platform_device scif6_device = {
160 .name = "sh-sci",
161 .id = 6,
162 .dev = {
163 .platform_data = &scif6_platform_data,
164 },
165};
166
167static struct sh_timer_config cmt10_platform_data = {
168 .name = "CMT10",
169 .channel_offset = 0x10,
170 .timer_bit = 0,
c793c1b0
MD		 171 .clockevent_rating = 125,
172 .clocksource_rating = 125,
173};
174
175static struct resource cmt10_resources[] = {
176 [0] = {
177 .name = "CMT10",
178 .start = 0xe6138010,
179 .end = 0xe613801b,
180 .flags = IORESOURCE_MEM,
181 },
182 [1] = {
7490509f 183 .start = evt2irq(0xb00), /* CMT1_CMT10 */
c793c1b0
MD		 184 .flags = IORESOURCE_IRQ,
185 },
186};
187
188static struct platform_device cmt10_device = {
189 .name = "sh_cmt",
190 .id = 10,
191 .dev = {
192 .platform_data = &cmt10_platform_data,
193 },
194 .resource = cmt10_resources,
195 .num_resources = ARRAY_SIZE(cmt10_resources),
196};
197
198static struct platform_device *sh7367_early_devices[] __initdata = {
199 &scif0_device,
200 &scif1_device,
201 &scif2_device,
202 &scif3_device,
203 &scif4_device,
204 &scif5_device,
205 &scif6_device,
206 &cmt10_device,
207};
208
209void __init sh7367_add_standard_devices(void)
210{
211 platform_add_devices(sh7367_early_devices,
212 ARRAY_SIZE(sh7367_early_devices));
213}
214
215#define SYMSTPCR2 0xe6158048
216#define SYMSTPCR2_CMT1 (1 << 29)
217
218void __init sh7367_add_early_devices(void)
219{
220 /* enable clock to CMT1 */
221 __raw_writel(__raw_readl(SYMSTPCR2) & ~SYMSTPCR2_CMT1, SYMSTPCR2);
222
223 early_platform_add_devices(sh7367_early_devices,
224 ARRAY_SIZE(sh7367_early_devices));
225}
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