Commit | Line | Data |
---|---|---|
50c517d9 MD |
1 | /* |
2 | * R-Car Generation 2 support | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
5 | * Copyright (C) 2013 Magnus Damm | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | */ | |
20 | ||
4b5c211f | 21 | #include <linux/clk/shmobile.h> |
50c517d9 | 22 | #include <linux/clocksource.h> |
f8e81935 MD |
23 | #include <linux/device.h> |
24 | #include <linux/dma-contiguous.h> | |
50c517d9 MD |
25 | #include <linux/io.h> |
26 | #include <linux/kernel.h> | |
f8e81935 | 27 | #include <linux/of_fdt.h> |
50c517d9 | 28 | #include <asm/mach/arch.h> |
fd44aa5e | 29 | #include "common.h" |
62872989 | 30 | #include "rcar-gen2.h" |
50c517d9 MD |
31 | |
32 | #define MODEMR 0xe6160060 | |
33 | ||
e7509f6e | 34 | u32 rcar_gen2_read_mode_pins(void) |
50c517d9 | 35 | { |
835d737d GU |
36 | static u32 mode; |
37 | static bool mode_valid; | |
50c517d9 | 38 | |
835d737d GU |
39 | if (!mode_valid) { |
40 | void __iomem *modemr = ioremap_nocache(MODEMR, 4); | |
41 | BUG_ON(!modemr); | |
42 | mode = ioread32(modemr); | |
43 | iounmap(modemr); | |
44 | mode_valid = true; | |
45 | } | |
50c517d9 MD |
46 | |
47 | return mode; | |
48 | } | |
49 | ||
50 | #define CNTCR 0 | |
51 | #define CNTFID0 0x20 | |
52 | ||
53 | void __init rcar_gen2_timer_init(void) | |
54 | { | |
4b5c211f | 55 | #if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK) |
50c517d9 | 56 | u32 mode = rcar_gen2_read_mode_pins(); |
4b5c211f LP |
57 | #endif |
58 | #ifdef CONFIG_ARM_ARCH_TIMER | |
50c517d9 MD |
59 | void __iomem *base; |
60 | int extal_mhz = 0; | |
61 | u32 freq; | |
62 | ||
63 | /* At Linux boot time the r8a7790 arch timer comes up | |
64 | * with the counter disabled. Moreover, it may also report | |
65 | * a potentially incorrect fixed 13 MHz frequency. To be | |
66 | * correct these registers need to be updated to use the | |
67 | * frequency EXTAL / 2 which can be determined by the MD pins. | |
68 | */ | |
69 | ||
70 | switch (mode & (MD(14) | MD(13))) { | |
71 | case 0: | |
72 | extal_mhz = 15; | |
73 | break; | |
74 | case MD(13): | |
75 | extal_mhz = 20; | |
76 | break; | |
77 | case MD(14): | |
78 | extal_mhz = 26; | |
79 | break; | |
80 | case MD(13) | MD(14): | |
81 | extal_mhz = 30; | |
82 | break; | |
83 | } | |
84 | ||
85 | /* The arch timer frequency equals EXTAL / 2 */ | |
86 | freq = extal_mhz * (1000000 / 2); | |
87 | ||
88 | /* Remap "armgcnt address map" space */ | |
89 | base = ioremap(0xe6080000, PAGE_SIZE); | |
90 | ||
0fe35077 BD |
91 | /* |
92 | * Update the timer if it is either not running, or is not at the | |
93 | * right frequency. The timer is only configurable in secure mode | |
94 | * so this avoids an abort if the loader started the timer and | |
95 | * entered the kernel in non-secure mode. | |
96 | */ | |
97 | ||
98 | if ((ioread32(base + CNTCR) & 1) == 0 || | |
99 | ioread32(base + CNTFID0) != freq) { | |
100 | /* Update registers with correct frequency */ | |
101 | iowrite32(freq, base + CNTFID0); | |
102 | asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); | |
103 | ||
104 | /* make sure arch timer is started by setting bit 0 of CNTCR */ | |
105 | iowrite32(1, base + CNTCR); | |
106 | } | |
50c517d9 | 107 | |
50c517d9 MD |
108 | iounmap(base); |
109 | #endif /* CONFIG_ARM_ARCH_TIMER */ | |
110 | ||
4b5c211f LP |
111 | #ifdef CONFIG_COMMON_CLK |
112 | rcar_gen2_clocks_init(mode); | |
113 | #endif | |
50c517d9 MD |
114 | clocksource_of_init(); |
115 | } | |
83850b04 GU |
116 | |
117 | struct memory_reserve_config { | |
118 | u64 reserved; | |
119 | u64 base, size; | |
120 | }; | |
121 | ||
122 | static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname, | |
123 | int depth, void *data) | |
124 | { | |
125 | const char *type = of_get_flat_dt_prop(node, "device_type", NULL); | |
126 | const __be32 *reg, *endp; | |
127 | int l; | |
128 | struct memory_reserve_config *mrc = data; | |
b69f47c0 | 129 | u64 lpae_start = 1ULL << 32; |
83850b04 GU |
130 | |
131 | /* We are scanning "memory" nodes only */ | |
ea2a0d58 | 132 | if (type == NULL || strcmp(type, "memory")) |
83850b04 GU |
133 | return 0; |
134 | ||
135 | reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l); | |
136 | if (reg == NULL) | |
137 | reg = of_get_flat_dt_prop(node, "reg", &l); | |
138 | if (reg == NULL) | |
139 | return 0; | |
140 | ||
141 | endp = reg + (l / sizeof(__be32)); | |
142 | while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) { | |
143 | u64 base, size; | |
144 | ||
145 | base = dt_mem_next_cell(dt_root_addr_cells, ®); | |
146 | size = dt_mem_next_cell(dt_root_size_cells, ®); | |
147 | ||
148 | if (base >= lpae_start) | |
149 | continue; | |
150 | ||
151 | if ((base + size) >= lpae_start) | |
152 | size = lpae_start - base; | |
153 | ||
154 | if (size < mrc->reserved) | |
155 | continue; | |
156 | ||
157 | if (base < mrc->base) | |
158 | continue; | |
159 | ||
160 | /* keep the area at top near the 32-bit legacy limit */ | |
161 | mrc->base = base + size - mrc->reserved; | |
162 | mrc->size = mrc->reserved; | |
163 | } | |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
168 | struct cma *rcar_gen2_dma_contiguous; | |
169 | ||
170 | void __init rcar_gen2_reserve(void) | |
171 | { | |
172 | struct memory_reserve_config mrc; | |
173 | ||
174 | /* reserve 256 MiB at the top of the physical legacy 32-bit space */ | |
175 | memset(&mrc, 0, sizeof(mrc)); | |
176 | mrc.reserved = SZ_256M; | |
177 | ||
178 | of_scan_flat_dt(rcar_gen2_scan_mem, &mrc); | |
179 | #ifdef CONFIG_DMA_CMA | |
180 | if (mrc.size) | |
181 | dma_contiguous_reserve_area(mrc.size, mrc.base, 0, | |
14a5e926 | 182 | &rcar_gen2_dma_contiguous, true); |
83850b04 GU |
183 | #endif |
184 | } |