Commit | Line | Data |
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0468b2d6 MD |
1 | /* |
2 | * r8a7790 processor support | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
5 | * Copyright (C) 2013 Magnus Damm | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | */ | |
20 | ||
21 | #include <linux/irq.h> | |
0468b2d6 MD |
22 | #include <linux/kernel.h> |
23 | #include <linux/of_platform.h> | |
43ca9cbb | 24 | #include <linux/platform_data/gpio-rcar.h> |
8f5ec0a5 | 25 | #include <linux/platform_data/irq-renesas-irqc.h> |
99ade1a0 | 26 | #include <linux/serial_sci.h> |
2c578a1b | 27 | #include <linux/sh_dma.h> |
99ade1a0 | 28 | #include <linux/sh_timer.h> |
fccae893 | 29 | |
0468b2d6 MD |
30 | #include <asm/mach/arch.h> |
31 | ||
fd44aa5e | 32 | #include "common.h" |
74ac0de8 | 33 | #include "dma-register.h" |
b6bab126 | 34 | #include "irqs.h" |
fccae893 | 35 | #include "r8a7790.h" |
62872989 | 36 | #include "rcar-gen2.h" |
0468b2d6 | 37 | |
2c578a1b KM |
38 | /* Audio-DMAC */ |
39 | #define AUDIO_DMAC_SLAVE(_id, _addr, t, r) \ | |
40 | { \ | |
41 | .slave_id = AUDIO_DMAC_SLAVE_## _id ##_TX, \ | |
42 | .addr = _addr + 0x8, \ | |
43 | .chcr = CHCR_TX(XMIT_SZ_32BIT), \ | |
44 | .mid_rid = t, \ | |
45 | }, { \ | |
46 | .slave_id = AUDIO_DMAC_SLAVE_## _id ##_RX, \ | |
47 | .addr = _addr + 0xc, \ | |
48 | .chcr = CHCR_RX(XMIT_SZ_32BIT), \ | |
49 | .mid_rid = r, \ | |
50 | } | |
51 | ||
52 | static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = { | |
53 | AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02), | |
54 | AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04), | |
55 | AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06), | |
56 | AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08), | |
57 | AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a), | |
58 | AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c), | |
59 | AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e), | |
60 | AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10), | |
61 | AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12), | |
62 | AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14), | |
63 | }; | |
64 | ||
65 | #define DMAE_CHANNEL(a, b) \ | |
66 | { \ | |
67 | .offset = (a) - 0x20, \ | |
68 | .dmars = (a) - 0x20 + 0x40, \ | |
69 | .chclr_bit = (b), \ | |
70 | .chclr_offset = 0x80 - 0x20, \ | |
71 | } | |
72 | ||
73 | static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = { | |
74 | DMAE_CHANNEL(0x8000, 0), | |
75 | DMAE_CHANNEL(0x8080, 1), | |
76 | DMAE_CHANNEL(0x8100, 2), | |
77 | DMAE_CHANNEL(0x8180, 3), | |
78 | DMAE_CHANNEL(0x8200, 4), | |
79 | DMAE_CHANNEL(0x8280, 5), | |
80 | DMAE_CHANNEL(0x8300, 6), | |
81 | DMAE_CHANNEL(0x8380, 7), | |
82 | DMAE_CHANNEL(0x8400, 8), | |
83 | DMAE_CHANNEL(0x8480, 9), | |
84 | DMAE_CHANNEL(0x8500, 10), | |
85 | DMAE_CHANNEL(0x8580, 11), | |
86 | DMAE_CHANNEL(0x8600, 12), | |
87 | }; | |
88 | ||
89 | static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = { | |
90 | .slave = r8a7790_audio_dmac_slaves, | |
91 | .slave_num = ARRAY_SIZE(r8a7790_audio_dmac_slaves), | |
92 | .channel = r8a7790_audio_dmac_channels, | |
93 | .channel_num = ARRAY_SIZE(r8a7790_audio_dmac_channels), | |
94 | .ts_low_shift = TS_LOW_SHIFT, | |
95 | .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, | |
96 | .ts_high_shift = TS_HI_SHIFT, | |
97 | .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, | |
98 | .ts_shift = dma_ts_shift, | |
99 | .ts_shift_num = ARRAY_SIZE(dma_ts_shift), | |
100 | .dmaor_init = DMAOR_DME, | |
101 | .chclr_present = 1, | |
102 | .chclr_bitwise = 1, | |
103 | }; | |
104 | ||
105 | static struct resource r8a7790_audio_dmac_resources[] = { | |
106 | /* Channel registers and DMAOR for low */ | |
107 | DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20), | |
108 | DEFINE_RES_IRQ(gic_spi(346)), | |
109 | DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ), | |
110 | ||
111 | /* Channel registers and DMAOR for hi */ | |
112 | DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */ | |
113 | DEFINE_RES_IRQ(gic_spi(347)), | |
114 | DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ), | |
115 | }; | |
116 | ||
117 | #define r8a7790_register_audio_dmac(id) \ | |
118 | platform_device_register_resndata( \ | |
d2168146 | 119 | NULL, "sh-dma-engine", id, \ |
2c578a1b KM |
120 | &r8a7790_audio_dmac_resources[id * 3], 3, \ |
121 | &r8a7790_audio_dmac_platform_data, \ | |
122 | sizeof(r8a7790_audio_dmac_platform_data)) | |
123 | ||
cde214a8 | 124 | static const struct resource pfc_resources[] __initconst = { |
69e351d0 MD |
125 | DEFINE_RES_MEM(0xe6060000, 0x250), |
126 | }; | |
127 | ||
8d0b3bf7 MD |
128 | #define r8a7790_register_pfc() \ |
129 | platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \ | |
130 | ARRAY_SIZE(pfc_resources)) | |
131 | ||
43ca9cbb | 132 | #define R8A7790_GPIO(idx) \ |
cde214a8 | 133 | static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \ |
43ca9cbb LP |
134 | DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \ |
135 | DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ | |
136 | }; \ | |
137 | \ | |
cde214a8 LP |
138 | static const struct gpio_rcar_config \ |
139 | r8a7790_gpio##idx##_platform_data __initconst = { \ | |
43ca9cbb LP |
140 | .gpio_base = 32 * (idx), \ |
141 | .irq_base = 0, \ | |
142 | .number_of_pins = 32, \ | |
143 | .pctl_name = "pfc-r8a7790", \ | |
d93906b8 | 144 | .has_both_edge_trigger = 1, \ |
43ca9cbb LP |
145 | }; \ |
146 | ||
147 | R8A7790_GPIO(0); | |
148 | R8A7790_GPIO(1); | |
149 | R8A7790_GPIO(2); | |
150 | R8A7790_GPIO(3); | |
151 | R8A7790_GPIO(4); | |
152 | R8A7790_GPIO(5); | |
153 | ||
154 | #define r8a7790_register_gpio(idx) \ | |
d2168146 | 155 | platform_device_register_resndata(NULL, "gpio_rcar", idx, \ |
43ca9cbb LP |
156 | r8a7790_gpio##idx##_resources, \ |
157 | ARRAY_SIZE(r8a7790_gpio##idx##_resources), \ | |
158 | &r8a7790_gpio##idx##_platform_data, \ | |
159 | sizeof(r8a7790_gpio##idx##_platform_data)) | |
160 | ||
b448c904 KM |
161 | static struct resource i2c_resources[] __initdata = { |
162 | /* I2C0 */ | |
163 | DEFINE_RES_MEM(0xE6508000, 0x40), | |
164 | DEFINE_RES_IRQ(gic_spi(287)), | |
165 | /* I2C1 */ | |
166 | DEFINE_RES_MEM(0xE6518000, 0x40), | |
167 | DEFINE_RES_IRQ(gic_spi(288)), | |
168 | /* I2C2 */ | |
169 | DEFINE_RES_MEM(0xE6530000, 0x40), | |
170 | DEFINE_RES_IRQ(gic_spi(286)), | |
171 | /* I2C3 */ | |
172 | DEFINE_RES_MEM(0xE6540000, 0x40), | |
173 | DEFINE_RES_IRQ(gic_spi(290)), | |
174 | ||
175 | }; | |
176 | ||
177 | #define r8a7790_register_i2c(idx) \ | |
178 | platform_device_register_simple( \ | |
db455c78 | 179 | "i2c-rcar_gen2", idx, \ |
b448c904 KM |
180 | i2c_resources + (2 * idx), 2); \ |
181 | ||
69e351d0 MD |
182 | void __init r8a7790_pinmux_init(void) |
183 | { | |
8d0b3bf7 | 184 | r8a7790_register_pfc(); |
43ca9cbb LP |
185 | r8a7790_register_gpio(0); |
186 | r8a7790_register_gpio(1); | |
187 | r8a7790_register_gpio(2); | |
188 | r8a7790_register_gpio(3); | |
189 | r8a7790_register_gpio(4); | |
190 | r8a7790_register_gpio(5); | |
69e351d0 MD |
191 | } |
192 | ||
6319ea50 | 193 | #define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \ |
302d8898 LP |
194 | static struct plat_sci_port scif##index##_platform_data = { \ |
195 | .type = scif_type, \ | |
302d8898 | 196 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
302d8898 | 197 | .scscr = _scscr, \ |
c0a384f5 LP |
198 | }; \ |
199 | \ | |
200 | static struct resource scif##index##_resources[] = { \ | |
201 | DEFINE_RES_MEM(baseaddr, 0x100), \ | |
202 | DEFINE_RES_IRQ(irq), \ | |
d44f8308 UH |
203 | } |
204 | ||
302d8898 LP |
205 | #define R8A7790_SCIF(index, baseaddr, irq) \ |
206 | __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \ | |
6319ea50 | 207 | index, baseaddr, irq) |
302d8898 LP |
208 | |
209 | #define R8A7790_SCIFA(index, baseaddr, irq) \ | |
210 | __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ | |
6319ea50 | 211 | index, baseaddr, irq) |
302d8898 LP |
212 | |
213 | #define R8A7790_SCIFB(index, baseaddr, irq) \ | |
214 | __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \ | |
6319ea50 | 215 | index, baseaddr, irq) |
302d8898 LP |
216 | |
217 | #define R8A7790_HSCIF(index, baseaddr, irq) \ | |
218 | __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \ | |
6319ea50 | 219 | index, baseaddr, irq) |
302d8898 LP |
220 | |
221 | R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ | |
222 | R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ | |
223 | R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ | |
224 | R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ | |
225 | R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ | |
226 | R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */ | |
227 | R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */ | |
228 | R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */ | |
229 | R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */ | |
230 | R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */ | |
231 | ||
232 | #define r8a7790_register_scif(index) \ | |
d2168146 | 233 | platform_device_register_resndata(NULL, "sh-sci", index, \ |
c0a384f5 LP |
234 | scif##index##_resources, \ |
235 | ARRAY_SIZE(scif##index##_resources), \ | |
236 | &scif##index##_platform_data, \ | |
237 | sizeof(scif##index##_platform_data)) | |
55d9fab2 | 238 | |
cde214a8 | 239 | static const struct renesas_irqc_config irqc0_data __initconst = { |
8f5ec0a5 MD |
240 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ |
241 | }; | |
242 | ||
cde214a8 | 243 | static const struct resource irqc0_resources[] __initconst = { |
8f5ec0a5 MD |
244 | DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ |
245 | DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ | |
246 | DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ | |
247 | DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ | |
248 | DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ | |
249 | }; | |
250 | ||
251 | #define r8a7790_register_irqc(idx) \ | |
d2168146 | 252 | platform_device_register_resndata(NULL, "renesas_irqc", \ |
8f5ec0a5 MD |
253 | idx, irqc##idx##_resources, \ |
254 | ARRAY_SIZE(irqc##idx##_resources), \ | |
255 | &irqc##idx##_data, \ | |
256 | sizeof(struct renesas_irqc_config)) | |
257 | ||
cde214a8 | 258 | static const struct resource thermal_resources[] __initconst = { |
0b8eeba4 SH |
259 | DEFINE_RES_MEM(0xe61f0000, 0x14), |
260 | DEFINE_RES_MEM(0xe61f0100, 0x38), | |
261 | DEFINE_RES_IRQ(gic_spi(69)), | |
262 | }; | |
263 | ||
264 | #define r8a7790_register_thermal() \ | |
265 | platform_device_register_simple("rcar_thermal", -1, \ | |
266 | thermal_resources, \ | |
267 | ARRAY_SIZE(thermal_resources)) | |
268 | ||
711ee6c8 LP |
269 | static struct sh_timer_config cmt0_platform_data = { |
270 | .channels_mask = 0x60, | |
99ade1a0 MD |
271 | }; |
272 | ||
711ee6c8 LP |
273 | static struct resource cmt0_resources[] = { |
274 | DEFINE_RES_MEM(0xffca0000, 0x1004), | |
275 | DEFINE_RES_IRQ(gic_spi(142)), | |
99ade1a0 MD |
276 | }; |
277 | ||
278 | #define r8a7790_register_cmt(idx) \ | |
d2168146 | 279 | platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \ |
99ade1a0 MD |
280 | idx, cmt##idx##_resources, \ |
281 | ARRAY_SIZE(cmt##idx##_resources), \ | |
282 | &cmt##idx##_platform_data, \ | |
283 | sizeof(struct sh_timer_config)) | |
284 | ||
4e9c4877 | 285 | void __init r8a7790_add_standard_devices(void) |
0468b2d6 | 286 | { |
302d8898 LP |
287 | r8a7790_register_scif(0); |
288 | r8a7790_register_scif(1); | |
289 | r8a7790_register_scif(2); | |
290 | r8a7790_register_scif(3); | |
291 | r8a7790_register_scif(4); | |
292 | r8a7790_register_scif(5); | |
293 | r8a7790_register_scif(6); | |
294 | r8a7790_register_scif(7); | |
295 | r8a7790_register_scif(8); | |
296 | r8a7790_register_scif(9); | |
247fd5ec | 297 | r8a7790_register_cmt(0); |
8f5ec0a5 | 298 | r8a7790_register_irqc(0); |
0b8eeba4 | 299 | r8a7790_register_thermal(); |
f05b4b52 MD |
300 | r8a7790_register_i2c(0); |
301 | r8a7790_register_i2c(1); | |
302 | r8a7790_register_i2c(2); | |
303 | r8a7790_register_i2c(3); | |
304 | r8a7790_register_audio_dmac(0); | |
305 | r8a7790_register_audio_dmac(1); | |
0468b2d6 MD |
306 | } |
307 | ||
308 | #ifdef CONFIG_USE_OF | |
0468b2d6 | 309 | |
cde214a8 | 310 | static const char * const r8a7790_boards_compat_dt[] __initconst = { |
0468b2d6 MD |
311 | "renesas,r8a7790", |
312 | NULL, | |
313 | }; | |
314 | ||
315 | DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") | |
ad09cb83 | 316 | .smp = smp_ops(r8a7790_smp_ops), |
ed06ecbc | 317 | .init_early = shmobile_init_delay, |
50c517d9 | 318 | .init_time = rcar_gen2_timer_init, |
7d95b9dd | 319 | .init_late = shmobile_init_late, |
f8e81935 | 320 | .reserve = rcar_gen2_reserve, |
0468b2d6 MD |
321 | .dt_compat = r8a7790_boards_compat_dt, |
322 | MACHINE_END | |
323 | #endif /* CONFIG_USE_OF */ |