[linux-2.6-block.git] / arch / arm / mach-shmobile / setup-r8a7778.c

/*
 * r8a7778 processor support
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
 * Copyright (C) 2013  Cogent Embedded, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_data/dma-rcar-hpbdma.h>
#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_data/irq-renesas-intc-irqpin.h>
#include <linux/platform_device.h>
#include <linux/irqchip.h>
#include <linux/serial_sci.h>
#include <linux/sh_timer.h>
#include <linux/pm_runtime.h>
#include <linux/usb/phy.h>
#include <linux/usb/hcd.h>
#include <linux/usb/ehci_pdriver.h>
#include <linux/usb/ohci_pdriver.h>
#include <linux/dma-mapping.h>

#include <asm/mach/arch.h>
#include <asm/hardware/cache-l2x0.h>

#include "common.h"
#include "irqs.h"
#include "r8a7778.h"

/* SCIF */
#define R8A7778_SCIF(index, baseaddr, irq)			\
static struct plat_sci_port scif##index##_platform_data = {	\
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,	\
	.scscr		= SCSCR_RE | SCSCR_TE | SCSCR_CKE1,	\
	.type		= PORT_SCIF,				\
};								\
								\
static struct resource scif##index##_resources[] = {		\
	DEFINE_RES_MEM(baseaddr, 0x100),			\
	DEFINE_RES_IRQ(irq),					\
}

R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));

#define r8a7778_register_scif(index)					       \
	platform_device_register_resndata(NULL, "sh-sci", index,	       \
					  scif##index##_resources,	       \
					  ARRAY_SIZE(scif##index##_resources), \
					  &scif##index##_platform_data,	       \
					  sizeof(scif##index##_platform_data))

/* TMU */
static struct sh_timer_config sh_tmu0_platform_data = {
	.channels_mask = 7,
};

static struct resource sh_tmu0_resources[] = {
	DEFINE_RES_MEM(0xffd80000, 0x30),
	DEFINE_RES_IRQ(gic_iid(0x40)),
	DEFINE_RES_IRQ(gic_iid(0x41)),
	DEFINE_RES_IRQ(gic_iid(0x42)),
};

#define r8a7778_register_tmu(idx)			\
	platform_device_register_resndata(		\
		NULL, "sh-tmu", idx,			\
		sh_tmu##idx##_resources,		\
		ARRAY_SIZE(sh_tmu##idx##_resources),	\
		&sh_tmu##idx##_platform_data,		\
		sizeof(sh_tmu##idx##_platform_data))

int r8a7778_usb_phy_power(bool enable)
{
	static struct usb_phy *phy = NULL;
	int ret = 0;

	if (!phy)
		phy = usb_get_phy(USB_PHY_TYPE_USB2);

	if (IS_ERR(phy)) {
		pr_err("kernel doesn't have usb phy driver\n");
		return PTR_ERR(phy);
	}

	if (enable)
		ret = usb_phy_init(phy);
	else
		usb_phy_shutdown(phy);

	return ret;
}

/* USB */
static int usb_power_on(struct platform_device *pdev)
{
	int ret = r8a7778_usb_phy_power(true);

	if (ret)
		return ret;

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	return 0;
}

static void usb_power_off(struct platform_device *pdev)
{
	if (r8a7778_usb_phy_power(false))
		return;

	pm_runtime_put_sync(&pdev->dev);
	pm_runtime_disable(&pdev->dev);
}

static int ehci_init_internal_buffer(struct usb_hcd *hcd)
{
	/*
	 * Below are recommended values from the datasheet;
	 * see [USB :: Setting of EHCI Internal Buffer].
	 */
	/* EHCI IP internal buffer setting */
	iowrite32(0x00ff0040, hcd->regs + 0x0094);
	/* EHCI IP internal buffer enable */
	iowrite32(0x00000001, hcd->regs + 0x009C);

	return 0;
}

static struct usb_ehci_pdata ehci_pdata __initdata = {
	.power_on	= usb_power_on,
	.power_off	= usb_power_off,
	.power_suspend	= usb_power_off,
	.pre_setup	= ehci_init_internal_buffer,
};

static struct resource ehci_resources[] __initdata = {
	DEFINE_RES_MEM(0xffe70000, 0x400),
	DEFINE_RES_IRQ(gic_iid(0x4c)),
};

static struct usb_ohci_pdata ohci_pdata __initdata = {
	.power_on	= usb_power_on,
	.power_off	= usb_power_off,
	.power_suspend	= usb_power_off,
};

static struct resource ohci_resources[] __initdata = {
	DEFINE_RES_MEM(0xffe70400, 0x400),
	DEFINE_RES_IRQ(gic_iid(0x4c)),
};

#define USB_PLATFORM_INFO(hci)					\
static struct platform_device_info hci##_info __initdata = {	\
	.name		= #hci "-platform",			\
	.id		= -1,					\
	.res		= hci##_resources,			\
	.num_res	= ARRAY_SIZE(hci##_resources),		\
	.data		= &hci##_pdata,				\
	.size_data	= sizeof(hci##_pdata),			\
	.dma_mask	= DMA_BIT_MASK(32),			\
}

USB_PLATFORM_INFO(ehci);
USB_PLATFORM_INFO(ohci);

/* PFC/GPIO */
static struct resource pfc_resources[] __initdata = {
	DEFINE_RES_MEM(0xfffc0000, 0x118),
};

#define R8A7778_GPIO(idx)						\
static struct resource r8a7778_gpio##idx##_resources[] __initdata = {	\
	DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),		\
	DEFINE_RES_IRQ(gic_iid(0x87)),					\
};									\
									\
static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
	.gpio_base	= 32 * (idx),					\
	.irq_base	= GPIO_IRQ_BASE(idx),				\
	.number_of_pins	= 32,						\
	.pctl_name	= "pfc-r8a7778",				\
}

R8A7778_GPIO(0);
R8A7778_GPIO(1);
R8A7778_GPIO(2);
R8A7778_GPIO(3);
R8A7778_GPIO(4);

#define r8a7778_register_gpio(idx)				\
	platform_device_register_resndata(			\
		NULL, "gpio_rcar", idx,				\
		r8a7778_gpio##idx##_resources,			\
		ARRAY_SIZE(r8a7778_gpio##idx##_resources),	\
		&r8a7778_gpio##idx##_platform_data,		\
		sizeof(r8a7778_gpio##idx##_platform_data))

void __init r8a7778_pinmux_init(void)
{
	platform_device_register_simple(
		"pfc-r8a7778", -1,
		pfc_resources,
		ARRAY_SIZE(pfc_resources));

	r8a7778_register_gpio(0);
	r8a7778_register_gpio(1);
	r8a7778_register_gpio(2);
	r8a7778_register_gpio(3);
	r8a7778_register_gpio(4);
};

/* I2C */
static struct resource i2c_resources[] __initdata = {
	/* I2C0 */
	DEFINE_RES_MEM(0xffc70000, 0x1000),
	DEFINE_RES_IRQ(gic_iid(0x63)),
	/* I2C1 */
	DEFINE_RES_MEM(0xffc71000, 0x1000),
	DEFINE_RES_IRQ(gic_iid(0x6e)),
	/* I2C2 */
	DEFINE_RES_MEM(0xffc72000, 0x1000),
	DEFINE_RES_IRQ(gic_iid(0x6c)),
	/* I2C3 */
	DEFINE_RES_MEM(0xffc73000, 0x1000),
	DEFINE_RES_IRQ(gic_iid(0x6d)),
};

static void __init r8a7778_register_i2c(int id)
{
	BUG_ON(id < 0 || id > 3);

	platform_device_register_simple(
		"i2c-rcar", id,
		i2c_resources + (2 * id), 2);
}

/* HSPI */
static struct resource hspi_resources[] __initdata = {
	/* HSPI0 */
	DEFINE_RES_MEM(0xfffc7000, 0x18),
	DEFINE_RES_IRQ(gic_iid(0x5f)),
	/* HSPI1 */
	DEFINE_RES_MEM(0xfffc8000, 0x18),
	DEFINE_RES_IRQ(gic_iid(0x74)),
	/* HSPI2 */
	DEFINE_RES_MEM(0xfffc6000, 0x18),
	DEFINE_RES_IRQ(gic_iid(0x75)),
};

static void __init r8a7778_register_hspi(int id)
{
	BUG_ON(id < 0 || id > 2);

	platform_device_register_simple(
		"sh-hspi", id,
		hspi_resources + (2 * id), 2);
}

void __init r8a7778_add_dt_devices(void)
{
#ifdef CONFIG_CACHE_L2X0
	void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
	if (base) {
		/*
		 * Shared attribute override enable, 64K*16way
		 * don't call iounmap(base)
		 */
		l2x0_init(base, 0x00400000, 0xc20f0fff);
	}
#endif
}

/* HPB-DMA */

/* Asynchronous mode register (ASYNCMDR) bits */
#define HPB_DMAE_ASYNCMDR_ASMD22_MASK	BIT(2)	/* SDHI0 */
#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE	BIT(2)	/* SDHI0 */
#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI	0	/* SDHI0 */
#define HPB_DMAE_ASYNCMDR_ASMD21_MASK	BIT(1)	/* SDHI0 */
#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE	BIT(1)	/* SDHI0 */
#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI	0	/* SDHI0 */

#define HPBDMA_SSI(_id)				\
{						\
	.id	= HPBDMA_SLAVE_SSI## _id ##_TX,	\
	.addr	= 0xffd91008 + (_id * 0x40),	\
	.dcr	= HPB_DMAE_DCR_CT |		\
		  HPB_DMAE_DCR_DIP |		\
		  HPB_DMAE_DCR_SPDS_32BIT |	\
		  HPB_DMAE_DCR_DMDL |		\
		  HPB_DMAE_DCR_DPDS_32BIT,	\
	.port   = _id + (_id << 8),		\
	.dma_ch = (28 + _id),			\
}, {						\
	.id	= HPBDMA_SLAVE_SSI## _id ##_RX,	\
	.addr	= 0xffd9100c + (_id * 0x40),	\
	.dcr	= HPB_DMAE_DCR_CT |		\
		  HPB_DMAE_DCR_DIP |		\
		  HPB_DMAE_DCR_SMDL |		\
		  HPB_DMAE_DCR_SPDS_32BIT |	\
		  HPB_DMAE_DCR_DPDS_32BIT,	\
	.port   = _id + (_id << 8),		\
	.dma_ch = (28 + _id),			\
}

#define HPBDMA_HPBIF(_id)				\
{							\
	.id	= HPBDMA_SLAVE_HPBIF## _id ##_TX,	\
	.addr	= 0xffda0000 + (_id * 0x1000),		\
	.dcr	= HPB_DMAE_DCR_CT |			\
		  HPB_DMAE_DCR_DIP |			\
		  HPB_DMAE_DCR_SPDS_32BIT |		\
		  HPB_DMAE_DCR_DMDL |			\
		  HPB_DMAE_DCR_DPDS_32BIT,		\
	.port   = 0x1111,				\
	.dma_ch = (28 + _id),				\
}, {							\
	.id	= HPBDMA_SLAVE_HPBIF## _id ##_RX,	\
	.addr	= 0xffda0000 + (_id * 0x1000),		\
	.dcr	= HPB_DMAE_DCR_CT |			\
		  HPB_DMAE_DCR_DIP |			\
		  HPB_DMAE_DCR_SMDL |			\
		  HPB_DMAE_DCR_SPDS_32BIT |		\
		  HPB_DMAE_DCR_DPDS_32BIT,		\
	.port   = 0x1111,				\
	.dma_ch = (28 + _id),				\
}

static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
	{
		.id	= HPBDMA_SLAVE_SDHI0_TX,
		.addr	= 0xffe4c000 + 0x30,
		.dcr	= HPB_DMAE_DCR_SPDS_16BIT |
			  HPB_DMAE_DCR_DMDL |
			  HPB_DMAE_DCR_DPDS_16BIT,
		.rstr	= HPB_DMAE_ASYNCRSTR_ASRST21 |
			  HPB_DMAE_ASYNCRSTR_ASRST22 |
			  HPB_DMAE_ASYNCRSTR_ASRST23,
		.mdr	= HPB_DMAE_ASYNCMDR_ASMD21_MULTI,
		.mdm	= HPB_DMAE_ASYNCMDR_ASMD21_MASK,
		.port	= 0x0D0C,
		.flags	= HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
		.dma_ch	= 21,
	}, {
		.id	= HPBDMA_SLAVE_SDHI0_RX,
		.addr	= 0xffe4c000 + 0x30,
		.dcr	= HPB_DMAE_DCR_SMDL |
			  HPB_DMAE_DCR_SPDS_16BIT |
			  HPB_DMAE_DCR_DPDS_16BIT,
		.rstr	= HPB_DMAE_ASYNCRSTR_ASRST21 |
			  HPB_DMAE_ASYNCRSTR_ASRST22 |
			  HPB_DMAE_ASYNCRSTR_ASRST23,
		.mdr	= HPB_DMAE_ASYNCMDR_ASMD22_MULTI,
		.mdm	= HPB_DMAE_ASYNCMDR_ASMD22_MASK,
		.port	= 0x0D0C,
		.flags	= HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE,
		.dma_ch	= 22,
	}, {
		.id	= HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */
		.addr	= 0xffe60018,
		.dcr	= HPB_DMAE_DCR_SPDS_32BIT |
			  HPB_DMAE_DCR_DMDL |
			  HPB_DMAE_DCR_DPDS_32BIT,
		.port	= 0x0000,
		.dma_ch	= 14,
	}, {
		.id	= HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */
		.addr	= 0xffe6001c,
		.dcr	= HPB_DMAE_DCR_SMDL |
			  HPB_DMAE_DCR_SPDS_32BIT |
			  HPB_DMAE_DCR_DPDS_32BIT,
		.port	= 0x0101,
		.dma_ch	= 15,
	},

	HPBDMA_SSI(0),
	HPBDMA_SSI(1),
	HPBDMA_SSI(2),
	HPBDMA_SSI(3),
	HPBDMA_SSI(4),
	HPBDMA_SSI(5),
	HPBDMA_SSI(6),
	HPBDMA_SSI(7),
	HPBDMA_SSI(8),

	HPBDMA_HPBIF(0),
	HPBDMA_HPBIF(1),
	HPBDMA_HPBIF(2),
	HPBDMA_HPBIF(3),
	HPBDMA_HPBIF(4),
	HPBDMA_HPBIF(5),
	HPBDMA_HPBIF(6),
	HPBDMA_HPBIF(7),
	HPBDMA_HPBIF(8),
};

static const struct hpb_dmae_channel hpb_dmae_channels[] = {
	HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */
	HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */
	HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
	HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX),   /* ch. 28 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX),   /* ch. 28 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX),   /* ch. 29 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX),   /* ch. 29 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX),   /* ch. 30 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX),   /* ch. 30 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX),   /* ch. 31 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX),   /* ch. 31 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX),   /* ch. 32 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX),   /* ch. 32 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX),   /* ch. 33 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX),   /* ch. 33 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX),   /* ch. 34 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX),   /* ch. 34 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX),   /* ch. 35 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX),   /* ch. 35 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX),   /* ch. 36 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX),   /* ch. 36 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
};

static struct hpb_dmae_pdata dma_platform_data __initdata = {
	.slaves			= hpb_dmae_slaves,
	.num_slaves		= ARRAY_SIZE(hpb_dmae_slaves),
	.channels		= hpb_dmae_channels,
	.num_channels		= ARRAY_SIZE(hpb_dmae_channels),
	.ts_shift		= {
		[XMIT_SZ_8BIT]	= 0,
		[XMIT_SZ_16BIT]	= 1,
		[XMIT_SZ_32BIT]	= 2,
	},
	.num_hw_channels	= 39,
};

static struct resource hpb_dmae_resources[] __initdata = {
	/* Channel registers */
	DEFINE_RES_MEM(0xffc08000, 0x1000),
	/* Common registers */
	DEFINE_RES_MEM(0xffc09000, 0x170),
	/* Asynchronous reset registers */
	DEFINE_RES_MEM(0xffc00300, 4),
	/* Asynchronous mode registers */
	DEFINE_RES_MEM(0xffc00400, 4),
	/* IRQ for DMA channels */
	DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ),
};

static void __init r8a7778_register_hpb_dmae(void)
{
	platform_device_register_resndata(NULL, "hpb-dma-engine",
					  -1, hpb_dmae_resources,
					  ARRAY_SIZE(hpb_dmae_resources),
					  &dma_platform_data,
					  sizeof(dma_platform_data));
}

void __init r8a7778_add_standard_devices(void)
{
	r8a7778_add_dt_devices();
	r8a7778_register_tmu(0);
	r8a7778_register_scif(0);
	r8a7778_register_scif(1);
	r8a7778_register_scif(2);
	r8a7778_register_scif(3);
	r8a7778_register_scif(4);
	r8a7778_register_scif(5);
	r8a7778_register_i2c(0);
	r8a7778_register_i2c(1);
	r8a7778_register_i2c(2);
	r8a7778_register_i2c(3);
	r8a7778_register_hspi(0);
	r8a7778_register_hspi(1);
	r8a7778_register_hspi(2);

	r8a7778_register_hpb_dmae();
}

void __init r8a7778_init_late(void)
{
	shmobile_init_late();
	platform_device_register_full(&ehci_info);
	platform_device_register_full(&ohci_info);
}

static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
	.sense_bitfield_width = 2,
};

static struct resource irqpin_resources[] __initdata = {
	DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
	DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
	DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
	DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
	DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
	DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
	DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
	DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
	DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
};

void __init r8a7778_init_irq_extpin_dt(int irlm)
{
	void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
	unsigned long tmp;

	if (!icr0) {
		pr_warn("r8a7778: unable to setup external irq pin mode\n");
		return;
	}

	tmp = ioread32(icr0);
	if (irlm)
		tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
	else
		tmp &= ~(1 << 23); /* IRL mode - not supported */
	tmp |= (1 << 21); /* LVLMODE = 1 */
	iowrite32(tmp, icr0);
	iounmap(icr0);
}

void __init r8a7778_init_irq_extpin(int irlm)
{
	r8a7778_init_irq_extpin_dt(irlm);
	if (irlm)
		platform_device_register_resndata(
			NULL, "renesas_intc_irqpin", -1,
			irqpin_resources, ARRAY_SIZE(irqpin_resources),
			&irqpin_platform_data, sizeof(irqpin_platform_data));
}

void __init r8a7778_init_delay(void)
{
	shmobile_init_delay();
}

#ifdef CONFIG_USE_OF
#define INT2SMSKCR0	0x82288 /* 0xfe782288 */
#define INT2SMSKCR1	0x8228c /* 0xfe78228c */

#define INT2NTSR0	0x00018 /* 0xfe700018 */
#define INT2NTSR1	0x0002c /* 0xfe70002c */
void __init r8a7778_init_irq_dt(void)
{
	void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);

	BUG_ON(!base);

	irqchip_init();

	/* route all interrupts to ARM */
	__raw_writel(0x73ffffff, base + INT2NTSR0);
	__raw_writel(0xffffffff, base + INT2NTSR1);

	/* unmask all known interrupts in INTCS2 */
	__raw_writel(0x08330773, base + INT2SMSKCR0);
	__raw_writel(0x00311110, base + INT2SMSKCR1);

	iounmap(base);
}

static const char *r8a7778_compat_dt[] __initdata = {
	"renesas,r8a7778",
	NULL,
};

DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
	.init_early	= r8a7778_init_delay,
	.init_irq	= r8a7778_init_irq_dt,
	.init_late	= shmobile_init_late,
	.dt_compat	= r8a7778_compat_dt,
MACHINE_END

#endif /* CONFIG_USE_OF */
Commit	Line	Data
ccb7cc74 KM	1	/*
	2	* r8a7778 processor support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
52421914	6	* Copyright (C) 2013 Cogent Embedded, Inc.
ccb7cc74 KM	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; version 2 of the License.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
ccb7cc74 KM	16	*/
	17
	18	#include <linux/kernel.h>
	19	#include <linux/io.h>
	20	#include <linux/irqchip/arm-gic.h>
	21	#include <linux/of.h>
	22	#include <linux/of_platform.h>
338c4991	23	#include <linux/platform_data/dma-rcar-hpbdma.h>
39ca2283	24	#include <linux/platform_data/gpio-rcar.h>
3a42fa20	25	#include <linux/platform_data/irq-renesas-intc-irqpin.h>
ccb7cc74 KM	26	#include <linux/platform_device.h>
ccb7cc74 KM	27	#include <linux/irqchip.h>
db331fc8	28	#include <linux/serial_sci.h>
ccb7cc74	29	#include <linux/sh_timer.h>
02474a41 SS	30	#include <linux/pm_runtime.h>
	31	#include <linux/usb/phy.h>
	32	#include <linux/usb/hcd.h>
	33	#include <linux/usb/ehci_pdriver.h>
	34	#include <linux/usb/ohci_pdriver.h>
	35	#include <linux/dma-mapping.h>
02c94f38	36
ccb7cc74 KM	37	#include <asm/mach/arch.h>
	38	#include <asm/hardware/cache-l2x0.h>
	39
fd44aa5e	40	#include "common.h"
b6bab126	41	#include "irqs.h"
02c94f38	42	#include "r8a7778.h"
ccb7cc74	43
db331fc8	44	/* SCIF */
ecbcd715 LP	45	#define R8A7778_SCIF(index, baseaddr, irq) \
ecbcd715 LP	46	static struct plat_sci_port scif##index##_platform_data = { \
db331fc8 KM	47	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP, \
db331fc8 KM	48	.scscr = SCSCR_RE \| SCSCR_TE \| SCSCR_CKE1, \
db331fc8	49	.type = PORT_SCIF, \
23399a6f LP	50	}; \
	51	\
	52	static struct resource scif##index##_resources[] = { \
	53	DEFINE_RES_MEM(baseaddr, 0x100), \
	54	DEFINE_RES_IRQ(irq), \
db331fc8 KM	55	}
db331fc8 KM	56
ecbcd715 LP	57	R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66));
	58	R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67));
	59	R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68));
	60	R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69));
	61	R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a));
	62	R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
	63
	64	#define r8a7778_register_scif(index) \
d2168146	65	platform_device_register_resndata(NULL, "sh-sci", index, \
23399a6f LP	66	scif##index##_resources, \
	67	ARRAY_SIZE(scif##index##_resources), \
	68	&scif##index##_platform_data, \
	69	sizeof(scif##index##_platform_data))
db331fc8	70
ccb7cc74	71	/* TMU */
535ef0d9 LP	72	static struct sh_timer_config sh_tmu0_platform_data = {
535ef0d9 LP	73	.channels_mask = 7,
ccb7cc74 KM	74	};
ccb7cc74 KM	75
535ef0d9 LP	76	static struct resource sh_tmu0_resources[] = {
	77	DEFINE_RES_MEM(0xffd80000, 0x30),
	78	DEFINE_RES_IRQ(gic_iid(0x40)),
ccb7cc74	79	DEFINE_RES_IRQ(gic_iid(0x41)),
535ef0d9	80	DEFINE_RES_IRQ(gic_iid(0x42)),
ccb7cc74 KM	81	};
ccb7cc74 KM	82
81484487 KM	83	#define r8a7778_register_tmu(idx) \
81484487 KM	84	platform_device_register_resndata( \
d2168146	85	NULL, "sh-tmu", idx, \
81484487 KM	86	sh_tmu##idx##_resources, \
	87	ARRAY_SIZE(sh_tmu##idx##_resources), \
	88	&sh_tmu##idx##_platform_data, \
	89	sizeof(sh_tmu##idx##_platform_data))
ccb7cc74	90
f39d35fc KM	91	int r8a7778_usb_phy_power(bool enable)
	92	{
	93	static struct usb_phy *phy = NULL;
	94	int ret = 0;
	95
	96	if (!phy)
	97	phy = usb_get_phy(USB_PHY_TYPE_USB2);
	98
	99	if (IS_ERR(phy)) {
	100	pr_err("kernel doesn't have usb phy driver\n");
	101	return PTR_ERR(phy);
	102	}
02474a41	103
f39d35fc KM	104	if (enable)
	105	ret = usb_phy_init(phy);
	106	else
	107	usb_phy_shutdown(phy);
02474a41	108
f39d35fc KM	109	return ret;
	110	}
	111
	112	/* USB */
02474a41 SS	113	static int usb_power_on(struct platform_device *pdev)
02474a41 SS	114	{
f39d35fc KM	115	int ret = r8a7778_usb_phy_power(true);
	116
	117	if (ret)
	118	return ret;
02474a41 SS	119
	120	pm_runtime_enable(&pdev->dev);
	121	pm_runtime_get_sync(&pdev->dev);
	122
02474a41 SS	123	return 0;
	124	}
	125
	126	static void usb_power_off(struct platform_device *pdev)
	127	{
f39d35fc	128	if (r8a7778_usb_phy_power(false))
02474a41 SS	129	return;
02474a41 SS	130
02474a41 SS	131	pm_runtime_put_sync(&pdev->dev);
	132	pm_runtime_disable(&pdev->dev);
	133	}
	134
	135	static int ehci_init_internal_buffer(struct usb_hcd *hcd)
	136	{
	137	/*
	138	* Below are recommended values from the datasheet;
	139	* see [USB :: Setting of EHCI Internal Buffer].
	140	*/
	141	/* EHCI IP internal buffer setting */
	142	iowrite32(0x00ff0040, hcd->regs + 0x0094);
	143	/* EHCI IP internal buffer enable */
	144	iowrite32(0x00000001, hcd->regs + 0x009C);
	145
	146	return 0;
	147	}
	148
	149	static struct usb_ehci_pdata ehci_pdata __initdata = {
	150	.power_on = usb_power_on,
	151	.power_off = usb_power_off,
	152	.power_suspend = usb_power_off,
	153	.pre_setup = ehci_init_internal_buffer,
	154	};
	155
	156	static struct resource ehci_resources[] __initdata = {
	157	DEFINE_RES_MEM(0xffe70000, 0x400),
	158	DEFINE_RES_IRQ(gic_iid(0x4c)),
	159	};
	160
	161	static struct usb_ohci_pdata ohci_pdata __initdata = {
	162	.power_on = usb_power_on,
	163	.power_off = usb_power_off,
	164	.power_suspend = usb_power_off,
	165	};
	166
	167	static struct resource ohci_resources[] __initdata = {
	168	DEFINE_RES_MEM(0xffe70400, 0x400),
	169	DEFINE_RES_IRQ(gic_iid(0x4c)),
	170	};
	171
	172	#define USB_PLATFORM_INFO(hci) \
	173	static struct platform_device_info hci##_info __initdata = { \
02474a41 SS	174	.name = #hci "-platform", \
	175	.id = -1, \
	176	.res = hci##_resources, \
	177	.num_res = ARRAY_SIZE(hci##_resources), \
	178	.data = &hci##_pdata, \
	179	.size_data = sizeof(hci##_pdata), \
	180	.dma_mask = DMA_BIT_MASK(32), \
	181	}
	182
	183	USB_PLATFORM_INFO(ehci);
	184	USB_PLATFORM_INFO(ohci);
	185
39ca2283	186	/* PFC/GPIO */
c9031fbb	187	static struct resource pfc_resources[] __initdata = {
369b00bb KM	188	DEFINE_RES_MEM(0xfffc0000, 0x118),
	189	};
	190
39ca2283	191	#define R8A7778_GPIO(idx) \
c9031fbb	192	static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \
39ca2283 KM	193	DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \
	194	DEFINE_RES_IRQ(gic_iid(0x87)), \
	195	}; \
	196	\
c9031fbb	197	static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
39ca2283 KM	198	.gpio_base = 32 * (idx), \
	199	.irq_base = GPIO_IRQ_BASE(idx), \
	200	.number_of_pins = 32, \
	201	.pctl_name = "pfc-r8a7778", \
	202	}
	203
	204	R8A7778_GPIO(0);
	205	R8A7778_GPIO(1);
	206	R8A7778_GPIO(2);
	207	R8A7778_GPIO(3);
	208	R8A7778_GPIO(4);
	209
	210	#define r8a7778_register_gpio(idx) \
	211	platform_device_register_resndata( \
d2168146	212	NULL, "gpio_rcar", idx, \
39ca2283 KM	213	r8a7778_gpio##idx##_resources, \
	214	ARRAY_SIZE(r8a7778_gpio##idx##_resources), \
	215	&r8a7778_gpio##idx##_platform_data, \
	216	sizeof(r8a7778_gpio##idx##_platform_data))
	217
369b00bb KM	218	void __init r8a7778_pinmux_init(void)
	219	{
	220	platform_device_register_simple(
	221	"pfc-r8a7778", -1,
	222	pfc_resources,
	223	ARRAY_SIZE(pfc_resources));
39ca2283 KM	224
	225	r8a7778_register_gpio(0);
	226	r8a7778_register_gpio(1);
	227	r8a7778_register_gpio(2);
	228	r8a7778_register_gpio(3);
	229	r8a7778_register_gpio(4);
ae8b378f SH	230	};
ae8b378f SH	231
46b9a092 KM	232	/* I2C */
	233	static struct resource i2c_resources[] __initdata = {
	234	/* I2C0 */
	235	DEFINE_RES_MEM(0xffc70000, 0x1000),
	236	DEFINE_RES_IRQ(gic_iid(0x63)),
	237	/* I2C1 */
	238	DEFINE_RES_MEM(0xffc71000, 0x1000),
	239	DEFINE_RES_IRQ(gic_iid(0x6e)),
	240	/* I2C2 */
	241	DEFINE_RES_MEM(0xffc72000, 0x1000),
	242	DEFINE_RES_IRQ(gic_iid(0x6c)),
	243	/* I2C3 */
	244	DEFINE_RES_MEM(0xffc73000, 0x1000),
	245	DEFINE_RES_IRQ(gic_iid(0x6d)),
	246	};
	247
1fd4eecd	248	static void __init r8a7778_register_i2c(int id)
46b9a092 KM	249	{
	250	BUG_ON(id < 0 \|\| id > 3);
	251
	252	platform_device_register_simple(
	253	"i2c-rcar", id,
	254	i2c_resources + (2 * id), 2);
	255	}
	256
8b89797f KM	257	/* HSPI */
	258	static struct resource hspi_resources[] __initdata = {
	259	/* HSPI0 */
	260	DEFINE_RES_MEM(0xfffc7000, 0x18),
	261	DEFINE_RES_IRQ(gic_iid(0x5f)),
	262	/* HSPI1 */
	263	DEFINE_RES_MEM(0xfffc8000, 0x18),
	264	DEFINE_RES_IRQ(gic_iid(0x74)),
	265	/* HSPI2 */
	266	DEFINE_RES_MEM(0xfffc6000, 0x18),
	267	DEFINE_RES_IRQ(gic_iid(0x75)),
	268	};
	269
117378e5	270	static void __init r8a7778_register_hspi(int id)
8b89797f KM	271	{
	272	BUG_ON(id < 0 \|\| id > 2);
	273
	274	platform_device_register_simple(
	275	"sh-hspi", id,
	276	hspi_resources + (2 * id), 2);
	277	}
	278
cfa66a81	279	void __init r8a7778_add_dt_devices(void)
ccb7cc74	280	{
ccb7cc74 KM	281	#ifdef CONFIG_CACHE_L2X0
	282	void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
	283	if (base) {
	284	/*
36bccb11	285	* Shared attribute override enable, 64K*16way
ccb7cc74 KM	286	* don't call iounmap(base)
ccb7cc74 KM	287	*/
2edb89cd	288	l2x0_init(base, 0x00400000, 0xc20f0fff);
ccb7cc74 KM	289	}
ccb7cc74 KM	290	#endif
ccb7cc74 KM	291	}
ccb7cc74 KM	292
338c4991 MF	293	/* HPB-DMA */
	294
	295	/* Asynchronous mode register (ASYNCMDR) bits */
	296	#define HPB_DMAE_ASYNCMDR_ASMD22_MASK BIT(2) /* SDHI0 */
	297	#define HPB_DMAE_ASYNCMDR_ASMD22_SINGLE BIT(2) /* SDHI0 */
	298	#define HPB_DMAE_ASYNCMDR_ASMD22_MULTI 0 /* SDHI0 */
	299	#define HPB_DMAE_ASYNCMDR_ASMD21_MASK BIT(1) /* SDHI0 */
	300	#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */
	301	#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */
	302
a91be22c KM	303	#define HPBDMA_SSI(_id) \
	304	{ \
	305	.id = HPBDMA_SLAVE_SSI## _id ##_TX, \
	306	.addr = 0xffd91008 + (_id * 0x40), \
	307	.dcr = HPB_DMAE_DCR_CT \| \
	308	HPB_DMAE_DCR_DIP \| \
	309	HPB_DMAE_DCR_SPDS_32BIT \| \
	310	HPB_DMAE_DCR_DMDL \| \
	311	HPB_DMAE_DCR_DPDS_32BIT, \
	312	.port = _id + (_id << 8), \
	313	.dma_ch = (28 + _id), \
	314	}, { \
	315	.id = HPBDMA_SLAVE_SSI## _id ##_RX, \
	316	.addr = 0xffd9100c + (_id * 0x40), \
	317	.dcr = HPB_DMAE_DCR_CT \| \
	318	HPB_DMAE_DCR_DIP \| \
	319	HPB_DMAE_DCR_SMDL \| \
	320	HPB_DMAE_DCR_SPDS_32BIT \| \
	321	HPB_DMAE_DCR_DPDS_32BIT, \
	322	.port = _id + (_id << 8), \
	323	.dma_ch = (28 + _id), \
	324	}
	325
b4283184 KM	326	#define HPBDMA_HPBIF(_id) \
	327	{ \
	328	.id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \
	329	.addr = 0xffda0000 + (_id * 0x1000), \
	330	.dcr = HPB_DMAE_DCR_CT \| \
	331	HPB_DMAE_DCR_DIP \| \
	332	HPB_DMAE_DCR_SPDS_32BIT \| \
	333	HPB_DMAE_DCR_DMDL \| \
	334	HPB_DMAE_DCR_DPDS_32BIT, \
	335	.port = 0x1111, \
	336	.dma_ch = (28 + _id), \
	337	}, { \
	338	.id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \
	339	.addr = 0xffda0000 + (_id * 0x1000), \
	340	.dcr = HPB_DMAE_DCR_CT \| \
	341	HPB_DMAE_DCR_DIP \| \
	342	HPB_DMAE_DCR_SMDL \| \
	343	HPB_DMAE_DCR_SPDS_32BIT \| \
	344	HPB_DMAE_DCR_DPDS_32BIT, \
	345	.port = 0x1111, \
	346	.dma_ch = (28 + _id), \
	347	}
	348
338c4991 MF	349	static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
	350	{
	351	.id = HPBDMA_SLAVE_SDHI0_TX,
	352	.addr = 0xffe4c000 + 0x30,
	353	.dcr = HPB_DMAE_DCR_SPDS_16BIT \|
	354	HPB_DMAE_DCR_DMDL \|
	355	HPB_DMAE_DCR_DPDS_16BIT,
	356	.rstr = HPB_DMAE_ASYNCRSTR_ASRST21 \|
	357	HPB_DMAE_ASYNCRSTR_ASRST22 \|
	358	HPB_DMAE_ASYNCRSTR_ASRST23,
	359	.mdr = HPB_DMAE_ASYNCMDR_ASMD21_MULTI,
	360	.mdm = HPB_DMAE_ASYNCMDR_ASMD21_MASK,
	361	.port = 0x0D0C,
	362	.flags = HPB_DMAE_SET_ASYNC_RESET \| HPB_DMAE_SET_ASYNC_MODE,
	363	.dma_ch = 21,
	364	}, {
	365	.id = HPBDMA_SLAVE_SDHI0_RX,
	366	.addr = 0xffe4c000 + 0x30,
	367	.dcr = HPB_DMAE_DCR_SMDL \|
	368	HPB_DMAE_DCR_SPDS_16BIT \|
	369	HPB_DMAE_DCR_DPDS_16BIT,
	370	.rstr = HPB_DMAE_ASYNCRSTR_ASRST21 \|
	371	HPB_DMAE_ASYNCRSTR_ASRST22 \|
	372	HPB_DMAE_ASYNCRSTR_ASRST23,
	373	.mdr = HPB_DMAE_ASYNCMDR_ASMD22_MULTI,
	374	.mdm = HPB_DMAE_ASYNCMDR_ASMD22_MASK,
	375	.port = 0x0D0C,
	376	.flags = HPB_DMAE_SET_ASYNC_RESET \| HPB_DMAE_SET_ASYNC_MODE,
	377	.dma_ch = 22,
aa993864 KM	378	}, {
	379	.id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */
	380	.addr = 0xffe60018,
	381	.dcr = HPB_DMAE_DCR_SPDS_32BIT \|
	382	HPB_DMAE_DCR_DMDL \|
	383	HPB_DMAE_DCR_DPDS_32BIT,
	384	.port = 0x0000,
	385	.dma_ch = 14,
	386	}, {
	387	.id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */
	388	.addr = 0xffe6001c,
	389	.dcr = HPB_DMAE_DCR_SMDL \|
	390	HPB_DMAE_DCR_SPDS_32BIT \|
	391	HPB_DMAE_DCR_DPDS_32BIT,
	392	.port = 0x0101,
	393	.dma_ch = 15,
338c4991	394	},
b4283184	395
a91be22c KM	396	HPBDMA_SSI(0),
	397	HPBDMA_SSI(1),
	398	HPBDMA_SSI(2),
	399	HPBDMA_SSI(3),
	400	HPBDMA_SSI(4),
	401	HPBDMA_SSI(5),
	402	HPBDMA_SSI(6),
	403	HPBDMA_SSI(7),
	404	HPBDMA_SSI(8),
	405
b4283184 KM	406	HPBDMA_HPBIF(0),
	407	HPBDMA_HPBIF(1),
	408	HPBDMA_HPBIF(2),
	409	HPBDMA_HPBIF(3),
	410	HPBDMA_HPBIF(4),
	411	HPBDMA_HPBIF(5),
	412	HPBDMA_HPBIF(6),
	413	HPBDMA_HPBIF(7),
	414	HPBDMA_HPBIF(8),
338c4991 MF	415	};
	416
	417	static const struct hpb_dmae_channel hpb_dmae_channels[] = {
aa993864 KM	418	HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */
aa993864 KM	419	HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */
338c4991 MF	420	HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */
338c4991 MF	421	HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */
a91be22c KM	422	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */
a91be22c KM	423	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */
b4283184 KM	424	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */
b4283184 KM	425	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */
a91be22c KM	426	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */
a91be22c KM	427	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */
b4283184 KM	428	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */
b4283184 KM	429	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */
a91be22c KM	430	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */
a91be22c KM	431	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */
b4283184 KM	432	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */
b4283184 KM	433	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */
a91be22c KM	434	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */
a91be22c KM	435	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */
b4283184 KM	436	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */
b4283184 KM	437	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */
a91be22c KM	438	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */
a91be22c KM	439	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */
b4283184 KM	440	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */
b4283184 KM	441	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */
a91be22c KM	442	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */
a91be22c KM	443	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */
b4283184 KM	444	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */
b4283184 KM	445	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */
a91be22c KM	446	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */
a91be22c KM	447	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */
b4283184 KM	448	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */
b4283184 KM	449	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */
a91be22c KM	450	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */
a91be22c KM	451	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */
b4283184 KM	452	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */
b4283184 KM	453	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */
a91be22c KM	454	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */
a91be22c KM	455	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */
b4283184 KM	456	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */
b4283184 KM	457	HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */
338c4991 MF	458	};
	459
	460	static struct hpb_dmae_pdata dma_platform_data __initdata = {
	461	.slaves = hpb_dmae_slaves,
	462	.num_slaves = ARRAY_SIZE(hpb_dmae_slaves),
	463	.channels = hpb_dmae_channels,
	464	.num_channels = ARRAY_SIZE(hpb_dmae_channels),
	465	.ts_shift = {
	466	[XMIT_SZ_8BIT] = 0,
	467	[XMIT_SZ_16BIT] = 1,
	468	[XMIT_SZ_32BIT] = 2,
	469	},
	470	.num_hw_channels = 39,
	471	};
	472
	473	static struct resource hpb_dmae_resources[] __initdata = {
	474	/* Channel registers */
	475	DEFINE_RES_MEM(0xffc08000, 0x1000),
	476	/* Common registers */
	477	DEFINE_RES_MEM(0xffc09000, 0x170),
	478	/* Asynchronous reset registers */
	479	DEFINE_RES_MEM(0xffc00300, 4),
	480	/* Asynchronous mode registers */
	481	DEFINE_RES_MEM(0xffc00400, 4),
	482	/* IRQ for DMA channels */
	483	DEFINE_RES_NAMED(gic_iid(0x7b), 5, NULL, IORESOURCE_IRQ),
	484	};
	485
	486	static void __init r8a7778_register_hpb_dmae(void)
	487	{
d2168146 PM	488	platform_device_register_resndata(NULL, "hpb-dma-engine",
d2168146 PM	489	-1, hpb_dmae_resources,
338c4991 MF	490	ARRAY_SIZE(hpb_dmae_resources),
	491	&dma_platform_data,
	492	sizeof(dma_platform_data));
	493	}
	494
cfa66a81 KM	495	void __init r8a7778_add_standard_devices(void)
	496	{
	497	r8a7778_add_dt_devices();
18b27aeb	498	r8a7778_register_tmu(0);
5be97ca4 SH	499	r8a7778_register_scif(0);
	500	r8a7778_register_scif(1);
	501	r8a7778_register_scif(2);
	502	r8a7778_register_scif(3);
	503	r8a7778_register_scif(4);
	504	r8a7778_register_scif(5);
1fd4eecd KM	505	r8a7778_register_i2c(0);
	506	r8a7778_register_i2c(1);
	507	r8a7778_register_i2c(2);
	508	r8a7778_register_i2c(3);
3c7b5362 KM	509	r8a7778_register_hspi(0);
	510	r8a7778_register_hspi(1);
	511	r8a7778_register_hspi(2);
338c4991 MF	512
338c4991 MF	513	r8a7778_register_hpb_dmae();
cfa66a81 KM	514	}
cfa66a81 KM	515
02474a41 SS	516	void __init r8a7778_init_late(void)
02474a41 SS	517	{
54a06dde	518	shmobile_init_late();
02474a41 SS	519	platform_device_register_full(&ehci_info);
	520	platform_device_register_full(&ohci_info);
	521	}
	522
c9031fbb	523	static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
3a42fa20 KM	524	.irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
	525	.sense_bitfield_width = 2,
	526	};
	527
c9031fbb	528	static struct resource irqpin_resources[] __initdata = {
3a42fa20 KM	529	DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
	530	DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
	531	DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
	532	DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
	533	DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
	534	DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
	535	DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
	536	DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
	537	DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
	538	};
	539
2238577b	540	void __init r8a7778_init_irq_extpin_dt(int irlm)
3a42fa20 KM	541	{
	542	void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
	543	unsigned long tmp;
	544
	545	if (!icr0) {
	546	pr_warn("r8a7778: unable to setup external irq pin mode\n");
	547	return;
	548	}
	549
	550	tmp = ioread32(icr0);
	551	if (irlm)
	552	tmp \|= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
	553	else
	554	tmp &= ~(1 << 23); /* IRL mode - not supported */
	555	tmp \|= (1 << 21); /* LVLMODE = 1 */
	556	iowrite32(tmp, icr0);
	557	iounmap(icr0);
2238577b	558	}
3a42fa20	559
2238577b KM	560	void __init r8a7778_init_irq_extpin(int irlm)
	561	{
	562	r8a7778_init_irq_extpin_dt(irlm);
3a42fa20 KM	563	if (irlm)
3a42fa20 KM	564	platform_device_register_resndata(
d2168146	565	NULL, "renesas_intc_irqpin", -1,
3a42fa20 KM	566	irqpin_resources, ARRAY_SIZE(irqpin_resources),
	567	&irqpin_platform_data, sizeof(irqpin_platform_data));
	568	}
	569
54aa4c48 KM	570	void __init r8a7778_init_delay(void)
54aa4c48 KM	571	{
6fe950eb	572	shmobile_init_delay();
54aa4c48 KM	573	}
	574
	575	#ifdef CONFIG_USE_OF
ccb7cc74 KM	576	#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
	577	#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
	578
	579	#define INT2NTSR0 0x00018 /* 0xfe700018 */
	580	#define INT2NTSR1 0x0002c /* 0xfe70002c */
54aa4c48	581	void __init r8a7778_init_irq_dt(void)
ccb7cc74 KM	582	{
	583	void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
	584
	585	BUG_ON(!base);
	586
54aa4c48 KM	587	irqchip_init();
54aa4c48 KM	588
ccb7cc74 KM	589	/* route all interrupts to ARM */
	590	__raw_writel(0x73ffffff, base + INT2NTSR0);
	591	__raw_writel(0xffffffff, base + INT2NTSR1);
	592
	593	/* unmask all known interrupts in INTCS2 */
	594	__raw_writel(0x08330773, base + INT2SMSKCR0);
	595	__raw_writel(0x00311110, base + INT2SMSKCR1);
	596
	597	iounmap(base);
	598	}
	599
ccb7cc74 KM	600	static const char *r8a7778_compat_dt[] __initdata = {
	601	"renesas,r8a7778",
	602	NULL,
	603	};
	604
	605	DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
	606	.init_early = r8a7778_init_delay,
	607	.init_irq = r8a7778_init_irq_dt,
7759a7a8	608	.init_late = shmobile_init_late,
ccb7cc74 KM	609	.dt_compat = r8a7778_compat_dt,
	610	MACHINE_END
	611
	612	#endif /* CONFIG_USE_OF */