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eccf0607 MD |
1 | /* |
2 | * r8a73a4 processor support | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
5 | * Copyright (C) 2013 Magnus Damm | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | */ | |
20 | #include <linux/irq.h> | |
21 | #include <linux/irqchip.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/of_platform.h> | |
984ca295 | 24 | #include <linux/platform_data/irq-renesas-irqc.h> |
e481a528 | 25 | #include <linux/serial_sci.h> |
eccf0607 MD |
26 | #include <mach/common.h> |
27 | #include <mach/irqs.h> | |
28 | #include <mach/r8a73a4.h> | |
29 | #include <asm/mach/arch.h> | |
30 | ||
d313d068 MD |
31 | static const struct resource pfc_resources[] = { |
32 | DEFINE_RES_MEM(0xe6050000, 0x9000), | |
33 | }; | |
34 | ||
35 | void __init r8a73a4_pinmux_init(void) | |
36 | { | |
37 | platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources, | |
38 | ARRAY_SIZE(pfc_resources)); | |
39 | } | |
40 | ||
e481a528 MD |
41 | #define SCIF_COMMON(scif_type, baseaddr, irq) \ |
42 | .type = scif_type, \ | |
43 | .mapbase = baseaddr, \ | |
44 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | |
45 | .scbrr_algo_id = SCBRR_ALGO_4, \ | |
46 | .irqs = SCIx_IRQ_MUXED(irq) | |
47 | ||
48 | #define SCIFA_DATA(index, baseaddr, irq) \ | |
49 | [index] = { \ | |
50 | SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ | |
51 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ | |
52 | } | |
53 | ||
54 | #define SCIFB_DATA(index, baseaddr, irq) \ | |
55 | [index] = { \ | |
56 | SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ | |
57 | .scscr = SCSCR_RE | SCSCR_TE, \ | |
58 | } | |
59 | ||
60 | enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 }; | |
61 | ||
62 | static const struct plat_sci_port scif[] = { | |
63 | SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ | |
64 | SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ | |
65 | SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */ | |
66 | SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ | |
67 | SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ | |
68 | SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */ | |
69 | }; | |
70 | ||
71 | static inline void r8a73a4_register_scif(int idx) | |
72 | { | |
73 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | |
74 | sizeof(struct plat_sci_port)); | |
75 | } | |
76 | ||
984ca295 MD |
77 | static const struct renesas_irqc_config irqc0_data = { |
78 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ | |
79 | }; | |
80 | ||
81 | static const struct resource irqc0_resources[] = { | |
82 | DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */ | |
83 | DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */ | |
84 | DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */ | |
85 | DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */ | |
86 | DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */ | |
87 | DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */ | |
88 | DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */ | |
89 | DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */ | |
90 | DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */ | |
91 | DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */ | |
92 | DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */ | |
93 | DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */ | |
94 | DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */ | |
95 | DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */ | |
96 | DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */ | |
97 | DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */ | |
98 | DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */ | |
99 | DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */ | |
100 | DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */ | |
101 | DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */ | |
102 | DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */ | |
103 | DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */ | |
104 | DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */ | |
105 | DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */ | |
106 | DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */ | |
107 | DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */ | |
108 | DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */ | |
109 | DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */ | |
110 | DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */ | |
111 | DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */ | |
112 | DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */ | |
113 | DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */ | |
114 | DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */ | |
115 | }; | |
116 | ||
117 | static const struct renesas_irqc_config irqc1_data = { | |
118 | .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */ | |
119 | }; | |
120 | ||
121 | static const struct resource irqc1_resources[] = { | |
122 | DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */ | |
123 | DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */ | |
124 | DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */ | |
125 | DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */ | |
126 | DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */ | |
127 | DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */ | |
128 | DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */ | |
129 | DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */ | |
130 | DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */ | |
131 | DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */ | |
132 | DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */ | |
133 | DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */ | |
134 | DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */ | |
135 | DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */ | |
136 | DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */ | |
137 | DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */ | |
138 | DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */ | |
139 | DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */ | |
140 | DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */ | |
141 | DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */ | |
142 | DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */ | |
143 | DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */ | |
144 | DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */ | |
145 | DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */ | |
146 | DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */ | |
147 | DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */ | |
148 | DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */ | |
149 | }; | |
150 | ||
151 | #define r8a73a4_register_irqc(idx) \ | |
152 | platform_device_register_resndata(&platform_bus, "renesas_irqc", \ | |
153 | idx, irqc##idx##_resources, \ | |
154 | ARRAY_SIZE(irqc##idx##_resources), \ | |
155 | &irqc##idx##_data, \ | |
156 | sizeof(struct renesas_irqc_config)) | |
157 | ||
eccf0607 MD |
158 | void __init r8a73a4_add_standard_devices(void) |
159 | { | |
e481a528 MD |
160 | r8a73a4_register_scif(SCIFA0); |
161 | r8a73a4_register_scif(SCIFA1); | |
162 | r8a73a4_register_scif(SCIFB0); | |
163 | r8a73a4_register_scif(SCIFB1); | |
164 | r8a73a4_register_scif(SCIFB2); | |
165 | r8a73a4_register_scif(SCIFB3); | |
984ca295 MD |
166 | r8a73a4_register_irqc(0); |
167 | r8a73a4_register_irqc(1); | |
eccf0607 MD |
168 | } |
169 | ||
170 | #ifdef CONFIG_USE_OF | |
171 | void __init r8a73a4_add_standard_devices_dt(void) | |
172 | { | |
173 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | |
174 | } | |
175 | ||
176 | static const char *r8a73a4_boards_compat_dt[] __initdata = { | |
177 | "renesas,r8a73a4", | |
178 | NULL, | |
179 | }; | |
180 | ||
181 | DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") | |
182 | .init_irq = irqchip_init, | |
183 | .init_machine = r8a73a4_add_standard_devices_dt, | |
184 | .init_time = shmobile_timer_init, | |
185 | .dt_compat = r8a73a4_boards_compat_dt, | |
186 | MACHINE_END | |
187 | #endif /* CONFIG_USE_OF */ |