[linux-2.6-block.git] / arch / arm / mach-shmobile / setup-r8a73a4.c

/*
 * r8a73a4 processor support
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/serial_sci.h>
#include <linux/sh_dma.h>
#include <linux/sh_timer.h>

#include <asm/mach/arch.h>

#include "common.h"
#include "dma-register.h"
#include "irqs.h"
#include "r8a73a4.h"

static const struct resource pfc_resources[] = {
	DEFINE_RES_MEM(0xe6050000, 0x9000),
};

void __init r8a73a4_pinmux_init(void)
{
	platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
					ARRAY_SIZE(pfc_resources));
}

#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq)	\
static struct plat_sci_port scif##index##_platform_data = {	\
	.type		= scif_type,				\
	.flags		= UPF_BOOT_AUTOCONF | UPF_IOREMAP,	\
	.scscr		= _scscr,				\
};								\
								\
static struct resource scif##index##_resources[] = {		\
	DEFINE_RES_MEM(baseaddr, 0x100),			\
	DEFINE_RES_IRQ(irq),					\
}

#define R8A73A4_SCIFA(index, baseaddr, irq)	\
	R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
		     index, baseaddr, irq)

#define R8A73A4_SCIFB(index, baseaddr, irq)	\
	R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
		     index, baseaddr, irq)

R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */

#define r8a73a4_register_scif(index)					       \
	platform_device_register_resndata(NULL, "sh-sci", index,	       \
					  scif##index##_resources,	       \
					  ARRAY_SIZE(scif##index##_resources), \
					  &scif##index##_platform_data,	       \
					  sizeof(scif##index##_platform_data))

static const struct renesas_irqc_config irqc0_data = {
	.irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
};

static const struct resource irqc0_resources[] = {
	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
	DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
	DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
	DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
	DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
	DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
	DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
	DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
	DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
	DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
	DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
	DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
	DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
	DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
	DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
	DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
	DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
	DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
	DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
	DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
	DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
	DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
	DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
	DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
	DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
	DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
	DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
	DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
	DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
};

static const struct renesas_irqc_config irqc1_data = {
	.irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
};

static const struct resource irqc1_resources[] = {
	DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
	DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
	DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
	DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
	DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
	DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
	DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
	DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
	DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
	DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
	DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
	DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
	DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
	DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
	DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
	DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
	DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
	DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
	DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
	DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
	DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
	DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
	DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
	DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
	DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
	DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
	DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
};

#define r8a73a4_register_irqc(idx)					\
	platform_device_register_resndata(NULL, "renesas_irqc", 	\
					  idx, irqc##idx##_resources,	\
					  ARRAY_SIZE(irqc##idx##_resources), \
					  &irqc##idx##_data,		\
					  sizeof(struct renesas_irqc_config))

/* Thermal0 -> Thermal2 */
static const struct resource thermal0_resources[] = {
	DEFINE_RES_MEM(0xe61f0000, 0x14),
	DEFINE_RES_MEM(0xe61f0100, 0x38),
	DEFINE_RES_MEM(0xe61f0200, 0x38),
	DEFINE_RES_MEM(0xe61f0300, 0x38),
	DEFINE_RES_IRQ(gic_spi(69)),
};

#define r8a73a4_register_thermal()					\
	platform_device_register_simple("rcar_thermal", -1,		\
					thermal0_resources,		\
					ARRAY_SIZE(thermal0_resources))

static struct sh_timer_config cmt1_platform_data = {
	.channels_mask = 0xff,
};

static struct resource cmt1_resources[] = {
	DEFINE_RES_MEM(0xe6130000, 0x1004),
	DEFINE_RES_IRQ(gic_spi(120)),
};

#define r8a7790_register_cmt(idx)					\
	platform_device_register_resndata(NULL, "sh-cmt-48-gen2",	\
					  idx, cmt##idx##_resources,	\
					  ARRAY_SIZE(cmt##idx##_resources), \
					  &cmt##idx##_platform_data,	\
					  sizeof(struct sh_timer_config))

void __init r8a73a4_add_dt_devices(void)
{
	r8a7790_register_cmt(1);
}

/* DMA */
static const struct sh_dmae_slave_config dma_slaves[] = {
	{
		.slave_id	= SHDMA_SLAVE_MMCIF0_TX,
		.addr		= 0xee200034,
		.chcr		= CHCR_TX(XMIT_SZ_32BIT),
		.mid_rid	= 0xd1,
	}, {
		.slave_id	= SHDMA_SLAVE_MMCIF0_RX,
		.addr		= 0xee200034,
		.chcr		= CHCR_RX(XMIT_SZ_32BIT),
		.mid_rid	= 0xd2,
	}, {
		.slave_id	= SHDMA_SLAVE_MMCIF1_TX,
		.addr		= 0xee220034,
		.chcr		= CHCR_TX(XMIT_SZ_32BIT),
		.mid_rid	= 0xe1,
	}, {
		.slave_id	= SHDMA_SLAVE_MMCIF1_RX,
		.addr		= 0xee220034,
		.chcr		= CHCR_RX(XMIT_SZ_32BIT),
		.mid_rid	= 0xe2,
	},
};

#define DMAE_CHANNEL(a, b)				\
	{						\
		.offset         = (a) - 0x20,		\
		.dmars          = (a) - 0x20 + 0x40,	\
		.chclr_bit	= (b),			\
		.chclr_offset	= 0x80 - 0x20,		\
	}

static const struct sh_dmae_channel dma_channels[] = {
	DMAE_CHANNEL(0x8000, 0),
	DMAE_CHANNEL(0x8080, 1),
	DMAE_CHANNEL(0x8100, 2),
	DMAE_CHANNEL(0x8180, 3),
	DMAE_CHANNEL(0x8200, 4),
	DMAE_CHANNEL(0x8280, 5),
	DMAE_CHANNEL(0x8300, 6),
	DMAE_CHANNEL(0x8380, 7),
	DMAE_CHANNEL(0x8400, 8),
	DMAE_CHANNEL(0x8480, 9),
	DMAE_CHANNEL(0x8500, 10),
	DMAE_CHANNEL(0x8580, 11),
	DMAE_CHANNEL(0x8600, 12),
	DMAE_CHANNEL(0x8680, 13),
	DMAE_CHANNEL(0x8700, 14),
	DMAE_CHANNEL(0x8780, 15),
	DMAE_CHANNEL(0x8800, 16),
	DMAE_CHANNEL(0x8880, 17),
	DMAE_CHANNEL(0x8900, 18),
	DMAE_CHANNEL(0x8980, 19),
};

static const struct sh_dmae_pdata dma_pdata = {
	.slave		= dma_slaves,
	.slave_num	= ARRAY_SIZE(dma_slaves),
	.channel	= dma_channels,
	.channel_num	= ARRAY_SIZE(dma_channels),
	.ts_low_shift	= TS_LOW_SHIFT,
	.ts_low_mask	= TS_LOW_BIT << TS_LOW_SHIFT,
	.ts_high_shift	= TS_HI_SHIFT,
	.ts_high_mask	= TS_HI_BIT << TS_HI_SHIFT,
	.ts_shift	= dma_ts_shift,
	.ts_shift_num	= ARRAY_SIZE(dma_ts_shift),
	.dmaor_init     = DMAOR_DME,
	.chclr_present	= 1,
	.chclr_bitwise	= 1,
};

static struct resource dma_resources[] = {
	DEFINE_RES_MEM(0xe6700020, 0x89e0),
	DEFINE_RES_IRQ(gic_spi(220)),
	{
		/* IRQ for channels 0-19 */
		.start  = gic_spi(200),
		.end    = gic_spi(219),
		.flags  = IORESOURCE_IRQ,
	},
};

#define r8a73a4_register_dmac()							\
	platform_device_register_resndata(NULL, "sh-dma-engine", 0,		\
				dma_resources, ARRAY_SIZE(dma_resources),	\
				&dma_pdata, sizeof(dma_pdata))

void __init r8a73a4_add_standard_devices(void)
{
	r8a73a4_add_dt_devices();
	r8a73a4_register_scif(0);
	r8a73a4_register_scif(1);
	r8a73a4_register_scif(2);
	r8a73a4_register_scif(3);
	r8a73a4_register_scif(4);
	r8a73a4_register_scif(5);
	r8a73a4_register_irqc(0);
	r8a73a4_register_irqc(1);
	r8a73a4_register_thermal();
	r8a73a4_register_dmac();
}

#ifdef CONFIG_USE_OF

static const char *r8a73a4_boards_compat_dt[] __initdata = {
	"renesas,r8a73a4",
	NULL,
};

DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
	.init_early	= shmobile_init_delay,
	.init_late	= shmobile_init_late,
	.dt_compat	= r8a73a4_boards_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
Commit	Line	Data
eccf0607 MD	1	/*
	2	* r8a73a4 processor support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Magnus Damm
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20	#include <linux/irq.h>
eccf0607 MD	21	#include <linux/kernel.h>
eccf0607 MD	22	#include <linux/of_platform.h>
984ca295	23	#include <linux/platform_data/irq-renesas-irqc.h>
e481a528	24	#include <linux/serial_sci.h>
9f754b4a	25	#include <linux/sh_dma.h>
a7b99f27	26	#include <linux/sh_timer.h>
fac49568	27
eccf0607 MD	28	#include <asm/mach/arch.h>
eccf0607 MD	29
fd44aa5e	30	#include "common.h"
74ac0de8	31	#include "dma-register.h"
b6bab126	32	#include "irqs.h"
fac49568	33	#include "r8a73a4.h"
eccf0607	34
d313d068 MD	35	static const struct resource pfc_resources[] = {
	36	DEFINE_RES_MEM(0xe6050000, 0x9000),
	37	};
	38
	39	void __init r8a73a4_pinmux_init(void)
	40	{
	41	platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
	42	ARRAY_SIZE(pfc_resources));
	43	}
	44
4d32e834 LP	45	#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \
4d32e834 LP	46	static struct plat_sci_port scif##index##_platform_data = { \
e481a528	47	.type = scif_type, \
e481a528	48	.flags = UPF_BOOT_AUTOCONF \| UPF_IOREMAP, \
4d32e834	49	.scscr = _scscr, \
8826478e LP	50	}; \
	51	\
	52	static struct resource scif##index##_resources[] = { \
	53	DEFINE_RES_MEM(baseaddr, 0x100), \
	54	DEFINE_RES_IRQ(irq), \
e481a528 MD	55	}
e481a528 MD	56
4d32e834 LP	57	#define R8A73A4_SCIFA(index, baseaddr, irq) \
	58	R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE \| SCSCR_TE \| SCSCR_CKE0, \
	59	index, baseaddr, irq)
e481a528	60
4d32e834 LP	61	#define R8A73A4_SCIFB(index, baseaddr, irq) \
	62	R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE \| SCSCR_TE, \
	63	index, baseaddr, irq)
e481a528	64
4d32e834 LP	65	R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
	66	R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
	67	R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
	68	R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
	69	R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
	70	R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
e481a528	71
4d32e834	72	#define r8a73a4_register_scif(index) \
d2168146	73	platform_device_register_resndata(NULL, "sh-sci", index, \
8826478e LP	74	scif##index##_resources, \
	75	ARRAY_SIZE(scif##index##_resources), \
	76	&scif##index##_platform_data, \
	77	sizeof(scif##index##_platform_data))
e481a528	78
984ca295 MD	79	static const struct renesas_irqc_config irqc0_data = {
	80	.irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
	81	};
	82
	83	static const struct resource irqc0_resources[] = {
	84	DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
	85	DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
	86	DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
	87	DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
	88	DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
	89	DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
	90	DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
	91	DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
	92	DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
	93	DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
	94	DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
	95	DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
	96	DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
	97	DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
	98	DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
	99	DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
	100	DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
	101	DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
	102	DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
	103	DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
	104	DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
	105	DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
	106	DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
	107	DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
	108	DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
	109	DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
	110	DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
	111	DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
	112	DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
	113	DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
	114	DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
	115	DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
	116	DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
	117	};
	118
	119	static const struct renesas_irqc_config irqc1_data = {
	120	.irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
	121	};
	122
	123	static const struct resource irqc1_resources[] = {
	124	DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
	125	DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
	126	DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
	127	DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
	128	DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
	129	DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
	130	DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
	131	DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
	132	DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
	133	DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
	134	DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
	135	DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
	136	DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
	137	DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
	138	DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
	139	DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
	140	DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
	141	DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
	142	DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
143	DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
144	DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
145	DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
146	DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
147	DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
148	DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
149	DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
150	DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
151	};
152
153	#define r8a73a4_register_irqc(idx) \
d2168146	154	platform_device_register_resndata(NULL, "renesas_irqc", \
984ca295 MD	155	idx, irqc##idx##_resources, \
	156	ARRAY_SIZE(irqc##idx##_resources), \
	157	&irqc##idx##_data, \
	158	sizeof(struct renesas_irqc_config))
	159
c91cf2fa KM	160	/* Thermal0 -> Thermal2 */
	161	static const struct resource thermal0_resources[] = {
	162	DEFINE_RES_MEM(0xe61f0000, 0x14),
	163	DEFINE_RES_MEM(0xe61f0100, 0x38),
	164	DEFINE_RES_MEM(0xe61f0200, 0x38),
	165	DEFINE_RES_MEM(0xe61f0300, 0x38),
	166	DEFINE_RES_IRQ(gic_spi(69)),
	167	};
	168
	169	#define r8a73a4_register_thermal() \
	170	platform_device_register_simple("rcar_thermal", -1, \
	171	thermal0_resources, \
	172	ARRAY_SIZE(thermal0_resources))
	173
52065ef7 LP	174	static struct sh_timer_config cmt1_platform_data = {
52065ef7 LP	175	.channels_mask = 0xff,
a7b99f27 MD	176	};
a7b99f27 MD	177
52065ef7 LP	178	static struct resource cmt1_resources[] = {
	179	DEFINE_RES_MEM(0xe6130000, 0x1004),
	180	DEFINE_RES_IRQ(gic_spi(120)),
a7b99f27 MD	181	};
	182
	183	#define r8a7790_register_cmt(idx) \
d2168146	184	platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \
a7b99f27 MD	185	idx, cmt##idx##_resources, \
	186	ARRAY_SIZE(cmt##idx##_resources), \
	187	&cmt##idx##_platform_data, \
	188	sizeof(struct sh_timer_config))
	189
69f36661	190	void __init r8a73a4_add_dt_devices(void)
eccf0607	191	{
52065ef7	192	r8a7790_register_cmt(1);
69f36661 GL	193	}
69f36661 GL	194
9f754b4a GL	195	/* DMA */
	196	static const struct sh_dmae_slave_config dma_slaves[] = {
	197	{
	198	.slave_id = SHDMA_SLAVE_MMCIF0_TX,
	199	.addr = 0xee200034,
	200	.chcr = CHCR_TX(XMIT_SZ_32BIT),
	201	.mid_rid = 0xd1,
	202	}, {
	203	.slave_id = SHDMA_SLAVE_MMCIF0_RX,
	204	.addr = 0xee200034,
	205	.chcr = CHCR_RX(XMIT_SZ_32BIT),
	206	.mid_rid = 0xd2,
	207	}, {
	208	.slave_id = SHDMA_SLAVE_MMCIF1_TX,
	209	.addr = 0xee220034,
	210	.chcr = CHCR_TX(XMIT_SZ_32BIT),
	211	.mid_rid = 0xe1,
	212	}, {
	213	.slave_id = SHDMA_SLAVE_MMCIF1_RX,
	214	.addr = 0xee220034,
	215	.chcr = CHCR_RX(XMIT_SZ_32BIT),
	216	.mid_rid = 0xe2,
	217	},
	218	};
	219
	220	#define DMAE_CHANNEL(a, b) \
	221	{ \
	222	.offset = (a) - 0x20, \
	223	.dmars = (a) - 0x20 + 0x40, \
	224	.chclr_bit = (b), \
	225	.chclr_offset = 0x80 - 0x20, \
	226	}
	227
	228	static const struct sh_dmae_channel dma_channels[] = {
	229	DMAE_CHANNEL(0x8000, 0),
	230	DMAE_CHANNEL(0x8080, 1),
	231	DMAE_CHANNEL(0x8100, 2),
	232	DMAE_CHANNEL(0x8180, 3),
	233	DMAE_CHANNEL(0x8200, 4),
	234	DMAE_CHANNEL(0x8280, 5),
	235	DMAE_CHANNEL(0x8300, 6),
	236	DMAE_CHANNEL(0x8380, 7),
	237	DMAE_CHANNEL(0x8400, 8),
	238	DMAE_CHANNEL(0x8480, 9),
	239	DMAE_CHANNEL(0x8500, 10),
	240	DMAE_CHANNEL(0x8580, 11),
	241	DMAE_CHANNEL(0x8600, 12),
	242	DMAE_CHANNEL(0x8680, 13),
	243	DMAE_CHANNEL(0x8700, 14),
	244	DMAE_CHANNEL(0x8780, 15),
	245	DMAE_CHANNEL(0x8800, 16),
	246	DMAE_CHANNEL(0x8880, 17),
	247	DMAE_CHANNEL(0x8900, 18),
	248	DMAE_CHANNEL(0x8980, 19),
	249	};
	250
	251	static const struct sh_dmae_pdata dma_pdata = {
	252	.slave = dma_slaves,
	253	.slave_num = ARRAY_SIZE(dma_slaves),
	254	.channel = dma_channels,
	255	.channel_num = ARRAY_SIZE(dma_channels),
	256	.ts_low_shift = TS_LOW_SHIFT,
	257	.ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
	258	.ts_high_shift = TS_HI_SHIFT,
259	.ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
260	.ts_shift = dma_ts_shift,
261	.ts_shift_num = ARRAY_SIZE(dma_ts_shift),
262	.dmaor_init = DMAOR_DME,
263	.chclr_present = 1,
264	.chclr_bitwise = 1,
265	};
266
267	static struct resource dma_resources[] = {
268	DEFINE_RES_MEM(0xe6700020, 0x89e0),
1a936a38	269	DEFINE_RES_IRQ(gic_spi(220)),
9f754b4a GL	270	{
	271	/* IRQ for channels 0-19 */
	272	.start = gic_spi(200),
	273	.end = gic_spi(219),
	274	.flags = IORESOURCE_IRQ,
	275	},
	276	};
	277
	278	#define r8a73a4_register_dmac() \
d2168146	279	platform_device_register_resndata(NULL, "sh-dma-engine", 0, \
9f754b4a GL	280	dma_resources, ARRAY_SIZE(dma_resources), \
	281	&dma_pdata, sizeof(dma_pdata))
	282
69f36661 GL	283	void __init r8a73a4_add_standard_devices(void)
	284	{
	285	r8a73a4_add_dt_devices();
27bc8235 SH	286	r8a73a4_register_scif(0);
	287	r8a73a4_register_scif(1);
	288	r8a73a4_register_scif(2);
	289	r8a73a4_register_scif(3);
	290	r8a73a4_register_scif(4);
	291	r8a73a4_register_scif(5);
984ca295 MD	292	r8a73a4_register_irqc(0);
984ca295 MD	293	r8a73a4_register_irqc(1);
c91cf2fa	294	r8a73a4_register_thermal();
9f754b4a	295	r8a73a4_register_dmac();
eccf0607 MD	296	}
	297
	298	#ifdef CONFIG_USE_OF
eccf0607 MD	299
	300	static const char *r8a73a4_boards_compat_dt[] __initdata = {
	301	"renesas,r8a73a4",
	302	NULL,
	303	};
	304
	305	DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
f5720080	306	.init_early = shmobile_init_delay,
0592d1b5	307	.init_late = shmobile_init_late,
eccf0607 MD	308	.dt_compat = r8a73a4_boards_compat_dt,
	309	MACHINE_END
	310	#endif /* CONFIG_USE_OF */