[linux-block.git] / arch / arm / mach-shmobile / headsmp-scu.S

/* SPDX-License-Identifier: GPL-2.0+
 *
 * Shared SCU setup for mach-shmobile
 *
 * Copyright (C) 2012 Bastian Hecht
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/page.h>

/*
 * Boot code for secondary CPUs.
 *
 * First we turn on L1 cache coherency for our CPU. Then we jump to
 * secondary_startup that invalidates the cache and hands over control
 * to the common ARM startup code.
 */
ENTRY(shmobile_boot_scu)
					@ r0 = SCU base address
	mrc     p15, 0, r1, c0, c0, 5	@ read MPIDR
	and	r1, r1, #3		@ mask out cpu ID
	lsl	r1, r1, #3		@ we will shift by cpu_id * 8 bits
	ldr	r2, [r0, #8]		@ SCU Power Status Register
	mov	r3, #3
	lsl	r3, r3, r1
	bic	r2, r2, r3		@ Clear bits of our CPU (Run Mode)
	str	r2, [r0, #8]		@ write back

	b	secondary_startup
ENDPROC(shmobile_boot_scu)
Commit	Line	Data
e2f2594b KM	1	/* SPDX-License-Identifier: GPL-2.0+
e2f2594b KM	2	*
ec0d84a8 MD	3	* Shared SCU setup for mach-shmobile
	4	*
	5	* Copyright (C) 2012 Bastian Hecht
ec0d84a8 MD	6	*/
	7
	8	#include <linux/linkage.h>
	9	#include <linux/init.h>
a9ff6961	10	#include <asm/page.h>
ec0d84a8	11
ec0d84a8	12	/*
4f6da36f	13	* Boot code for secondary CPUs.
ec0d84a8 MD	14	*
ec0d84a8 MD	15	* First we turn on L1 cache coherency for our CPU. Then we jump to
02b4e275	16	* secondary_startup that invalidates the cache and hands over control
ec0d84a8	17	* to the common ARM startup code.
ec0d84a8	18	*/
bfabbcc6 MD	19	ENTRY(shmobile_boot_scu)
bfabbcc6 MD	20	@ r0 = SCU base address
e24f317c	21	mrc p15, 0, r1, c0, c0, 5 @ read MPIDR
bfabbcc6 MD	22	and r1, r1, #3 @ mask out cpu ID
	23	lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
	24	ldr r2, [r0, #8] @ SCU Power Status Register
	25	mov r3, #3
bdea6c65 TK	26	lsl r3, r3, r1
bdea6c65 TK	27	bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
bfabbcc6 MD	28	str r2, [r0, #8] @ write back
bfabbcc6 MD	29
02b4e275	30	b secondary_startup
bfabbcc6	31	ENDPROC(shmobile_boot_scu)