[linux-2.6-block.git] / arch / arm / mach-shmobile / clock-r8a7790.c

/*
 * r8a7790 clock framework support
 *
 * Copyright (C) 2013  Renesas Solutions Corp.
 * Copyright (C) 2013  Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/sh_clk.h>
#include <linux/clkdev.h>

#include "clock.h"
#include "common.h"
#include "r8a7790.h"
#include "rcar-gen2.h"

/*
 *   MD		EXTAL		PLL0	PLL1	PLL3
 * 14 13 19	(MHz)		*1	*1
 *---------------------------------------------------
 * 0  0  0	15 x 1		x172/2	x208/2	x106
 * 0  0  1	15 x 1		x172/2	x208/2	x88
 * 0  1  0	20 x 1		x130/2	x156/2	x80
 * 0  1  1	20 x 1		x130/2	x156/2	x66
 * 1  0  0	26 / 2		x200/2	x240/2	x122
 * 1  0  1	26 / 2		x200/2	x240/2	x102
 * 1  1  0	30 / 2		x172/2	x208/2	x106
 * 1  1  1	30 / 2		x172/2	x208/2	x88
 *
 * *1 :	Table 7.6 indicates VCO ouput (PLLx = VCO/2)
 *	see "p1 / 2" on R8A7790_CLOCK_ROOT() below
 */

#define CPG_BASE	0xe6150000
#define CPG_LEN		0x1000

#define SMSTPCR1	0xe6150134
#define SMSTPCR2	0xe6150138
#define SMSTPCR3	0xe615013c
#define SMSTPCR5	0xe6150144
#define SMSTPCR7	0xe615014c
#define SMSTPCR8	0xe6150990
#define SMSTPCR9	0xe6150994
#define SMSTPCR10	0xe6150998

#define MSTPSR1		IOMEM(0xe6150038)
#define MSTPSR2		IOMEM(0xe6150040)
#define MSTPSR3		IOMEM(0xe6150048)
#define MSTPSR5		IOMEM(0xe615003c)
#define MSTPSR7		IOMEM(0xe61501c4)
#define MSTPSR8		IOMEM(0xe61509a0)
#define MSTPSR9		IOMEM(0xe61509a4)
#define MSTPSR10	IOMEM(0xe61509a8)

#define SDCKCR		0xE6150074
#define SD2CKCR		0xE6150078
#define SD3CKCR		0xE615007C
#define MMC0CKCR	0xE6150240
#define MMC1CKCR	0xE6150244
#define SSPCKCR		0xE6150248
#define SSPRSCKCR	0xE615024C

static struct clk_mapping cpg_mapping = {
	.phys   = CPG_BASE,
	.len    = CPG_LEN,
};

static struct clk extal_clk = {
	/* .rate will be updated on r8a7790_clock_init() */
	.mapping	= &cpg_mapping,
};

static struct sh_clk_ops followparent_clk_ops = {
	.recalc	= followparent_recalc,
};

static struct clk main_clk = {
	/* .parent will be set r8a7790_clock_init */
	.ops	= &followparent_clk_ops,
};

static struct clk audio_clk_a = {
};

static struct clk audio_clk_b = {
};

static struct clk audio_clk_c = {
};

/*
 * clock ratio of these clock will be updated
 * on r8a7790_clock_init()
 */
SH_FIXED_RATIO_CLK_SET(pll1_clk,		main_clk,	1, 1);
SH_FIXED_RATIO_CLK_SET(pll3_clk,		main_clk,	1, 1);
SH_FIXED_RATIO_CLK_SET(lb_clk,			pll1_clk,	1, 1);
SH_FIXED_RATIO_CLK_SET(qspi_clk,		pll1_clk,	1, 1);

/* fixed ratio clock */
SH_FIXED_RATIO_CLK_SET(extal_div2_clk,		extal_clk,	1, 2);
SH_FIXED_RATIO_CLK_SET(cp_clk,			extal_clk,	1, 2);

SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,		pll1_clk,	1, 2);
SH_FIXED_RATIO_CLK_SET(zg_clk,			pll1_clk,	1, 3);
SH_FIXED_RATIO_CLK_SET(zx_clk,			pll1_clk,	1, 3);
SH_FIXED_RATIO_CLK_SET(zs_clk,			pll1_clk,	1, 6);
SH_FIXED_RATIO_CLK_SET(hp_clk,			pll1_clk,	1, 12);
SH_FIXED_RATIO_CLK_SET(i_clk,			pll1_clk,	1, 2);
SH_FIXED_RATIO_CLK_SET(b_clk,			pll1_clk,	1, 12);
SH_FIXED_RATIO_CLK_SET(p_clk,			pll1_clk,	1, 24);
SH_FIXED_RATIO_CLK_SET(cl_clk,			pll1_clk,	1, 48);
SH_FIXED_RATIO_CLK_SET(m2_clk,			pll1_clk,	1, 8);
SH_FIXED_RATIO_CLK_SET(imp_clk,			pll1_clk,	1, 4);
SH_FIXED_RATIO_CLK_SET(rclk_clk,		pll1_clk,	1, (48 * 1024));
SH_FIXED_RATIO_CLK_SET(oscclk_clk,		pll1_clk,	1, (12 * 1024));

SH_FIXED_RATIO_CLK_SET(zb3_clk,			pll3_clk,	1, 4);
SH_FIXED_RATIO_CLK_SET(zb3d2_clk,		pll3_clk,	1, 8);
SH_FIXED_RATIO_CLK_SET(ddr_clk,			pll3_clk,	1, 8);
SH_FIXED_RATIO_CLK_SET(mp_clk,			pll1_div2_clk,	1, 15);

static struct clk *main_clks[] = {
	&audio_clk_a,
	&audio_clk_b,
	&audio_clk_c,
	&extal_clk,
	&extal_div2_clk,
	&main_clk,
	&pll1_clk,
	&pll1_div2_clk,
	&pll3_clk,
	&lb_clk,
	&qspi_clk,
	&zg_clk,
	&zx_clk,
	&zs_clk,
	&hp_clk,
	&i_clk,
	&b_clk,
	&p_clk,
	&cl_clk,
	&m2_clk,
	&imp_clk,
	&rclk_clk,
	&oscclk_clk,
	&zb3_clk,
	&zb3d2_clk,
	&ddr_clk,
	&mp_clk,
	&cp_clk,
};

/* SDHI (DIV4) clock */
static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = divisors,
	.nr_divisors = ARRAY_SIZE(divisors),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

enum {
	DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
};

static struct clk div4_clks[DIV4_NR] = {
	[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
	[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
	[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
};

/* DIV6 clocks */
enum {
	DIV6_SD2, DIV6_SD3,
	DIV6_MMC0, DIV6_MMC1,
	DIV6_SSP, DIV6_SSPRS,
	DIV6_NR
};

static struct clk div6_clks[DIV6_NR] = {
	[DIV6_SD2]	= SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
	[DIV6_SD3]	= SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
	[DIV6_MMC0]	= SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
	[DIV6_MMC1]	= SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
	[DIV6_SSP]	= SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
	[DIV6_SSPRS]	= SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
};

/* MSTP */
enum {
	MSTP1017, /* parent of SCU */

	MSTP1031, MSTP1030,
	MSTP1029, MSTP1028, MSTP1027, MSTP1026, MSTP1025, MSTP1024, MSTP1023, MSTP1022,
	MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
	MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
	MSTP931, MSTP930, MSTP929, MSTP928,
	MSTP917,
	MSTP815, MSTP814,
	MSTP813,
	MSTP811, MSTP810, MSTP809, MSTP808,
	MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
	MSTP717, MSTP716,
	MSTP704, MSTP703,
	MSTP522,
	MSTP502, MSTP501,
	MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
	MSTP124,
	MSTP_NR
};

static struct clk mstp_clks[MSTP_NR] = {
	[MSTP1031] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 31, MSTPSR10, 0), /* SCU0 */
	[MSTP1030] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 30, MSTPSR10, 0), /* SCU1 */
	[MSTP1029] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 29, MSTPSR10, 0), /* SCU2 */
	[MSTP1028] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 28, MSTPSR10, 0), /* SCU3 */
	[MSTP1027] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 27, MSTPSR10, 0), /* SCU4 */
	[MSTP1026] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 26, MSTPSR10, 0), /* SCU5 */
	[MSTP1025] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 25, MSTPSR10, 0), /* SCU6 */
	[MSTP1024] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 24, MSTPSR10, 0), /* SCU7 */
	[MSTP1023] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 23, MSTPSR10, 0), /* SCU8 */
	[MSTP1022] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 22, MSTPSR10, 0), /* SCU9 */
	[MSTP1017] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 17, MSTPSR10, 0), /* SCU */
	[MSTP1015] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 15, MSTPSR10, 0), /* SSI0 */
	[MSTP1014] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 14, MSTPSR10, 0), /* SSI1 */
	[MSTP1013] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 13, MSTPSR10, 0), /* SSI2 */
	[MSTP1012] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 12, MSTPSR10, 0), /* SSI3 */
	[MSTP1011] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 11, MSTPSR10, 0), /* SSI4 */
	[MSTP1010] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 10, MSTPSR10, 0), /* SSI5 */
	[MSTP1009] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 9, MSTPSR10, 0), /* SSI6 */
	[MSTP1008] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 8, MSTPSR10, 0), /* SSI7 */
	[MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
	[MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
	[MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
	[MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
	[MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
	[MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
	[MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
	[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
	[MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
	[MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
	[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
	[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
	[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
	[MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  9, MSTPSR8, 0), /* VIN2 */
	[MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  8, MSTPSR8, 0), /* VIN3 */
	[MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
	[MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
	[MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
	[MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
	[MSTP722] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 22, MSTPSR7, 0), /* DU2 */
	[MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
	[MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
	[MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */
	[MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
	[MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
	[MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
	[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
	[MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
	[MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
	[MSTP315] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, MSTPSR3, 0), /* MMC0 */
	[MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
	[MSTP313] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD1], SMSTPCR3, 13, MSTPSR3, 0), /* SDHI1 */
	[MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI2 */
	[MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD3], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI3 */
	[MSTP305] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, MSTPSR3, 0), /* MMC1 */
	[MSTP304] = SH_CLK_MSTP32_STS(&cp_clk, SMSTPCR3, 4, MSTPSR3, 0), /* TPU0 */
	[MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
	[MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
	[MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
	[MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
	[MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
	[MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
	[MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
};

static struct clk_lookup lookups[] = {

	/* main clocks */
	CLKDEV_CON_ID("extal",		&extal_clk),
	CLKDEV_CON_ID("extal_div2",	&extal_div2_clk),
	CLKDEV_CON_ID("main",		&main_clk),
	CLKDEV_CON_ID("pll1",		&pll1_clk),
	CLKDEV_CON_ID("pll1_div2",	&pll1_div2_clk),
	CLKDEV_CON_ID("pll3",		&pll3_clk),
	CLKDEV_CON_ID("zg",		&zg_clk),
	CLKDEV_CON_ID("zx",		&zx_clk),
	CLKDEV_CON_ID("zs",		&zs_clk),
	CLKDEV_CON_ID("hp",		&hp_clk),
	CLKDEV_CON_ID("i",		&i_clk),
	CLKDEV_CON_ID("b",		&b_clk),
	CLKDEV_CON_ID("lb",		&lb_clk),
	CLKDEV_CON_ID("p",		&p_clk),
	CLKDEV_CON_ID("cl",		&cl_clk),
	CLKDEV_CON_ID("m2",		&m2_clk),
	CLKDEV_CON_ID("imp",		&imp_clk),
	CLKDEV_CON_ID("rclk",		&rclk_clk),
	CLKDEV_CON_ID("oscclk",		&oscclk_clk),
	CLKDEV_CON_ID("zb3",		&zb3_clk),
	CLKDEV_CON_ID("zb3d2",		&zb3d2_clk),
	CLKDEV_CON_ID("ddr",		&ddr_clk),
	CLKDEV_CON_ID("mp",		&mp_clk),
	CLKDEV_CON_ID("qspi",		&qspi_clk),
	CLKDEV_CON_ID("cp",		&cp_clk),

	/* DIV4 */
	CLKDEV_CON_ID("sdh",		&div4_clks[DIV4_SDH]),

	/* DIV6 */
	CLKDEV_CON_ID("ssp",		&div6_clks[DIV6_SSP]),
	CLKDEV_CON_ID("ssprs",		&div6_clks[DIV6_SSPRS]),

	/* MSTP */
	CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
	CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
	CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
	CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
	CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
	CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
	CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
	CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
	CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
	CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
	CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
	CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
	CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
	CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
	CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
	CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
	CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
	CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
	CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
	CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
	CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
	CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
	CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
	CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
	CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),

	/* ICK */
	CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]),
	CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
	CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
	CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
	CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
	CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
	CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
	CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
	CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
	CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
	CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
	CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP1031]),
	CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP1030]),
	CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP1029]),
	CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP1028]),
	CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP1027]),
	CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP1026]),
	CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP1025]),
	CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP1024]),
	CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP1023]),
	CLKDEV_ICK_ID("src.9", "rcar_sound", &mstp_clks[MSTP1022]),
	CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
	CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
	CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
	CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
	CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
	CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
	CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
	CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
	CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
	CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),

};

#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\
	extal_clk.rate	= e * 1000 * 1000;			\
	main_clk.parent	= m;					\
	SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);		\
	if (mode & MD(19))					\
		SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);	\
	else							\
		SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)


void __init r8a7790_clock_init(void)
{
	u32 mode = rcar_gen2_read_mode_pins();
	int k, ret = 0;

	switch (mode & (MD(14) | MD(13))) {
	case 0:
		R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
		break;
	case MD(13):
		R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
		break;
	case MD(14):
		R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
		break;
	case MD(13) | MD(14):
		R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
		break;
	}

	if (mode & (MD(18)))
		SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
	else
		SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);

	if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
		SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
	else
		SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);

	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
		ret = clk_register(main_clks[k]);

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);

	if (!ret)
		ret = sh_clk_div6_register(div6_clks, DIV6_NR);

	if (!ret)
		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		shmobile_clk_init();
	else
		panic("failed to setup r8a7790 clocks\n");
}
Commit	Line	Data
0468b2d6 MD	1	/*
	2	* r8a7790 clock framework support
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Magnus Damm
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	*/
	20	#include <linux/init.h>
	21	#include <linux/io.h>
	22	#include <linux/kernel.h>
	23	#include <linux/sh_clk.h>
	24	#include <linux/clkdev.h>
fccae893	25
ad6ffa0b	26	#include "clock.h"
fd44aa5e	27	#include "common.h"
fccae893	28	#include "r8a7790.h"
62872989	29	#include "rcar-gen2.h"
0468b2d6	30
8d100c04 KM	31	/*
	32	* MD EXTAL PLL0 PLL1 PLL3
	33	* 14 13 19 (MHz) 1 1
	34	*---------------------------------------------------
	35	* 0 0 0 15 x 1 x172/2 x208/2 x106
	36	* 0 0 1 15 x 1 x172/2 x208/2 x88
	37	* 0 1 0 20 x 1 x130/2 x156/2 x80
	38	* 0 1 1 20 x 1 x130/2 x156/2 x66
	39	* 1 0 0 26 / 2 x200/2 x240/2 x122
	40	* 1 0 1 26 / 2 x200/2 x240/2 x102
	41	* 1 1 0 30 / 2 x172/2 x208/2 x106
	42	* 1 1 1 30 / 2 x172/2 x208/2 x88
	43	*
	44	* *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
	45	* see "p1 / 2" on R8A7790_CLOCK_ROOT() below
	46	*/
	47
cb9ec3ad SK	48	#define CPG_BASE 0xe6150000
cb9ec3ad SK	49	#define CPG_LEN 0x1000
0468b2d6	50
cb9ec3ad SK	51	#define SMSTPCR1 0xe6150134
	52	#define SMSTPCR2 0xe6150138
	53	#define SMSTPCR3 0xe615013c
	54	#define SMSTPCR5 0xe6150144
	55	#define SMSTPCR7 0xe615014c
	56	#define SMSTPCR8 0xe6150990
	57	#define SMSTPCR9 0xe6150994
	58	#define SMSTPCR10 0xe6150998
	59
	60	#define MSTPSR1 IOMEM(0xe6150038)
	61	#define MSTPSR2 IOMEM(0xe6150040)
	62	#define MSTPSR3 IOMEM(0xe6150048)
	63	#define MSTPSR5 IOMEM(0xe615003c)
	64	#define MSTPSR7 IOMEM(0xe61501c4)
	65	#define MSTPSR8 IOMEM(0xe61509a0)
	66	#define MSTPSR9 IOMEM(0xe61509a4)
	67	#define MSTPSR10 IOMEM(0xe61509a8)
55d9fab2	68
9f13ee6f	69	#define SDCKCR 0xE6150074
46632512 KM	70	#define SD2CKCR 0xE6150078
	71	#define SD3CKCR 0xE615007C
	72	#define MMC0CKCR 0xE6150240
	73	#define MMC1CKCR 0xE6150244
	74	#define SSPCKCR 0xE6150248
	75	#define SSPRSCKCR 0xE615024C
8d100c04	76
0468b2d6 MD	77	static struct clk_mapping cpg_mapping = {
	78	.phys = CPG_BASE,
	79	.len = CPG_LEN,
	80	};
	81
8d100c04 KM	82	static struct clk extal_clk = {
8d100c04 KM	83	/* .rate will be updated on r8a7790_clock_init() */
55d9fab2 MD	84	.mapping = &cpg_mapping,
	85	};
	86
8d100c04 KM	87	static struct sh_clk_ops followparent_clk_ops = {
8d100c04 KM	88	.recalc = followparent_recalc,
55d9fab2 MD	89	};
55d9fab2 MD	90
8d100c04	91	static struct clk main_clk = {
7d947813	92	/* .parent will be set r8a7790_clock_init */
8d100c04 KM	93	.ops = &followparent_clk_ops,
	94	};
	95
c7c2ec3a KM	96	static struct clk audio_clk_a = {
	97	};
	98
	99	static struct clk audio_clk_b = {
	100	};
	101
	102	static struct clk audio_clk_c = {
	103	};
	104
8d100c04 KM	105	/*
	106	* clock ratio of these clock will be updated
	107	* on r8a7790_clock_init()
	108	*/
	109	SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
	110	SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
	111	SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1);
	112	SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
	113
	114	/* fixed ratio clock */
	115	SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
	116	SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
	117
	118	SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
	119	SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
	120	SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
	121	SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
	122	SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
	123	SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2);
	124	SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12);
	125	SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
	126	SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48);
	127	SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8);
	128	SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4);
	129	SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
	130	SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024));
	131
	132	SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4);
	133	SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8);
	134	SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8);
	135	SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
	136
0468b2d6	137	static struct clk *main_clks[] = {
c7c2ec3a KM	138	&audio_clk_a,
	139	&audio_clk_b,
	140	&audio_clk_c,
8d100c04 KM	141	&extal_clk,
	142	&extal_div2_clk,
	143	&main_clk,
	144	&pll1_clk,
	145	&pll1_div2_clk,
	146	&pll3_clk,
	147	&lb_clk,
	148	&qspi_clk,
	149	&zg_clk,
	150	&zx_clk,
	151	&zs_clk,
	152	&hp_clk,
	153	&i_clk,
	154	&b_clk,
55d9fab2	155	&p_clk,
8d100c04 KM	156	&cl_clk,
	157	&m2_clk,
	158	&imp_clk,
	159	&rclk_clk,
	160	&oscclk_clk,
	161	&zb3_clk,
	162	&zb3d2_clk,
	163	&ddr_clk,
55d9fab2	164	&mp_clk,
8d100c04	165	&cp_clk,
0468b2d6 MD	166	};
0468b2d6 MD	167
9f13ee6f KM	168	/* SDHI (DIV4) clock */
	169	static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
	170
	171	static struct clk_div_mult_table div4_div_mult_table = {
	172	.divisors = divisors,
	173	.nr_divisors = ARRAY_SIZE(divisors),
	174	};
	175
	176	static struct clk_div4_table div4_table = {
	177	.div_mult_table = &div4_div_mult_table,
	178	};
	179
	180	enum {
	181	DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
	182	};
	183
72378a4a	184	static struct clk div4_clks[DIV4_NR] = {
9f13ee6f	185	[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
4fb12fe9 KM	186	[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
4fb12fe9 KM	187	[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
9f13ee6f KM	188	};
9f13ee6f KM	189
46632512 KM	190	/* DIV6 clocks */
	191	enum {
	192	DIV6_SD2, DIV6_SD3,
	193	DIV6_MMC0, DIV6_MMC1,
	194	DIV6_SSP, DIV6_SSPRS,
	195	DIV6_NR
	196	};
	197
	198	static struct clk div6_clks[DIV6_NR] = {
	199	[DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
	200	[DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
	201	[DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
	202	[DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
	203	[DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
	204	[DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
	205	};
	206
9f13ee6f	207	/* MSTP */
aa9c185b	208	enum {
9ced1d47 KM	209	MSTP1017, /* parent of SCU */
	210
	211	MSTP1031, MSTP1030,
	212	MSTP1029, MSTP1028, MSTP1027, MSTP1026, MSTP1025, MSTP1024, MSTP1023, MSTP1022,
b3cc52eb KM	213	MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
b3cc52eb KM	214	MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
911a644c	215	MSTP931, MSTP930, MSTP929, MSTP928,
3dd3b1cf	216	MSTP917,
64b7f9ac	217	MSTP815, MSTP814,
9b0b9c01	218	MSTP813,
b89dfdfa	219	MSTP811, MSTP810, MSTP809, MSTP808,
9d8907c4	220	MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
729cb826	221	MSTP717, MSTP716,
012a7069	222	MSTP704, MSTP703,
a4b91be0	223	MSTP522,
f5b2947e	224	MSTP502, MSTP501,
018222f5	225	MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
aa9c185b	226	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
99ade1a0	227	MSTP124,
aa9c185b LP	228	MSTP_NR
	229	};
	230
0468b2d6	231	static struct clk mstp_clks[MSTP_NR] = {
9ced1d47 KM	232	[MSTP1031] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 31, MSTPSR10, 0), /* SCU0 */
	233	[MSTP1030] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 30, MSTPSR10, 0), /* SCU1 */
	234	[MSTP1029] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 29, MSTPSR10, 0), /* SCU2 */
	235	[MSTP1028] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 28, MSTPSR10, 0), /* SCU3 */
	236	[MSTP1027] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 27, MSTPSR10, 0), /* SCU4 */
	237	[MSTP1026] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 26, MSTPSR10, 0), /* SCU5 */
	238	[MSTP1025] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 25, MSTPSR10, 0), /* SCU6 */
	239	[MSTP1024] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 24, MSTPSR10, 0), /* SCU7 */
	240	[MSTP1023] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 23, MSTPSR10, 0), /* SCU8 */
	241	[MSTP1022] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 22, MSTPSR10, 0), /* SCU9 */
	242	[MSTP1017] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 17, MSTPSR10, 0), /* SCU */
cb9ec3ad SK	243	[MSTP1015] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 15, MSTPSR10, 0), /* SSI0 */
	244	[MSTP1014] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 14, MSTPSR10, 0), /* SSI1 */
	245	[MSTP1013] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 13, MSTPSR10, 0), /* SSI2 */
	246	[MSTP1012] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 12, MSTPSR10, 0), /* SSI3 */
	247	[MSTP1011] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 11, MSTPSR10, 0), /* SSI4 */
	248	[MSTP1010] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 10, MSTPSR10, 0), /* SSI5 */
	249	[MSTP1009] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 9, MSTPSR10, 0), /* SSI6 */
	250	[MSTP1008] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 8, MSTPSR10, 0), /* SSI7 */
	251	[MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
	252	[MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
	253	[MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
ab077bfd LP	254	[MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
	255	[MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
	256	[MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
	257	[MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
cb9ec3ad	258	[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
64b7f9ac VB	259	[MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
64b7f9ac VB	260	[MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
cb9ec3ad	261	[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
b89dfdfa VB	262	[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
	263	[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
	264	[MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */
	265	[MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 8, MSTPSR8, 0), /* VIN3 */
cb9ec3ad SK	266	[MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
	267	[MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
	268	[MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
	269	[MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
	270	[MSTP722] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 22, MSTPSR7, 0), /* DU2 */
	271	[MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
	272	[MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
	273	[MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */
	274	[MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
	275	[MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
012a7069	276	[MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
cb9ec3ad	277	[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
f5b2947e KM	278	[MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
f5b2947e KM	279	[MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
cb9ec3ad SK	280	[MSTP315] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, MSTPSR3, 0), /* MMC0 */
	281	[MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
	282	[MSTP313] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD1], SMSTPCR3, 13, MSTPSR3, 0), /* SDHI1 */
	283	[MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI2 */
	284	[MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD3], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI3 */
	285	[MSTP305] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, MSTPSR3, 0), /* MMC1 */
	286	[MSTP304] = SH_CLK_MSTP32_STS(&cp_clk, SMSTPCR3, 4, MSTPSR3, 0), /* TPU0 */
	287	[MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
	288	[MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
	289	[MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
	290	[MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
	291	[MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
	292	[MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
	293	[MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
0468b2d6 MD	294	};
	295
	296	static struct clk_lookup lookups[] = {
8d100c04 KM	297
	298	/* main clocks */
	299	CLKDEV_CON_ID("extal", &extal_clk),
	300	CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
	301	CLKDEV_CON_ID("main", &main_clk),
	302	CLKDEV_CON_ID("pll1", &pll1_clk),
	303	CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
	304	CLKDEV_CON_ID("pll3", &pll3_clk),
	305	CLKDEV_CON_ID("zg", &zg_clk),
	306	CLKDEV_CON_ID("zx", &zx_clk),
	307	CLKDEV_CON_ID("zs", &zs_clk),
	308	CLKDEV_CON_ID("hp", &hp_clk),
	309	CLKDEV_CON_ID("i", &i_clk),
	310	CLKDEV_CON_ID("b", &b_clk),
	311	CLKDEV_CON_ID("lb", &lb_clk),
	312	CLKDEV_CON_ID("p", &p_clk),
	313	CLKDEV_CON_ID("cl", &cl_clk),
	314	CLKDEV_CON_ID("m2", &m2_clk),
	315	CLKDEV_CON_ID("imp", &imp_clk),
	316	CLKDEV_CON_ID("rclk", &rclk_clk),
	317	CLKDEV_CON_ID("oscclk", &oscclk_clk),
	318	CLKDEV_CON_ID("zb3", &zb3_clk),
	319	CLKDEV_CON_ID("zb3d2", &zb3d2_clk),
	320	CLKDEV_CON_ID("ddr", &ddr_clk),
	321	CLKDEV_CON_ID("mp", &mp_clk),
	322	CLKDEV_CON_ID("qspi", &qspi_clk),
	323	CLKDEV_CON_ID("cp", &cp_clk),
	324
9f13ee6f KM	325	/* DIV4 */
9f13ee6f KM	326	CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]),
9f13ee6f	327
46632512	328	/* DIV6 */
46632512 KM	329	CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]),
	330	CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
	331
8d100c04	332	/* MSTP */
b3cc52eb	333	CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
55d9fab2 MD	334	CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
	335	CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
	336	CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
	337	CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
	338	CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
	339	CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
	340	CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
	341	CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
729cb826 UH	342	CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
729cb826 UH	343	CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
db455c78	344	CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
db455c78	345	CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
db455c78	346	CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
db455c78	347	CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
9b0b9c01	348	CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
b89dfdfa VB	349	CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
	350	CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
	351	CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
	352	CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
a4b91be0	353	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
f5b2947e KM	354	CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
f5b2947e KM	355	CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
018222f5	356	CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
018222f5	357	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
018222f5	358	CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
018222f5	359	CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
018222f5	360	CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
018222f5	361	CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
3dd3b1cf	362	CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
65779cb4	363	CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
012a7069 VB	364	CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
	365	CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
	366	CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
64b7f9ac VB	367	CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
64b7f9ac VB	368	CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
eb7a9174 KM	369
eb7a9174 KM	370	/* ICK */
711ee6c8	371	CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]),
65779cb4	372	CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
eb7a9174 KM	373	CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
	374	CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
	375	CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
	376	CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
	377	CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
c7c2ec3a KM	378	CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
	379	CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
	380	CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
	381	CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
932616ee KM	382	CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP1031]),
	383	CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP1030]),
	384	CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP1029]),
	385	CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP1028]),
	386	CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP1027]),
	387	CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP1026]),
	388	CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP1025]),
	389	CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP1024]),
	390	CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP1023]),
	391	CLKDEV_ICK_ID("src.9", "rcar_sound", &mstp_clks[MSTP1022]),
b3cc52eb KM	392	CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
	393	CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
	394	CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
	395	CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
	396	CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
	397	CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
	398	CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
	399	CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
	400	CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
	401	CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
eb7a9174	402
0468b2d6 MD	403	};
0468b2d6 MD	404
8d100c04 KM	405	#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
	406	extal_clk.rate = e * 1000 * 1000; \
	407	main_clk.parent = m; \
	408	SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
	409	if (mode & MD(19)) \
	410	SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
	411	else \
	412	SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
	413
	414
0468b2d6 MD	415	void __init r8a7790_clock_init(void)
0468b2d6 MD	416	{
50c517d9	417	u32 mode = rcar_gen2_read_mode_pins();
0468b2d6 MD	418	int k, ret = 0;
0468b2d6 MD	419
8d100c04 KM	420	switch (mode & (MD(14) \| MD(13))) {
	421	case 0:
	422	R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
	423	break;
	424	case MD(13):
	425	R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
	426	break;
	427	case MD(14):
31ac8e47	428	R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
8d100c04 KM	429	break;
8d100c04 KM	430	case MD(13) \| MD(14):
31ac8e47	431	R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
8d100c04 KM	432	break;
	433	}
	434
	435	if (mode & (MD(18)))
	436	SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
	437	else
	438	SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
	439
	440	if ((mode & (MD(3) \| MD(2) \| MD(1))) == MD(2))
	441	SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
	442	else
	443	SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
	444
0468b2d6 MD	445	for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
	446	ret = clk_register(main_clks[k]);
	447
9f13ee6f KM	448	if (!ret)
	449	ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
	450
46632512 KM	451	if (!ret)
	452	ret = sh_clk_div6_register(div6_clks, DIV6_NR);
	453
0468b2d6 MD	454	if (!ret)
	455	ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
	456
	457	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
	458
	459	if (!ret)
	460	shmobile_clk_init();
	461	else
	462	panic("failed to setup r8a7790 clocks\n");
	463	}