[linux-2.6-block.git] / arch / arm / mach-sa1100 / neponset.c

// SPDX-License-Identifier: GPL-2.0
/*
 * linux/arch/arm/mach-sa1100/neponset.c
 */
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/gpio-reg.h>
#include <linux/gpio/machine.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_data/sa11x0-serial.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/serial_core.h>
#include <linux/slab.h>
#include <linux/smc91x.h>

#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/hardware/sa1111.h>
#include <linux/sizes.h>

#include <mach/hardware.h>
#include <mach/assabet.h>
#include <mach/neponset.h>
#include <mach/irqs.h>

#define NEP_IRQ_SMC91X	0
#define NEP_IRQ_USAR	1
#define NEP_IRQ_SA1111	2
#define NEP_IRQ_NR	3

#define WHOAMI		0x00
#define LEDS		0x10
#define SWPK		0x20
#define IRR		0x24
#define KP_Y_IN		0x80
#define KP_X_OUT	0x90
#define NCR_0		0xa0
#define MDM_CTL_0	0xb0
#define MDM_CTL_1	0xb4
#define AUD_CTL		0xc0

#define IRR_ETHERNET	(1 << 0)
#define IRR_USAR	(1 << 1)
#define IRR_SA1111	(1 << 2)

#define NCR_NGPIO	7

#define MDM_CTL0_RTS1	(1 << 0)
#define MDM_CTL0_DTR1	(1 << 1)
#define MDM_CTL0_RTS2	(1 << 2)
#define MDM_CTL0_DTR2	(1 << 3)
#define MDM_CTL0_NGPIO	4

#define MDM_CTL1_CTS1	(1 << 0)
#define MDM_CTL1_DSR1	(1 << 1)
#define MDM_CTL1_DCD1	(1 << 2)
#define MDM_CTL1_CTS2	(1 << 3)
#define MDM_CTL1_DSR2	(1 << 4)
#define MDM_CTL1_DCD2	(1 << 5)
#define MDM_CTL1_NGPIO	6

#define AUD_SEL_1341	(1 << 0)
#define AUD_MUTE_1341	(1 << 1)
#define AUD_NGPIO	2

extern void sa1110_mb_disable(void);

#define to_neponset_gpio_chip(x) container_of(x, struct neponset_gpio_chip, gc)

static const char *neponset_ncr_names[] = {
	"gp01_off", "tp_power", "ms_power", "enet_osc",
	"spi_kb_wk_up", "a0vpp", "a1vpp"
};

static const char *neponset_mdmctl0_names[] = {
	"rts3", "dtr3", "rts1", "dtr1",
};

static const char *neponset_mdmctl1_names[] = {
	"cts3", "dsr3", "dcd3", "cts1", "dsr1", "dcd1"
};

static const char *neponset_aud_names[] = {
	"sel_1341", "mute_1341",
};

struct neponset_drvdata {
	void __iomem *base;
	struct platform_device *sa1111;
	struct platform_device *smc91x;
	unsigned irq_base;
	struct gpio_chip *gpio[4];
};

static struct gpiod_lookup_table neponset_pcmcia_table = {
	.dev_id = "1800",
	.table = {
		GPIO_LOOKUP("sa1111", 1, "a0vcc", GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP("sa1111", 0, "a1vcc", GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP("neponset-ncr", 5, "a0vpp", GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP("neponset-ncr", 6, "a1vpp", GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP("sa1111", 2, "b0vcc", GPIO_ACTIVE_HIGH),
		GPIO_LOOKUP("sa1111", 3, "b1vcc", GPIO_ACTIVE_HIGH),
		{ },
	},
};

static struct neponset_drvdata *nep;

void neponset_ncr_frob(unsigned int mask, unsigned int val)
{
	struct neponset_drvdata *n = nep;
	unsigned long m = mask, v = val;

	if (nep)
		n->gpio[0]->set_multiple(n->gpio[0], &m, &v);
	else
		WARN(1, "nep unset\n");
}
EXPORT_SYMBOL(neponset_ncr_frob);

static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
{
	struct neponset_drvdata *n = nep;
	unsigned long mask, val = 0;

	if (!n)
		return;

	if (port->mapbase == _Ser1UTCR0) {
		mask = MDM_CTL0_RTS2 | MDM_CTL0_DTR2;

		if (!(mctrl & TIOCM_RTS))
			val |= MDM_CTL0_RTS2;

		if (!(mctrl & TIOCM_DTR))
			val |= MDM_CTL0_DTR2;
	} else if (port->mapbase == _Ser3UTCR0) {
		mask = MDM_CTL0_RTS1 | MDM_CTL0_DTR1;

		if (!(mctrl & TIOCM_RTS))
			val |= MDM_CTL0_RTS1;

		if (!(mctrl & TIOCM_DTR))
			val |= MDM_CTL0_DTR1;
	}

	n->gpio[1]->set_multiple(n->gpio[1], &mask, &val);
}

static u_int neponset_get_mctrl(struct uart_port *port)
{
	void __iomem *base = nep->base;
	u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
	u_int mdm_ctl1;

	if (!base)
		return ret;

	mdm_ctl1 = readb_relaxed(base + MDM_CTL_1);
	if (port->mapbase == _Ser1UTCR0) {
		if (mdm_ctl1 & MDM_CTL1_DCD2)
			ret &= ~TIOCM_CD;
		if (mdm_ctl1 & MDM_CTL1_CTS2)
			ret &= ~TIOCM_CTS;
		if (mdm_ctl1 & MDM_CTL1_DSR2)
			ret &= ~TIOCM_DSR;
	} else if (port->mapbase == _Ser3UTCR0) {
		if (mdm_ctl1 & MDM_CTL1_DCD1)
			ret &= ~TIOCM_CD;
		if (mdm_ctl1 & MDM_CTL1_CTS1)
			ret &= ~TIOCM_CTS;
		if (mdm_ctl1 & MDM_CTL1_DSR1)
			ret &= ~TIOCM_DSR;
	}

	return ret;
}

static struct sa1100_port_fns neponset_port_fns = {
	.set_mctrl	= neponset_set_mctrl,
	.get_mctrl	= neponset_get_mctrl,
};

/*
 * Install handler for Neponset IRQ.  Note that we have to loop here
 * since the ETHERNET and USAR IRQs are level based, and we need to
 * ensure that the IRQ signal is deasserted before returning.  This
 * is rather unfortunate.
 */
static void neponset_irq_handler(struct irq_desc *desc)
{
	struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
	unsigned int irr;

	while (1) {
		/*
		 * Acknowledge the parent IRQ.
		 */
		desc->irq_data.chip->irq_ack(&desc->irq_data);

		/*
		 * Read the interrupt reason register.  Let's have all
		 * active IRQ bits high.  Note: there is a typo in the
		 * Neponset user's guide for the SA1111 IRR level.
		 */
		irr = readb_relaxed(d->base + IRR);
		irr ^= IRR_ETHERNET | IRR_USAR;

		if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
			break;

		/*
		 * Since there is no individual mask, we have to
		 * mask the parent IRQ.  This is safe, since we'll
		 * recheck the register for any pending IRQs.
		 */
		if (irr & (IRR_ETHERNET | IRR_USAR)) {
			desc->irq_data.chip->irq_mask(&desc->irq_data);

			/*
			 * Ack the interrupt now to prevent re-entering
			 * this neponset handler.  Again, this is safe
			 * since we'll check the IRR register prior to
			 * leaving.
			 */
			desc->irq_data.chip->irq_ack(&desc->irq_data);

			if (irr & IRR_ETHERNET)
				generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);

			if (irr & IRR_USAR)
				generic_handle_irq(d->irq_base + NEP_IRQ_USAR);

			desc->irq_data.chip->irq_unmask(&desc->irq_data);
		}

		if (irr & IRR_SA1111)
			generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
	}
}

/* Yes, we really do not have any kind of masking or unmasking */
static void nochip_noop(struct irq_data *irq)
{
}

static struct irq_chip nochip = {
	.name = "neponset",
	.irq_ack = nochip_noop,
	.irq_mask = nochip_noop,
	.irq_unmask = nochip_noop,
};

static int neponset_init_gpio(struct gpio_chip **gcp,
	struct device *dev, const char *label, void __iomem *reg,
	unsigned num, bool in, const char *const * names)
{
	struct gpio_chip *gc;

	gc = gpio_reg_init(dev, reg, -1, num, label, in ? 0xffffffff : 0,
			   readl_relaxed(reg), names, NULL, NULL);
	if (IS_ERR(gc))
		return PTR_ERR(gc);

	*gcp = gc;

	return 0;
}

static struct sa1111_platform_data sa1111_info = {
	.disable_devs	= SA1111_DEVID_PS2_MSE,
};

static int neponset_probe(struct platform_device *dev)
{
	struct neponset_drvdata *d;
	struct resource *nep_res, *sa1111_res, *smc91x_res;
	struct resource sa1111_resources[] = {
		DEFINE_RES_MEM(0x40000000, SZ_8K),
		{ .flags = IORESOURCE_IRQ },
	};
	struct platform_device_info sa1111_devinfo = {
		.parent = &dev->dev,
		.name = "sa1111",
		.id = 0,
		.res = sa1111_resources,
		.num_res = ARRAY_SIZE(sa1111_resources),
		.data = &sa1111_info,
		.size_data = sizeof(sa1111_info),
		.dma_mask = 0xffffffffUL,
	};
	struct resource smc91x_resources[] = {
		DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
			0x02000000, "smc91x-regs"),
		DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
			0x02000000, "smc91x-attrib"),
		{ .flags = IORESOURCE_IRQ },
	};
	struct smc91x_platdata smc91x_platdata = {
		.flags = SMC91X_USE_8BIT | SMC91X_IO_SHIFT_2 | SMC91X_NOWAIT,
	};
	struct platform_device_info smc91x_devinfo = {
		.parent = &dev->dev,
		.name = "smc91x",
		.id = 0,
		.res = smc91x_resources,
		.num_res = ARRAY_SIZE(smc91x_resources),
		.data = &smc91x_platdata,
		.size_data = sizeof(smc91x_platdata),
	};
	int ret, irq;

	if (nep)
		return -EBUSY;

	irq = ret = platform_get_irq(dev, 0);
	if (ret < 0)
		goto err_alloc;

	nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
	sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
	if (!nep_res || !smc91x_res || !sa1111_res) {
		ret = -ENXIO;
		goto err_alloc;
	}

	d = kzalloc(sizeof(*d), GFP_KERNEL);
	if (!d) {
		ret = -ENOMEM;
		goto err_alloc;
	}

	d->base = ioremap(nep_res->start, SZ_4K);
	if (!d->base) {
		ret = -ENOMEM;
		goto err_ioremap;
	}

	if (readb_relaxed(d->base + WHOAMI) != 0x11) {
		dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
			 readb_relaxed(d->base + WHOAMI));
		ret = -ENODEV;
		goto err_id;
	}

	ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
	if (ret <= 0) {
		dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
			NEP_IRQ_NR, ret);
		if (ret == 0)
			ret = -ENOMEM;
		goto err_irq_alloc;
	}

	d->irq_base = ret;

	irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
		handle_simple_irq);
	irq_clear_status_flags(d->irq_base + NEP_IRQ_SMC91X, IRQ_NOREQUEST | IRQ_NOPROBE);
	irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
		handle_simple_irq);
	irq_clear_status_flags(d->irq_base + NEP_IRQ_USAR, IRQ_NOREQUEST | IRQ_NOPROBE);
	irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);

	irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
	irq_set_chained_handler_and_data(irq, neponset_irq_handler, d);

	/* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
	writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);

	neponset_init_gpio(&d->gpio[0], &dev->dev, "neponset-ncr",
			   d->base + NCR_0, NCR_NGPIO, false,
			   neponset_ncr_names);
	neponset_init_gpio(&d->gpio[1], &dev->dev, "neponset-mdm-ctl0",
			   d->base + MDM_CTL_0, MDM_CTL0_NGPIO, false,
			   neponset_mdmctl0_names);
	neponset_init_gpio(&d->gpio[2], &dev->dev, "neponset-mdm-ctl1",
			   d->base + MDM_CTL_1, MDM_CTL1_NGPIO, true,
			   neponset_mdmctl1_names);
	neponset_init_gpio(&d->gpio[3], &dev->dev, "neponset-aud-ctl",
			   d->base + AUD_CTL, AUD_NGPIO, false,
			   neponset_aud_names);

	gpiod_add_lookup_table(&neponset_pcmcia_table);

	/*
	 * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
	 * something on the Neponset activates this IRQ on sleep (eth?)
	 */
#if 0
	enable_irq_wake(irq);
#endif

	dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
		 d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
	nep = d;

	sa1100_register_uart_fns(&neponset_port_fns);

	/* Ensure that the memory bus request/grant signals are setup */
	sa1110_mb_disable();

	sa1111_resources[0].parent = sa1111_res;
	sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
	sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
	d->sa1111 = platform_device_register_full(&sa1111_devinfo);

	smc91x_resources[0].parent = smc91x_res;
	smc91x_resources[1].parent = smc91x_res;
	smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
	smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
	d->smc91x = platform_device_register_full(&smc91x_devinfo);

	platform_set_drvdata(dev, d);

	return 0;

 err_irq_alloc:
 err_id:
	iounmap(d->base);
 err_ioremap:
	kfree(d);
 err_alloc:
	return ret;
}

static int neponset_remove(struct platform_device *dev)
{
	struct neponset_drvdata *d = platform_get_drvdata(dev);
	int irq = platform_get_irq(dev, 0);

	if (!IS_ERR(d->sa1111))
		platform_device_unregister(d->sa1111);
	if (!IS_ERR(d->smc91x))
		platform_device_unregister(d->smc91x);

	gpiod_remove_lookup_table(&neponset_pcmcia_table);

	irq_set_chained_handler(irq, NULL);
	irq_free_descs(d->irq_base, NEP_IRQ_NR);
	nep = NULL;
	iounmap(d->base);
	kfree(d);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int neponset_resume(struct device *dev)
{
	struct neponset_drvdata *d = dev_get_drvdata(dev);
	int i, ret = 0;

	for (i = 0; i < ARRAY_SIZE(d->gpio); i++) {
		ret = gpio_reg_resume(d->gpio[i]);
		if (ret)
			break;
	}

	return ret;
}

static const struct dev_pm_ops neponset_pm_ops = {
	.resume_noirq = neponset_resume,
	.restore_noirq = neponset_resume,
};
#define PM_OPS &neponset_pm_ops
#else
#define PM_OPS NULL
#endif

static struct platform_driver neponset_device_driver = {
	.probe		= neponset_probe,
	.remove		= neponset_remove,
	.driver		= {
		.name	= "neponset",
		.pm	= PM_OPS,
	},
};

static int __init neponset_init(void)
{
	return platform_driver_register(&neponset_device_driver);
}

subsys_initcall(neponset_init);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1da177e4 LT	2	/*
1da177e4 LT	3	* linux/arch/arm/mach-sa1100/neponset.c
1da177e4	4	*/
9590e898	5	#include <linux/err.h>
f85fac0e RK	6	#include <linux/gpio/driver.h>
f85fac0e RK	7	#include <linux/gpio/gpio-reg.h>
e2125d05	8	#include <linux/gpio/machine.h>
1da177e4	9	#include <linux/init.h>
1da177e4	10	#include <linux/ioport.h>
ced8d21c	11	#include <linux/irq.h>
92e617d9	12	#include <linux/kernel.h>
ae14c2e2	13	#include <linux/module.h>
6920b5a7	14	#include <linux/platform_data/sa11x0-serial.h>
d052d1be	15	#include <linux/platform_device.h>
51f93390	16	#include <linux/pm.h>
92e617d9	17	#include <linux/serial_core.h>
ae14c2e2	18	#include <linux/slab.h>
b70661c7	19	#include <linux/smc91x.h>
1da177e4	20
1da177e4	21	#include <asm/mach-types.h>
1da177e4	22	#include <asm/mach/map.h>
1da177e4	23	#include <asm/hardware/sa1111.h>
87dfb311	24	#include <linux/sizes.h>
1da177e4	25
92e617d9 RK	26	#include <mach/hardware.h>
	27	#include <mach/assabet.h>
	28	#include <mach/neponset.h>
f314f33b	29	#include <mach/irqs.h>
92e617d9	30
ced8d21c RK	31	#define NEP_IRQ_SMC91X 0
	32	#define NEP_IRQ_USAR 1
	33	#define NEP_IRQ_SA1111 2
	34	#define NEP_IRQ_NR 3
	35
f942b0fd RK	36	#define WHOAMI 0x00
	37	#define LEDS 0x10
	38	#define SWPK 0x20
	39	#define IRR 0x24
	40	#define KP_Y_IN 0x80
	41	#define KP_X_OUT 0x90
	42	#define NCR_0 0xa0
	43	#define MDM_CTL_0 0xb0
	44	#define MDM_CTL_1 0xb4
	45	#define AUD_CTL 0xc0
	46
	47	#define IRR_ETHERNET (1 << 0)
	48	#define IRR_USAR (1 << 1)
	49	#define IRR_SA1111 (1 << 2)
	50
f85fac0e RK	51	#define NCR_NGPIO 7
f85fac0e RK	52
f942b0fd RK	53	#define MDM_CTL0_RTS1 (1 << 0)
	54	#define MDM_CTL0_DTR1 (1 << 1)
	55	#define MDM_CTL0_RTS2 (1 << 2)
	56	#define MDM_CTL0_DTR2 (1 << 3)
f85fac0e	57	#define MDM_CTL0_NGPIO 4
f942b0fd RK	58
	59	#define MDM_CTL1_CTS1 (1 << 0)
	60	#define MDM_CTL1_DSR1 (1 << 1)
	61	#define MDM_CTL1_DCD1 (1 << 2)
	62	#define MDM_CTL1_CTS2 (1 << 3)
	63	#define MDM_CTL1_DSR2 (1 << 4)
	64	#define MDM_CTL1_DCD2 (1 << 5)
f85fac0e	65	#define MDM_CTL1_NGPIO 6
f942b0fd RK	66
	67	#define AUD_SEL_1341 (1 << 0)
	68	#define AUD_MUTE_1341 (1 << 1)
f85fac0e	69	#define AUD_NGPIO 2
f942b0fd	70
bab50a35 RK	71	extern void sa1110_mb_disable(void);
bab50a35 RK	72
f85fac0e RK	73	#define to_neponset_gpio_chip(x) container_of(x, struct neponset_gpio_chip, gc)
	74
	75	static const char *neponset_ncr_names[] = {
	76	"gp01_off", "tp_power", "ms_power", "enet_osc",
	77	"spi_kb_wk_up", "a0vpp", "a1vpp"
	78	};
	79
	80	static const char *neponset_mdmctl0_names[] = {
	81	"rts3", "dtr3", "rts1", "dtr1",
	82	};
	83
	84	static const char *neponset_mdmctl1_names[] = {
	85	"cts3", "dsr3", "dcd3", "cts1", "dsr1", "dcd1"
	86	};
	87
	88	static const char *neponset_aud_names[] = {
	89	"sel_1341", "mute_1341",
	90	};
	91
ae14c2e2	92	struct neponset_drvdata {
f942b0fd	93	void __iomem *base;
9590e898 RK	94	struct platform_device *sa1111;
9590e898 RK	95	struct platform_device *smc91x;
ced8d21c	96	unsigned irq_base;
f85fac0e	97	struct gpio_chip *gpio[4];
ae14c2e2 RK	98	};
ae14c2e2 RK	99
e2125d05 RK	100	static struct gpiod_lookup_table neponset_pcmcia_table = {
	101	.dev_id = "1800",
	102	.table = {
	103	GPIO_LOOKUP("sa1111", 1, "a0vcc", GPIO_ACTIVE_HIGH),
	104	GPIO_LOOKUP("sa1111", 0, "a1vcc", GPIO_ACTIVE_HIGH),
	105	GPIO_LOOKUP("neponset-ncr", 5, "a0vpp", GPIO_ACTIVE_HIGH),
	106	GPIO_LOOKUP("neponset-ncr", 6, "a1vpp", GPIO_ACTIVE_HIGH),
	107	GPIO_LOOKUP("sa1111", 2, "b0vcc", GPIO_ACTIVE_HIGH),
	108	GPIO_LOOKUP("sa1111", 3, "b1vcc", GPIO_ACTIVE_HIGH),
	109	{ },
	110	},
	111	};
	112
f85fac0e	113	static struct neponset_drvdata *nep;
f942b0fd	114
6ad1b614 RK	115	void neponset_ncr_frob(unsigned int mask, unsigned int val)
6ad1b614 RK	116	{
f85fac0e RK	117	struct neponset_drvdata *n = nep;
	118	unsigned long m = mask, v = val;
	119
	120	if (nep)
	121	n->gpio[0]->set_multiple(n->gpio[0], &m, &v);
	122	else
	123	WARN(1, "nep unset\n");
6ad1b614	124	}
ef0c1484	125	EXPORT_SYMBOL(neponset_ncr_frob);
6ad1b614	126
92e617d9 RK	127	static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
92e617d9 RK	128	{
f85fac0e RK	129	struct neponset_drvdata *n = nep;
f85fac0e RK	130	unsigned long mask, val = 0;
f942b0fd	131
f85fac0e	132	if (!n)
f942b0fd	133	return;
92e617d9 RK	134
92e617d9 RK	135	if (port->mapbase == _Ser1UTCR0) {
f85fac0e RK	136	mask = MDM_CTL0_RTS2 \| MDM_CTL0_DTR2;
	137
	138	if (!(mctrl & TIOCM_RTS))
	139	val \|= MDM_CTL0_RTS2;
	140
	141	if (!(mctrl & TIOCM_DTR))
	142	val \|= MDM_CTL0_DTR2;
92e617d9	143	} else if (port->mapbase == _Ser3UTCR0) {
f85fac0e RK	144	mask = MDM_CTL0_RTS1 \| MDM_CTL0_DTR1;
	145
	146	if (!(mctrl & TIOCM_RTS))
	147	val \|= MDM_CTL0_RTS1;
	148
	149	if (!(mctrl & TIOCM_DTR))
	150	val \|= MDM_CTL0_DTR1;
92e617d9 RK	151	}
92e617d9 RK	152
f85fac0e	153	n->gpio[1]->set_multiple(n->gpio[1], &mask, &val);
92e617d9 RK	154	}
	155
	156	static u_int neponset_get_mctrl(struct uart_port *port)
	157	{
f85fac0e	158	void __iomem *base = nep->base;
92e617d9	159	u_int ret = TIOCM_CD \| TIOCM_CTS \| TIOCM_DSR;
f942b0fd	160	u_int mdm_ctl1;
92e617d9	161
f942b0fd RK	162	if (!base)
	163	return ret;
	164
	165	mdm_ctl1 = readb_relaxed(base + MDM_CTL_1);
92e617d9 RK	166	if (port->mapbase == _Ser1UTCR0) {
	167	if (mdm_ctl1 & MDM_CTL1_DCD2)
	168	ret &= ~TIOCM_CD;
	169	if (mdm_ctl1 & MDM_CTL1_CTS2)
	170	ret &= ~TIOCM_CTS;
	171	if (mdm_ctl1 & MDM_CTL1_DSR2)
	172	ret &= ~TIOCM_DSR;
	173	} else if (port->mapbase == _Ser3UTCR0) {
	174	if (mdm_ctl1 & MDM_CTL1_DCD1)
	175	ret &= ~TIOCM_CD;
	176	if (mdm_ctl1 & MDM_CTL1_CTS1)
	177	ret &= ~TIOCM_CTS;
	178	if (mdm_ctl1 & MDM_CTL1_DSR1)
	179	ret &= ~TIOCM_DSR;
	180	}
	181
	182	return ret;
	183	}
	184
351a102d	185	static struct sa1100_port_fns neponset_port_fns = {
92e617d9 RK	186	.set_mctrl = neponset_set_mctrl,
	187	.get_mctrl = neponset_get_mctrl,
	188	};
	189
1da177e4 LT	190	/*
	191	* Install handler for Neponset IRQ. Note that we have to loop here
	192	* since the ETHERNET and USAR IRQs are level based, and we need to
	193	* ensure that the IRQ signal is deasserted before returning. This
	194	* is rather unfortunate.
	195	*/
bd0b9ac4	196	static void neponset_irq_handler(struct irq_desc *desc)
1da177e4	197	{
ced8d21c	198	struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
1da177e4 LT	199	unsigned int irr;
	200
	201	while (1) {
1da177e4 LT	202	/*
	203	* Acknowledge the parent IRQ.
	204	*/
c4e8964e	205	desc->irq_data.chip->irq_ack(&desc->irq_data);
1da177e4 LT	206
	207	/*
	208	* Read the interrupt reason register. Let's have all
	209	* active IRQ bits high. Note: there is a typo in the
	210	* Neponset user's guide for the SA1111 IRR level.
	211	*/
f942b0fd RK	212	irr = readb_relaxed(d->base + IRR);
f942b0fd RK	213	irr ^= IRR_ETHERNET \| IRR_USAR;
1da177e4 LT	214
	215	if ((irr & (IRR_ETHERNET \| IRR_USAR \| IRR_SA1111)) == 0)
	216	break;
	217
	218	/*
	219	* Since there is no individual mask, we have to
	220	* mask the parent IRQ. This is safe, since we'll
	221	* recheck the register for any pending IRQs.
	222	*/
	223	if (irr & (IRR_ETHERNET \| IRR_USAR)) {
c4e8964e	224	desc->irq_data.chip->irq_mask(&desc->irq_data);
1da177e4	225
d782f33d RK	226	/*
	227	* Ack the interrupt now to prevent re-entering
	228	* this neponset handler. Again, this is safe
	229	* since we'll check the IRR register prior to
	230	* leaving.
	231	*/
c4e8964e	232	desc->irq_data.chip->irq_ack(&desc->irq_data);
d782f33d	233
ced8d21c RK	234	if (irr & IRR_ETHERNET)
ced8d21c RK	235	generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
1da177e4	236
ced8d21c RK	237	if (irr & IRR_USAR)
ced8d21c RK	238	generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
1da177e4	239
c4e8964e	240	desc->irq_data.chip->irq_unmask(&desc->irq_data);
1da177e4 LT	241	}
1da177e4 LT	242
ced8d21c RK	243	if (irr & IRR_SA1111)
ced8d21c RK	244	generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
1da177e4 LT	245	}
	246	}
	247
ced8d21c	248	/* Yes, we really do not have any kind of masking or unmasking */
71045520 RK	249	static void nochip_noop(struct irq_data *irq)
	250	{
	251	}
	252
	253	static struct irq_chip nochip = {
	254	.name = "neponset",
	255	.irq_ack = nochip_noop,
	256	.irq_mask = nochip_noop,
	257	.irq_unmask = nochip_noop,
	258	};
	259
f85fac0e RK	260	static int neponset_init_gpio(struct gpio_chip **gcp,
	261	struct device dev, const char label, void __iomem *reg,
	262	unsigned num, bool in, const char const names)
	263	{
	264	struct gpio_chip *gc;
	265
	266	gc = gpio_reg_init(dev, reg, -1, num, label, in ? 0xffffffff : 0,
	267	readl_relaxed(reg), names, NULL, NULL);
	268	if (IS_ERR(gc))
	269	return PTR_ERR(gc);
	270
	271	*gcp = gc;
	272
	273	return 0;
	274	}
	275
92e617d9	276	static struct sa1111_platform_data sa1111_info = {
07be45f5	277	.disable_devs = SA1111_DEVID_PS2_MSE,
92e617d9 RK	278	};
92e617d9 RK	279
351a102d	280	static int neponset_probe(struct platform_device *dev)
1da177e4	281	{
ae14c2e2	282	struct neponset_drvdata *d;
f942b0fd	283	struct resource nep_res, sa1111_res, *smc91x_res;
ced8d21c RK	284	struct resource sa1111_resources[] = {
	285	DEFINE_RES_MEM(0x40000000, SZ_8K),
	286	{ .flags = IORESOURCE_IRQ },
	287	};
9590e898 RK	288	struct platform_device_info sa1111_devinfo = {
	289	.parent = &dev->dev,
	290	.name = "sa1111",
	291	.id = 0,
	292	.res = sa1111_resources,
	293	.num_res = ARRAY_SIZE(sa1111_resources),
	294	.data = &sa1111_info,
	295	.size_data = sizeof(sa1111_info),
	296	.dma_mask = 0xffffffffUL,
	297	};
ced8d21c RK	298	struct resource smc91x_resources[] = {
	299	DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
	300	0x02000000, "smc91x-regs"),
	301	DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
	302	0x02000000, "smc91x-attrib"),
	303	{ .flags = IORESOURCE_IRQ },
	304	};
b70661c7 AB	305	struct smc91x_platdata smc91x_platdata = {
	306	.flags = SMC91X_USE_8BIT \| SMC91X_IO_SHIFT_2 \| SMC91X_NOWAIT,
	307	};
9590e898 RK	308	struct platform_device_info smc91x_devinfo = {
	309	.parent = &dev->dev,
	310	.name = "smc91x",
	311	.id = 0,
	312	.res = smc91x_resources,
	313	.num_res = ARRAY_SIZE(smc91x_resources),
04b91701 AB	314	.data = &smc91x_platdata,
04b91701 AB	315	.size_data = sizeof(smc91x_platdata),
9590e898	316	};
b6bdfcf5 RK	317	int ret, irq;
b6bdfcf5 RK	318
f85fac0e	319	if (nep)
f942b0fd RK	320	return -EBUSY;
f942b0fd RK	321
b6bdfcf5 RK	322	irq = ret = platform_get_irq(dev, 0);
	323	if (ret < 0)
	324	goto err_alloc;
ae14c2e2	325
f942b0fd	326	nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
d2e539a5 RK	327	smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
d2e539a5 RK	328	sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
f942b0fd	329	if (!nep_res \|\| !smc91x_res \|\| !sa1111_res) {
d2e539a5 RK	330	ret = -ENXIO;
	331	goto err_alloc;
	332	}
	333
ae14c2e2 RK	334	d = kzalloc(sizeof(*d), GFP_KERNEL);
	335	if (!d) {
	336	ret = -ENOMEM;
	337	goto err_alloc;
	338	}
	339
f942b0fd RK	340	d->base = ioremap(nep_res->start, SZ_4K);
	341	if (!d->base) {
	342	ret = -ENOMEM;
	343	goto err_ioremap;
	344	}
	345
	346	if (readb_relaxed(d->base + WHOAMI) != 0x11) {
	347	dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
	348	readb_relaxed(d->base + WHOAMI));
	349	ret = -ENODEV;
	350	goto err_id;
	351	}
	352
ced8d21c RK	353	ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
	354	if (ret <= 0) {
	355	dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
	356	NEP_IRQ_NR, ret);
	357	if (ret == 0)
	358	ret = -ENOMEM;
	359	goto err_irq_alloc;
	360	}
	361
	362	d->irq_base = ret;
	363
	364	irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
	365	handle_simple_irq);
e8d36d5d	366	irq_clear_status_flags(d->irq_base + NEP_IRQ_SMC91X, IRQ_NOREQUEST \| IRQ_NOPROBE);
ced8d21c RK	367	irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
ced8d21c RK	368	handle_simple_irq);
e8d36d5d	369	irq_clear_status_flags(d->irq_base + NEP_IRQ_USAR, IRQ_NOREQUEST \| IRQ_NOPROBE);
ced8d21c	370	irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
1da177e4	371
b6bdfcf5	372	irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
056c0acf	373	irq_set_chained_handler_and_data(irq, neponset_irq_handler, d);
1da177e4	374
f85fac0e RK	375	/* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
	376	writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
	377
	378	neponset_init_gpio(&d->gpio[0], &dev->dev, "neponset-ncr",
	379	d->base + NCR_0, NCR_NGPIO, false,
	380	neponset_ncr_names);
	381	neponset_init_gpio(&d->gpio[1], &dev->dev, "neponset-mdm-ctl0",
	382	d->base + MDM_CTL_0, MDM_CTL0_NGPIO, false,
	383	neponset_mdmctl0_names);
	384	neponset_init_gpio(&d->gpio[2], &dev->dev, "neponset-mdm-ctl1",
	385	d->base + MDM_CTL_1, MDM_CTL1_NGPIO, true,
	386	neponset_mdmctl1_names);
	387	neponset_init_gpio(&d->gpio[3], &dev->dev, "neponset-aud-ctl",
	388	d->base + AUD_CTL, AUD_NGPIO, false,
	389	neponset_aud_names);
	390
e2125d05 RK	391	gpiod_add_lookup_table(&neponset_pcmcia_table);
e2125d05 RK	392
1da177e4	393	/*
ced8d21c RK	394	* We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
ced8d21c RK	395	* something on the Neponset activates this IRQ on sleep (eth?)
1da177e4 LT	396	*/
1da177e4 LT	397	#if 0
b6bdfcf5	398	enable_irq_wake(irq);
1da177e4 LT	399	#endif
1da177e4 LT	400
ced8d21c RK	401	dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
ced8d21c RK	402	d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
f85fac0e	403	nep = d;
1da177e4	404
ced8d21c RK	405	sa1100_register_uart_fns(&neponset_port_fns);
ced8d21c RK	406
bab50a35 RK	407	/* Ensure that the memory bus request/grant signals are setup */
	408	sa1110_mb_disable();
	409
d2e539a5	410	sa1111_resources[0].parent = sa1111_res;
ced8d21c RK	411	sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
ced8d21c RK	412	sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
9590e898	413	d->sa1111 = platform_device_register_full(&sa1111_devinfo);
ced8d21c	414
d2e539a5 RK	415	smc91x_resources[0].parent = smc91x_res;
d2e539a5 RK	416	smc91x_resources[1].parent = smc91x_res;
ced8d21c RK	417	smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
ced8d21c RK	418	smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
9590e898 RK	419	d->smc91x = platform_device_register_full(&smc91x_devinfo);
9590e898 RK	420
ae14c2e2 RK	421	platform_set_drvdata(dev, d);
ae14c2e2 RK	422
1da177e4	423	return 0;
ae14c2e2	424
ced8d21c	425	err_irq_alloc:
f942b0fd RK	426	err_id:
	427	iounmap(d->base);
	428	err_ioremap:
ced8d21c	429	kfree(d);
ae14c2e2 RK	430	err_alloc:
ae14c2e2 RK	431	return ret;
1da177e4 LT	432	}
1da177e4 LT	433
351a102d	434	static int neponset_remove(struct platform_device *dev)
ae14c2e2 RK	435	{
ae14c2e2 RK	436	struct neponset_drvdata *d = platform_get_drvdata(dev);
b6bdfcf5	437	int irq = platform_get_irq(dev, 0);
1da177e4	438
9590e898 RK	439	if (!IS_ERR(d->sa1111))
	440	platform_device_unregister(d->sa1111);
	441	if (!IS_ERR(d->smc91x))
	442	platform_device_unregister(d->smc91x);
e2125d05 RK	443
	444	gpiod_remove_lookup_table(&neponset_pcmcia_table);
	445
b6bdfcf5	446	irq_set_chained_handler(irq, NULL);
ced8d21c	447	irq_free_descs(d->irq_base, NEP_IRQ_NR);
f85fac0e	448	nep = NULL;
f942b0fd	449	iounmap(d->base);
ae14c2e2 RK	450	kfree(d);
	451
	452	return 0;
	453	}
93160c63	454
51f93390	455	#ifdef CONFIG_PM_SLEEP
51f93390	456	static int neponset_resume(struct device *dev)
1da177e4	457	{
51f93390	458	struct neponset_drvdata *d = dev_get_drvdata(dev);
f85fac0e	459	int i, ret = 0;
ae14c2e2	460
f85fac0e RK	461	for (i = 0; i < ARRAY_SIZE(d->gpio); i++) {
	462	ret = gpio_reg_resume(d->gpio[i]);
	463	if (ret)
	464	break;
	465	}
1da177e4	466
f85fac0e	467	return ret;
1da177e4 LT	468	}
1da177e4 LT	469
51f93390	470	static const struct dev_pm_ops neponset_pm_ops = {
51f93390	471	.resume_noirq = neponset_resume,
51f93390 RK	472	.restore_noirq = neponset_resume,
	473	};
	474	#define PM_OPS &neponset_pm_ops
1da177e4	475	#else
51f93390	476	#define PM_OPS NULL
1da177e4 LT	477	#endif
1da177e4 LT	478
3ae5eaec	479	static struct platform_driver neponset_device_driver = {
1da177e4	480	.probe = neponset_probe,
351a102d	481	.remove = neponset_remove,
3ae5eaec RK	482	.driver = {
3ae5eaec RK	483	.name = "neponset",
51f93390	484	.pm = PM_OPS,
3ae5eaec	485	},
1da177e4 LT	486	};
1da177e4 LT	487
1da177e4 LT	488	static int __init neponset_init(void)
1da177e4 LT	489	{
bab50a35	490	return platform_driver_register(&neponset_device_driver);
1da177e4 LT	491	}
	492
	493	subsys_initcall(neponset_init);