[linux-block.git] / arch / arm / mach-sa1100 / irq.c

/*
 * linux/arch/arm/mach-sa1100/irq.c
 *
 * Copyright (C) 1999-2001 Nicolas Pitre
 *
 * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/ioport.h>
#include <linux/sysdev.h>

#include <mach/hardware.h>
#include <asm/mach/irq.h>

#include "generic.h"


/*
 * SA1100 GPIO edge detection for IRQs:
 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
 * Use this instead of directly setting GRER/GFER.
 */
static int GPIO_IRQ_rising_edge;
static int GPIO_IRQ_falling_edge;
static int GPIO_IRQ_mask = (1 << 11) - 1;

/*
 * To get the GPIO number from an IRQ number
 */
#define GPIO_11_27_IRQ(i)	((i) - 21)
#define GPIO11_27_MASK(irq)	(1 << GPIO_11_27_IRQ(irq))

static int sa1100_gpio_type(unsigned int irq, unsigned int type)
{
	unsigned int mask;

	if (irq <= 10)
		mask = 1 << irq;
	else
		mask = GPIO11_27_MASK(irq);

	if (type == IRQ_TYPE_PROBE) {
		if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
			return 0;
		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	}

	if (type & IRQ_TYPE_EDGE_RISING) {
		GPIO_IRQ_rising_edge |= mask;
	} else
		GPIO_IRQ_rising_edge &= ~mask;
	if (type & IRQ_TYPE_EDGE_FALLING) {
		GPIO_IRQ_falling_edge |= mask;
	} else
		GPIO_IRQ_falling_edge &= ~mask;

	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;

	return 0;
}

/*
 * GPIO IRQs must be acknowledged.  This is for IRQs from 0 to 10.
 */
static void sa1100_low_gpio_ack(unsigned int irq)
{
	GEDR = (1 << irq);
}

static void sa1100_low_gpio_mask(unsigned int irq)
{
	ICMR &= ~(1 << irq);
}

static void sa1100_low_gpio_unmask(unsigned int irq)
{
	ICMR |= 1 << irq;
}

static int sa1100_low_gpio_wake(unsigned int irq, unsigned int on)
{
	if (on)
		PWER |= 1 << irq;
	else
		PWER &= ~(1 << irq);
	return 0;
}

static struct irq_chip sa1100_low_gpio_chip = {
	.name		= "GPIO-l",
	.ack		= sa1100_low_gpio_ack,
	.mask		= sa1100_low_gpio_mask,
	.unmask		= sa1100_low_gpio_unmask,
	.set_type	= sa1100_gpio_type,
	.set_wake	= sa1100_low_gpio_wake,
};

/*
 * IRQ11 (GPIO11 through 27) handler.  We enter here with the
 * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
 * and call the handler.
 */
static void
sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned int mask;

	mask = GEDR & 0xfffff800;
	do {
		/*
		 * clear down all currently active IRQ sources.
		 * We will be processing them all.
		 */
		GEDR = mask;

		irq = IRQ_GPIO11;
		desc = irq_desc + irq;
		mask >>= 11;
		do {
			if (mask & 1)
				desc_handle_irq(irq, desc);
			mask >>= 1;
			irq++;
			desc++;
		} while (mask);

		mask = GEDR & 0xfffff800;
	} while (mask);
}

/*
 * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
 * In addition, the IRQs are all collected up into one bit in the
 * interrupt controller registers.
 */
static void sa1100_high_gpio_ack(unsigned int irq)
{
	unsigned int mask = GPIO11_27_MASK(irq);

	GEDR = mask;
}

static void sa1100_high_gpio_mask(unsigned int irq)
{
	unsigned int mask = GPIO11_27_MASK(irq);

	GPIO_IRQ_mask &= ~mask;

	GRER &= ~mask;
	GFER &= ~mask;
}

static void sa1100_high_gpio_unmask(unsigned int irq)
{
	unsigned int mask = GPIO11_27_MASK(irq);

	GPIO_IRQ_mask |= mask;

	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
}

static int sa1100_high_gpio_wake(unsigned int irq, unsigned int on)
{
	if (on)
		PWER |= GPIO11_27_MASK(irq);
	else
		PWER &= ~GPIO11_27_MASK(irq);
	return 0;
}

static struct irq_chip sa1100_high_gpio_chip = {
	.name		= "GPIO-h",
	.ack		= sa1100_high_gpio_ack,
	.mask		= sa1100_high_gpio_mask,
	.unmask		= sa1100_high_gpio_unmask,
	.set_type	= sa1100_gpio_type,
	.set_wake	= sa1100_high_gpio_wake,
};

/*
 * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
 * this is for internal IRQs i.e. from 11 to 31.
 */
static void sa1100_mask_irq(unsigned int irq)
{
	ICMR &= ~(1 << irq);
}

static void sa1100_unmask_irq(unsigned int irq)
{
	ICMR |= (1 << irq);
}

/*
 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
 */
static int sa1100_set_wake(unsigned int irq, unsigned int on)
{
	if (irq == IRQ_RTCAlrm) {
		if (on)
			PWER |= PWER_RTC;
		else
			PWER &= ~PWER_RTC;
		return 0;
	}
	return -EINVAL;
}

static struct irq_chip sa1100_normal_chip = {
	.name		= "SC",
	.ack		= sa1100_mask_irq,
	.mask		= sa1100_mask_irq,
	.unmask		= sa1100_unmask_irq,
	.set_wake	= sa1100_set_wake,
};

static struct resource irq_resource = {
	.name	= "irqs",
	.start	= 0x90050000,
	.end	= 0x9005ffff,
};

static struct sa1100irq_state {
	unsigned int	saved;
	unsigned int	icmr;
	unsigned int	iclr;
	unsigned int	iccr;
} sa1100irq_state;

static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state)
{
	struct sa1100irq_state *st = &sa1100irq_state;

	st->saved = 1;
	st->icmr = ICMR;
	st->iclr = ICLR;
	st->iccr = ICCR;

	/*
	 * Disable all GPIO-based interrupts.
	 */
	ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
		  IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
		  IC_GPIO1|IC_GPIO0);

	/*
	 * Set the appropriate edges for wakeup.
	 */
	GRER = PWER & GPIO_IRQ_rising_edge;
	GFER = PWER & GPIO_IRQ_falling_edge;
	
	/*
	 * Clear any pending GPIO interrupts.
	 */
	GEDR = GEDR;

	return 0;
}

static int sa1100irq_resume(struct sys_device *dev)
{
	struct sa1100irq_state *st = &sa1100irq_state;

	if (st->saved) {
		ICCR = st->iccr;
		ICLR = st->iclr;

		GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
		GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;

		ICMR = st->icmr;
	}
	return 0;
}

static struct sysdev_class sa1100irq_sysclass = {
	.name		= "sa11x0-irq",
	.suspend	= sa1100irq_suspend,
	.resume		= sa1100irq_resume,
};

static struct sys_device sa1100irq_device = {
	.id		= 0,
	.cls		= &sa1100irq_sysclass,
};

static int __init sa1100irq_init_devicefs(void)
{
	sysdev_class_register(&sa1100irq_sysclass);
	return sysdev_register(&sa1100irq_device);
}

device_initcall(sa1100irq_init_devicefs);

void __init sa1100_init_irq(void)
{
	unsigned int irq;

	request_resource(&iomem_resource, &irq_resource);

	/* disable all IRQs */
	ICMR = 0;

	/* all IRQs are IRQ, not FIQ */
	ICLR = 0;

	/* clear all GPIO edge detects */
	GFER = 0;
	GRER = 0;
	GEDR = -1;

	/*
	 * Whatever the doc says, this has to be set for the wait-on-irq
	 * instruction to work... on a SA1100 rev 9 at least.
	 */
	ICCR = 1;

	for (irq = 0; irq <= 10; irq++) {
		set_irq_chip(irq, &sa1100_low_gpio_chip);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	for (irq = 12; irq <= 31; irq++) {
		set_irq_chip(irq, &sa1100_normal_chip);
		set_irq_handler(irq, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	for (irq = 32; irq <= 48; irq++) {
		set_irq_chip(irq, &sa1100_high_gpio_chip);
		set_irq_handler(irq, handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	/*
	 * Install handler for GPIO 11-27 edge detect interrupts
	 */
	set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
	set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);

	sa1100_init_gpio();
}
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mach-sa1100/irq.c
	3	*
	4	* Copyright (C) 1999-2001 Nicolas Pitre
	5	*
	6	* Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12	#include <linux/init.h>
	13	#include <linux/module.h>
119c641c TG	14	#include <linux/interrupt.h>
119c641c TG	15	#include <linux/irq.h>
1da177e4	16	#include <linux/ioport.h>
1da177e4 LT	17	#include <linux/sysdev.h>
1da177e4 LT	18
a09e64fb	19	#include <mach/hardware.h>
1da177e4 LT	20	#include <asm/mach/irq.h>
	21
	22	#include "generic.h"
	23
	24
	25	/*
	26	* SA1100 GPIO edge detection for IRQs:
	27	* IRQs are generated on Falling-Edge, Rising-Edge, or both.
	28	* Use this instead of directly setting GRER/GFER.
	29	*/
	30	static int GPIO_IRQ_rising_edge;
	31	static int GPIO_IRQ_falling_edge;
	32	static int GPIO_IRQ_mask = (1 << 11) - 1;
	33
	34	/*
	35	* To get the GPIO number from an IRQ number
	36	*/
	37	#define GPIO_11_27_IRQ(i) ((i) - 21)
	38	#define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq))
	39
	40	static int sa1100_gpio_type(unsigned int irq, unsigned int type)
	41	{
	42	unsigned int mask;
	43
	44	if (irq <= 10)
	45	mask = 1 << irq;
	46	else
	47	mask = GPIO11_27_MASK(irq);
	48
6cab4860	49	if (type == IRQ_TYPE_PROBE) {
1da177e4 LT	50	if ((GPIO_IRQ_rising_edge \| GPIO_IRQ_falling_edge) & mask)
1da177e4 LT	51	return 0;
6cab4860	52	type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
1da177e4 LT	53	}
1da177e4 LT	54
6cab4860	55	if (type & IRQ_TYPE_EDGE_RISING) {
1da177e4 LT	56	GPIO_IRQ_rising_edge \|= mask;
	57	} else
	58	GPIO_IRQ_rising_edge &= ~mask;
6cab4860	59	if (type & IRQ_TYPE_EDGE_FALLING) {
1da177e4 LT	60	GPIO_IRQ_falling_edge \|= mask;
	61	} else
	62	GPIO_IRQ_falling_edge &= ~mask;
	63
	64	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	65	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
	66
	67	return 0;
	68	}
	69
	70	/*
	71	* GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10.
	72	*/
	73	static void sa1100_low_gpio_ack(unsigned int irq)
	74	{
	75	GEDR = (1 << irq);
	76	}
	77
	78	static void sa1100_low_gpio_mask(unsigned int irq)
	79	{
	80	ICMR &= ~(1 << irq);
	81	}
	82
	83	static void sa1100_low_gpio_unmask(unsigned int irq)
	84	{
	85	ICMR \|= 1 << irq;
	86	}
	87
	88	static int sa1100_low_gpio_wake(unsigned int irq, unsigned int on)
	89	{
	90	if (on)
	91	PWER \|= 1 << irq;
	92	else
	93	PWER &= ~(1 << irq);
	94	return 0;
	95	}
	96
38c677cb DB	97	static struct irq_chip sa1100_low_gpio_chip = {
38c677cb DB	98	.name = "GPIO-l",
1da177e4 LT	99	.ack = sa1100_low_gpio_ack,
	100	.mask = sa1100_low_gpio_mask,
	101	.unmask = sa1100_low_gpio_unmask,
7801907b RK	102	.set_type = sa1100_gpio_type,
7801907b RK	103	.set_wake = sa1100_low_gpio_wake,
1da177e4 LT	104	};
	105
	106	/*
	107	* IRQ11 (GPIO11 through 27) handler. We enter here with the
	108	* irq_controller_lock held, and IRQs disabled. Decode the IRQ
	109	* and call the handler.
	110	*/
	111	static void
10dd5ce2	112	sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
1da177e4 LT	113	{
	114	unsigned int mask;
	115
	116	mask = GEDR & 0xfffff800;
	117	do {
	118	/*
	119	* clear down all currently active IRQ sources.
	120	* We will be processing them all.
	121	*/
	122	GEDR = mask;
	123
	124	irq = IRQ_GPIO11;
	125	desc = irq_desc + irq;
	126	mask >>= 11;
	127	do {
	128	if (mask & 1)
0cd61b68	129	desc_handle_irq(irq, desc);
1da177e4 LT	130	mask >>= 1;
	131	irq++;
	132	desc++;
	133	} while (mask);
	134
	135	mask = GEDR & 0xfffff800;
	136	} while (mask);
	137	}
	138
	139	/*
	140	* Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
	141	* In addition, the IRQs are all collected up into one bit in the
	142	* interrupt controller registers.
	143	*/
	144	static void sa1100_high_gpio_ack(unsigned int irq)
	145	{
	146	unsigned int mask = GPIO11_27_MASK(irq);
	147
	148	GEDR = mask;
	149	}
	150
	151	static void sa1100_high_gpio_mask(unsigned int irq)
	152	{
	153	unsigned int mask = GPIO11_27_MASK(irq);
	154
	155	GPIO_IRQ_mask &= ~mask;
	156
	157	GRER &= ~mask;
	158	GFER &= ~mask;
	159	}
	160
	161	static void sa1100_high_gpio_unmask(unsigned int irq)
	162	{
	163	unsigned int mask = GPIO11_27_MASK(irq);
	164
	165	GPIO_IRQ_mask \|= mask;
	166
	167	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	168	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
	169	}
	170
	171	static int sa1100_high_gpio_wake(unsigned int irq, unsigned int on)
	172	{
	173	if (on)
	174	PWER \|= GPIO11_27_MASK(irq);
	175	else
	176	PWER &= ~GPIO11_27_MASK(irq);
	177	return 0;
	178	}
	179
38c677cb DB	180	static struct irq_chip sa1100_high_gpio_chip = {
38c677cb DB	181	.name = "GPIO-h",
1da177e4 LT	182	.ack = sa1100_high_gpio_ack,
	183	.mask = sa1100_high_gpio_mask,
	184	.unmask = sa1100_high_gpio_unmask,
7801907b RK	185	.set_type = sa1100_gpio_type,
7801907b RK	186	.set_wake = sa1100_high_gpio_wake,
1da177e4 LT	187	};
	188
	189	/*
	190	* We don't need to ACK IRQs on the SA1100 unless they're GPIOs
	191	* this is for internal IRQs i.e. from 11 to 31.
	192	*/
	193	static void sa1100_mask_irq(unsigned int irq)
	194	{
	195	ICMR &= ~(1 << irq);
	196	}
	197
	198	static void sa1100_unmask_irq(unsigned int irq)
	199	{
	200	ICMR \|= (1 << irq);
	201	}
	202
19ca5d27 RK	203	/*
	204	* Apart form GPIOs, only the RTC alarm can be a wakeup event.
	205	*/
	206	static int sa1100_set_wake(unsigned int irq, unsigned int on)
	207	{
	208	if (irq == IRQ_RTCAlrm) {
	209	if (on)
	210	PWER \|= PWER_RTC;
	211	else
	212	PWER &= ~PWER_RTC;
	213	return 0;
	214	}
	215	return -EINVAL;
	216	}
	217
38c677cb DB	218	static struct irq_chip sa1100_normal_chip = {
38c677cb DB	219	.name = "SC",
1da177e4 LT	220	.ack = sa1100_mask_irq,
	221	.mask = sa1100_mask_irq,
	222	.unmask = sa1100_unmask_irq,
19ca5d27	223	.set_wake = sa1100_set_wake,
1da177e4 LT	224	};
	225
	226	static struct resource irq_resource = {
	227	.name = "irqs",
	228	.start = 0x90050000,
	229	.end = 0x9005ffff,
	230	};
	231
	232	static struct sa1100irq_state {
	233	unsigned int saved;
	234	unsigned int icmr;
	235	unsigned int iclr;
	236	unsigned int iccr;
	237	} sa1100irq_state;
	238
	239	static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state)
	240	{
	241	struct sa1100irq_state *st = &sa1100irq_state;
	242
	243	st->saved = 1;
	244	st->icmr = ICMR;
	245	st->iclr = ICLR;
	246	st->iccr = ICCR;
	247
	248	/*
	249	* Disable all GPIO-based interrupts.
	250	*/
	251	ICMR &= ~(IC_GPIO11_27\|IC_GPIO10\|IC_GPIO9\|IC_GPIO8\|IC_GPIO7\|
	252	IC_GPIO6\|IC_GPIO5\|IC_GPIO4\|IC_GPIO3\|IC_GPIO2\|
	253	IC_GPIO1\|IC_GPIO0);
	254
	255	/*
	256	* Set the appropriate edges for wakeup.
	257	*/
	258	GRER = PWER & GPIO_IRQ_rising_edge;
	259	GFER = PWER & GPIO_IRQ_falling_edge;
	260
	261	/*
	262	* Clear any pending GPIO interrupts.
	263	*/
	264	GEDR = GEDR;
	265
	266	return 0;
	267	}
	268
	269	static int sa1100irq_resume(struct sys_device *dev)
	270	{
	271	struct sa1100irq_state *st = &sa1100irq_state;
	272
	273	if (st->saved) {
	274	ICCR = st->iccr;
	275	ICLR = st->iclr;
	276
	277	GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
	278	GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
	279
	280	ICMR = st->icmr;
	281	}
	282	return 0;
	283	}
	284
	285	static struct sysdev_class sa1100irq_sysclass = {
af5ca3f4	286	.name = "sa11x0-irq",
1da177e4 LT	287	.suspend = sa1100irq_suspend,
	288	.resume = sa1100irq_resume,
	289	};
	290
	291	static struct sys_device sa1100irq_device = {
	292	.id = 0,
	293	.cls = &sa1100irq_sysclass,
	294	};
	295
	296	static int __init sa1100irq_init_devicefs(void)
	297	{
	298	sysdev_class_register(&sa1100irq_sysclass);
	299	return sysdev_register(&sa1100irq_device);
	300	}
	301
	302	device_initcall(sa1100irq_init_devicefs);
	303
	304	void __init sa1100_init_irq(void)
	305	{
	306	unsigned int irq;
	307
	308	request_resource(&iomem_resource, &irq_resource);
	309
	310	/* disable all IRQs */
	311	ICMR = 0;
	312
	313	/* all IRQs are IRQ, not FIQ */
	314	ICLR = 0;
	315
	316	/* clear all GPIO edge detects */
	317	GFER = 0;
	318	GRER = 0;
	319	GEDR = -1;
	320
	321	/*
	322	* Whatever the doc says, this has to be set for the wait-on-irq
	323	* instruction to work... on a SA1100 rev 9 at least.
	324	*/
	325	ICCR = 1;
	326
	327	for (irq = 0; irq <= 10; irq++) {
	328	set_irq_chip(irq, &sa1100_low_gpio_chip);
10dd5ce2	329	set_irq_handler(irq, handle_edge_irq);
1da177e4 LT	330	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	331	}
	332
	333	for (irq = 12; irq <= 31; irq++) {
	334	set_irq_chip(irq, &sa1100_normal_chip);
10dd5ce2	335	set_irq_handler(irq, handle_level_irq);
1da177e4 LT	336	set_irq_flags(irq, IRQF_VALID);
	337	}
	338
	339	for (irq = 32; irq <= 48; irq++) {
	340	set_irq_chip(irq, &sa1100_high_gpio_chip);
10dd5ce2	341	set_irq_handler(irq, handle_edge_irq);
1da177e4 LT	342	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	343	}
	344
	345	/*
	346	* Install handler for GPIO 11-27 edge detect interrupts
	347	*/
	348	set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
	349	set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
45528e38 DB	350
45528e38 DB	351	sa1100_init_gpio();
1da177e4	352	}