Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | #ifndef _INCLUDE_SHANNON_H |
3 | #define _INCLUDE_SHANNON_H | |
4 | ||
5 | /* taken from comp.os.inferno Tue, 12 Sep 2000 09:21:50 GMT, | |
6 | * written by <forsyth@vitanuova.com> */ | |
7 | ||
8 | #define SHANNON_GPIO_SPI_FLASH GPIO_GPIO (0) /* Output - Driven low, enables SPI to flash */ | |
9 | #define SHANNON_GPIO_SPI_DSP GPIO_GPIO (1) /* Output - Driven low, enables SPI to DSP */ | |
10 | /* lcd lower = GPIO 2-9 */ | |
11 | #define SHANNON_GPIO_SPI_OUTPUT GPIO_GPIO (10) /* Output - SPI output to DSP */ | |
12 | #define SHANNON_GPIO_SPI_INPUT GPIO_GPIO (11) /* Input - SPI input from DSP */ | |
13 | #define SHANNON_GPIO_SPI_CLOCK GPIO_GPIO (12) /* Output - Clock for SPI */ | |
14 | #define SHANNON_GPIO_SPI_FRAME GPIO_GPIO (13) /* Output - Frame marker - not used */ | |
15 | #define SHANNON_GPIO_SPI_RTS GPIO_GPIO (14) /* Input - SPI Ready to Send */ | |
16 | #define SHANNON_IRQ_GPIO_SPI_RTS IRQ_GPIO14 | |
17 | #define SHANNON_GPIO_SPI_CTS GPIO_GPIO (15) /* Output - SPI Clear to Send */ | |
18 | #define SHANNON_GPIO_IRQ_CODEC GPIO_GPIO (16) /* in, irq from ucb1200 */ | |
19 | #define SHANNON_IRQ_GPIO_IRQ_CODEC IRQ_GPIO16 | |
20 | #define SHANNON_GPIO_DSP_RESET GPIO_GPIO (17) /* Output - Drive low to reset the DSP */ | |
21 | #define SHANNON_GPIO_CODEC_RESET GPIO_GPIO (18) /* Output - Drive low to reset the UCB1x00 */ | |
22 | #define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */ | |
23 | #define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */ | |
24 | #define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ | |
00d94979 | 25 | #define SHANNON_GPIO_DISP_EN 22 /* out */ |
1da177e4 | 26 | /* XXX GPIO 23 unaccounted for */ |
3b61436a RK |
27 | #define SHANNON_GPIO_EJECT_0 24 /* in */ |
28 | #define SHANNON_GPIO_EJECT_1 25 /* in */ | |
29 | #define SHANNON_GPIO_RDY_0 26 /* in */ | |
30 | #define SHANNON_GPIO_RDY_1 27 /* in */ | |
1da177e4 LT |
31 | |
32 | /* MCP UCB codec GPIO pins... */ | |
33 | ||
34 | #define SHANNON_UCB_GPIO_BACKLIGHT 9 | |
35 | #define SHANNON_UCB_GPIO_BRIGHT_MASK 7 | |
36 | #define SHANNON_UCB_GPIO_BRIGHT 6 | |
37 | #define SHANNON_UCB_GPIO_CONTRAST_MASK 0x3f | |
38 | #define SHANNON_UCB_GPIO_CONTRAST 0 | |
39 | ||
40 | #endif |