[linux-2.6-block.git] / arch / arm / mach-sa1100 / clock.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  linux/arch/arm/mach-sa1100/clock.c
 */
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/spinlock.h>

#include <mach/hardware.h>
#include <mach/generic.h>

static const char * const clk_tucr_parents[] = {
	"clk32768", "clk3686400",
};

static DEFINE_SPINLOCK(tucr_lock);

static int clk_gpio27_enable(struct clk_hw *hw)
{
	unsigned long flags;

	/*
	 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
	 * (SA-1110 Developer's Manual, section 9.1.2.1)
	 */
	local_irq_save(flags);
	GAFR |= GPIO_32_768kHz;
	GPDR |= GPIO_32_768kHz;
	local_irq_restore(flags);

	return 0;
}

static void clk_gpio27_disable(struct clk_hw *hw)
{
	unsigned long flags;

	local_irq_save(flags);
	GPDR &= ~GPIO_32_768kHz;
	GAFR &= ~GPIO_32_768kHz;
	local_irq_restore(flags);
}

static const struct clk_ops clk_gpio27_ops = {
	.enable = clk_gpio27_enable,
	.disable = clk_gpio27_disable,
};

static const char * const clk_gpio27_parents[] = {
	"tucr-mux",
};

static const struct clk_init_data clk_gpio27_init_data __initconst = {
	.name = "gpio27",
	.ops = &clk_gpio27_ops,
	.parent_names = clk_gpio27_parents,
	.num_parents = ARRAY_SIZE(clk_gpio27_parents),
};

/*
 * Derived from the table 8-1 in the SA1110 manual, the MPLL appears to
 * multiply its input rate by 4 x (4 + PPCR).  This calculation gives
 * the exact rate.  The figures given in the table are the rates rounded
 * to 100kHz.  Stick with sa11x0_getspeed() for the time being.
 */
static unsigned long clk_mpll_recalc_rate(struct clk_hw *hw,
	unsigned long prate)
{
	return sa11x0_getspeed(0) * 1000;
}

static const struct clk_ops clk_mpll_ops = {
	.recalc_rate = clk_mpll_recalc_rate,
};

static const char * const clk_mpll_parents[] = {
	"clk3686400",
};

static const struct clk_init_data clk_mpll_init_data __initconst = {
	.name = "mpll",
	.ops = &clk_mpll_ops,
	.parent_names = clk_mpll_parents,
	.num_parents = ARRAY_SIZE(clk_mpll_parents),
	.flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL,
};

int __init sa11xx_clk_init(void)
{
	struct clk_hw *hw;
	int ret;

	hw = clk_hw_register_fixed_rate(NULL, "clk32768", NULL, 0, 32768);
	if (IS_ERR(hw))
		return PTR_ERR(hw);

	clk_hw_register_clkdev(hw, NULL, "sa1100-rtc");

	hw = clk_hw_register_fixed_rate(NULL, "clk3686400", NULL, 0, 3686400);
	if (IS_ERR(hw))
		return PTR_ERR(hw);

	clk_hw_register_clkdev(hw, "OSTIMER0", NULL);

	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
	if (!hw)
		return -ENOMEM;
	hw->init = &clk_mpll_init_data;
	ret = clk_hw_register(NULL, hw);
	if (ret) {
		kfree(hw);
		return ret;
	}

	clk_hw_register_clkdev(hw, NULL, "sa11x0-fb");
	clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia");
	clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.0");
	clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.1");
	clk_hw_register_clkdev(hw, NULL, "1800");

	hw = clk_hw_register_mux(NULL, "tucr-mux", clk_tucr_parents,
				 ARRAY_SIZE(clk_tucr_parents), 0,
				 (void __iomem *)&TUCR, FShft(TUCR_TSEL),
				 FAlnMsk(TUCR_TSEL), 0, &tucr_lock);
	clk_set_rate(hw->clk, 3686400);

	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
	if (!hw)
		return -ENOMEM;
	hw->init = &clk_gpio27_init_data;
	ret = clk_hw_register(NULL, hw);
	if (ret) {
		kfree(hw);
		return ret;
	}

	clk_hw_register_clkdev(hw, NULL, "sa1111.0");

	return 0;
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
97d654f8 RK	2	/*
	3	* linux/arch/arm/mach-sa1100/clock.c
	4	*/
97d654f8	5	#include <linux/kernel.h>
97d654f8 RK	6	#include <linux/errno.h>
97d654f8 RK	7	#include <linux/err.h>
97d654f8	8	#include <linux/clk.h>
4a8f8340	9	#include <linux/clkdev.h>
d6c82046 RK	10	#include <linux/clk-provider.h>
	11	#include <linux/io.h>
	12	#include <linux/spinlock.h>
97d654f8	13
a09e64fb	14	#include <mach/hardware.h>
4faee128	15	#include <mach/generic.h>
97d654f8	16
d6c82046 RK	17	static const char * const clk_tucr_parents[] = {
d6c82046 RK	18	"clk32768", "clk3686400",
4a8f8340 JZ	19	};
4a8f8340 JZ	20
d6c82046	21	static DEFINE_SPINLOCK(tucr_lock);
77a374c2	22
d6c82046	23	static int clk_gpio27_enable(struct clk_hw *hw)
77a374c2	24	{
d6c82046	25	unsigned long flags;
77a374c2	26
5e1dbdb4 RK	27	/*
	28	* First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
	29	* (SA-1110 Developer's Manual, section 9.1.2.1)
	30	*/
d6c82046	31	local_irq_save(flags);
5e1dbdb4 RK	32	GAFR \|= GPIO_32_768kHz;
5e1dbdb4 RK	33	GPDR \|= GPIO_32_768kHz;
d6c82046 RK	34	local_irq_restore(flags);
	35
	36	return 0;
5e1dbdb4 RK	37	}
5e1dbdb4 RK	38
d6c82046	39	static void clk_gpio27_disable(struct clk_hw *hw)
5e1dbdb4	40	{
d6c82046 RK	41	unsigned long flags;
	42
	43	local_irq_save(flags);
5e1dbdb4 RK	44	GPDR &= ~GPIO_32_768kHz;
5e1dbdb4 RK	45	GAFR &= ~GPIO_32_768kHz;
d6c82046	46	local_irq_restore(flags);
5e1dbdb4 RK	47	}
5e1dbdb4 RK	48
d6c82046 RK	49	static const struct clk_ops clk_gpio27_ops = {
	50	.enable = clk_gpio27_enable,
	51	.disable = clk_gpio27_disable,
	52	};
4faee128	53
d6c82046 RK	54	static const char * const clk_gpio27_parents[] = {
	55	"tucr-mux",
	56	};
4faee128	57
d6c82046 RK	58	static const struct clk_init_data clk_gpio27_init_data __initconst = {
	59	.name = "gpio27",
	60	.ops = &clk_gpio27_ops,
	61	.parent_names = clk_gpio27_parents,
	62	.num_parents = ARRAY_SIZE(clk_gpio27_parents),
	63	};
	64
	65	/*
	66	* Derived from the table 8-1 in the SA1110 manual, the MPLL appears to
	67	* multiply its input rate by 4 x (4 + PPCR). This calculation gives
	68	* the exact rate. The figures given in the table are the rates rounded
	69	* to 100kHz. Stick with sa11x0_getspeed() for the time being.
	70	*/
	71	static unsigned long clk_mpll_recalc_rate(struct clk_hw *hw,
	72	unsigned long prate)
4faee128 DES	73	{
	74	return sa11x0_getspeed(0) * 1000;
	75	}
	76
d6c82046 RK	77	static const struct clk_ops clk_mpll_ops = {
	78	.recalc_rate = clk_mpll_recalc_rate,
	79	};
97d654f8	80
d6c82046 RK	81	static const char * const clk_mpll_parents[] = {
	82	"clk3686400",
	83	};
97d654f8	84
d6c82046 RK	85	static const struct clk_init_data clk_mpll_init_data __initconst = {
	86	.name = "mpll",
	87	.ops = &clk_mpll_ops,
	88	.parent_names = clk_mpll_parents,
	89	.num_parents = ARRAY_SIZE(clk_mpll_parents),
	90	.flags = CLK_GET_RATE_NOCACHE \| CLK_IS_CRITICAL,
	91	};
97d654f8	92
d6c82046	93	int __init sa11xx_clk_init(void)
4faee128	94	{
d6c82046 RK	95	struct clk_hw *hw;
d6c82046 RK	96	int ret;
4faee128	97
d6c82046 RK	98	hw = clk_hw_register_fixed_rate(NULL, "clk32768", NULL, 0, 32768);
	99	if (IS_ERR(hw))
	100	return PTR_ERR(hw);
4a8f8340	101
d6c82046	102	clk_hw_register_clkdev(hw, NULL, "sa1100-rtc");
4faee128	103
d6c82046 RK	104	hw = clk_hw_register_fixed_rate(NULL, "clk3686400", NULL, 0, 3686400);
	105	if (IS_ERR(hw))
	106	return PTR_ERR(hw);
4a8f8340	107
d6c82046	108	clk_hw_register_clkdev(hw, "OSTIMER0", NULL);
4faee128	109
d6c82046 RK	110	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
	111	if (!hw)
	112	return -ENOMEM;
	113	hw->init = &clk_mpll_init_data;
	114	ret = clk_hw_register(NULL, hw);
	115	if (ret) {
	116	kfree(hw);
	117	return ret;
	118	}
ee3a4020	119
d6c82046 RK	120	clk_hw_register_clkdev(hw, NULL, "sa11x0-fb");
	121	clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia");
	122	clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.0");
	123	clk_hw_register_clkdev(hw, NULL, "sa11x0-pcmcia.1");
	124	clk_hw_register_clkdev(hw, NULL, "1800");
	125
	126	hw = clk_hw_register_mux(NULL, "tucr-mux", clk_tucr_parents,
	127	ARRAY_SIZE(clk_tucr_parents), 0,
	128	(void __iomem *)&TUCR, FShft(TUCR_TSEL),
	129	FAlnMsk(TUCR_TSEL), 0, &tucr_lock);
	130	clk_set_rate(hw->clk, 3686400);
	131
	132	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
	133	if (!hw)
	134	return -ENOMEM;
	135	hw->init = &clk_gpio27_init_data;
	136	ret = clk_hw_register(NULL, hw);
	137	if (ret) {
	138	kfree(hw);
	139	return ret;
	140	}
ee3a4020	141
d6c82046	142	clk_hw_register_clkdev(hw, NULL, "sa1111.0");
4a8f8340	143
4a8f8340	144	return 0;
97d654f8	145	}